gem5::ArmISA::ISA Class Reference

#include <isa.hh>

Inheritance diagram for gem5::ArmISA::ISA:

Public Member Functions
const RegId &	mapIntRegId (RegIndex idx) const
void	clear () override
SelfDebug *	getSelfDebug () const
const ArmRelease *	getRelease () const
RegVal	readMiscRegNoEffect (RegIndex idx) const override
RegVal	readMiscReg (RegIndex idx) override
void	setMiscRegNoEffect (RegIndex idx, RegVal val) override
void	setMiscReg (RegIndex, RegVal val) override
int	flattenMiscIndex (int reg) const
int	redirectRegVHE (int misc_reg)
	Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at EL2. More...
int	snsBankedIndex64 (MiscRegIndex reg, bool ns) const
std::pair< int, int >	getMiscIndices (int misc_reg) const
bool	inSecureState () const
	Return true if the PE is in Secure state. More...
ExceptionLevel	currEL () const
	Returns the current Exception Level (EL) of the ISA object. More...
unsigned	getCurSveVecLenInBits () const
unsigned	getCurSveVecLenInBitsAtReset () const
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
void	startup () override
	startup() is the final initialization call before simulation. More...
void	setupThreadContext ()
PCStateBase *	newPCState (Addr new_inst_addr=0) const override
void	takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) override
enums::DecoderFlavor	decoderFlavor () const
	PARAMS (ArmISA)
	ISA (const Params &p)
uint64_t	getExecutingAsid () const override
bool	inUserMode () const override
void	copyRegsFrom (ThreadContext *src) override
void	handleLockedRead (const RequestPtr &req) override
void	handleLockedRead (ExecContext *xc, const RequestPtr &req) override
bool	handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) override
bool	handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) override
void	handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) override
void	handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) override
void	handleLockedSnoopHit () override
void	handleLockedSnoopHit (ExecContext *xc) override
void	globalClearExclusive () override
void	globalClearExclusive (ExecContext *xc) override
Public Member Functions inherited from gem5::BaseISA
virtual void	setThreadContext (ThreadContext *_tc)
const RegClasses &	regClasses () const
Public Member Functions inherited from gem5::SimObject
const Params &	params () const
	SimObject (const Params &p)
virtual	~SimObject ()
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regProbePoints ()
	Register probe points for this object. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from gem5::Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from gem5::statistics::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group. More...
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters. More...
virtual void	resetStats ()
	Callback to reset stats. More...
virtual void	preDumpStats ()
	Callback before stats are dumped. More...
void	addStat (statistics::Info *info)
	Register a stat with this group. More...
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block. More...
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...
void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block. More...
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)
virtual	~Named ()=default
virtual std::string	name () const

Static Public Member Functions
static SelfDebug *	getSelfDebug (ThreadContext *tc)
template<typename Elem >
static void	zeroSveVecRegUpperPart (Elem *v, unsigned eCount)
Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it. More...

Protected Member Functions
const MiscRegLUTEntryInitializer	InitReg (uint32_t reg)
void	initializeMiscRegMetadata ()
BaseISADevice &	getGenericTimer ()
BaseISADevice &	getGICv3CPUInterface ()
BaseISADevice *	getGICv3CPUInterface (ThreadContext *tc)
void	updateRegMap (CPSR cpsr)
void	clear32 (const ArmISAParams &p, const SCTLR &sctlr_rst)
void	clear64 (const ArmISAParams &p)
void	initID32 (const ArmISAParams &p)
void	initID64 (const ArmISAParams &p)
void	addressTranslation (MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
void	addressTranslation64 (MMU::ArmTranslationType tran_type, BaseMMU::Mode mode, Request::Flags flags, RegVal val)
Protected Member Functions inherited from gem5::BaseISA
	SimObject (const Params &p)
Protected Member Functions inherited from gem5::Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain. More...
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
ArmSystem *	system
const enums::DecoderFlavor	_decoderFlavor
DummyISADevice	dummyDevice
	Dummy device for to handle non-existing ISA devices. More...
BaseISADevice *	pmu
std::unique_ptr< BaseISADevice >	timer
std::unique_ptr< BaseISADevice >	gicv3CpuInterface
bool	highestELIs64
bool	haveLargeAsid64
uint8_t	physAddrRange
unsigned	sveVL
	SVE vector length in quadwords. More...
const ArmRelease *	release
	This could be either a FS or a SE release. More...
bool	impdefAsNop
	If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION. More...
SelfDebug *	selfDebug
RegVal	miscRegs [NUM_MISCREGS]
const RegId *	intRegMap
Protected Attributes inherited from gem5::BaseISA
ThreadContext *	tc = nullptr
RegClasses	_regClasses
Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Public Types inherited from gem5::BaseISA
typedef std::vector< const RegClass * >	RegClasses
Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Detailed Description

Definition at line 69 of file isa.hh.

Constructor & Destructor Documentation

ISA()

gem5::ArmISA::ISA::ISA

(

const Params &

p

)

Definition at line 81 of file isa.cc.

References gem5::BaseISA::_regClasses, gem5::ArmISA::ccRegClass(), clear(), dummyDevice, gem5::ArmISA::flatIntRegClass, gem5::X86ISA::floatRegClass, gem5::FullSystem, haveLargeAsid64, gem5::ArmSystem::haveLargeAsid64(), highestELIs64, gem5::ArmSystem::highestELIs64(), initializeMiscRegMetadata(), gem5::ArmISA::MISCREG_SCTLR_RST, gem5::ArmISA::miscRegClass, miscRegs, gem5::VegaISA::p, physAddrRange, gem5::ArmSystem::physAddrRange(), pmu, gem5::ArmISA::preUnflattenMiscReg(), release, gem5::ArmSystem::releaseFS(), selfDebug, gem5::ArmISA::BaseISADevice::setISA(), sveVL, gem5::ArmSystem::sveVL(), system, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::ArmISA::vecRegClass.

Member Function Documentation

addressTranslation()

void gem5::ArmISA::ISA::addressTranslation ( MMU::ArmTranslationType  tran_type, BaseMMU::Mode  mode, Request::Flags  flags, RegVal  val  )

protected

Definition at line 2172 of file isa.cc.

References gem5::ThreadContext::contextId(), DPRINTF, flags, gem5::Request::funcRequestorId, gem5::ArmISA::MMU::getAttr(), gem5::ArmISA::ArmFault::getFsr(), gem5::ArmISA::getMMUPtr(), gem5::ArmRelease::has(), gem5::ArmISA::MMU::HypMode, gem5::PCStateBase::instAddr(), gem5::ArmISA::ArmFault::iss(), gem5::ArmISA::ArmFault::isStage2(), gem5::ArmISA::mask, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_PAR, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::mode, gem5::NoFault, gem5::ThreadContext::pcState(), readMiscRegNoEffect(), release, gem5::ArmISA::MMU::S1S2NsTran, setMiscRegNoEffect(), gem5::BaseISA::tc, gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::ArmFault::update(), gem5::X86ISA::val, and warn_once.

Referenced by setMiscReg().

addressTranslation64()

void gem5::ArmISA::ISA::addressTranslation64 ( MMU::ArmTranslationType  tran_type, BaseMMU::Mode  mode, Request::Flags  flags, RegVal  val  )

protected

Definition at line 2121 of file isa.cc.

References gem5::ArmISA::attr, gem5::ThreadContext::contextId(), DPRINTF, flags, gem5::Request::funcRequestorId, gem5::ArmISA::MMU::getAttr(), gem5::ArmISA::ArmFault::getFsr(), gem5::ArmISA::getMMUPtr(), gem5::PCStateBase::instAddr(), gem5::ArmISA::ArmFault::iss(), gem5::ArmISA::ArmFault::isStage2(), gem5::ArmISA::mask, gem5::ArmISA::MISCREG_PAR_EL1, gem5::ArmISA::mode, gem5::NoFault, gem5::ThreadContext::pcState(), setMiscRegNoEffect(), gem5::BaseISA::tc, gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::ArmFault::update(), gem5::X86ISA::val, and warn_once.

Referenced by setMiscReg().

clear()

void gem5::ArmISA::ISA::clear ( )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 130 of file isa.cc.

References clear32(), clear64(), gem5::FullSystem, gem5::ArmISA::getMMUPtr(), gem5::ArmSystem::highestELIs64(), initID32(), initID64(), gem5::ArmISA::MMU::invalidateMiscReg(), gem5::ArmISA::MISCREG_MVFR0, gem5::ArmISA::MISCREG_MVFR1, gem5::ArmISA::MISCREG_NMRR_NS, gem5::ArmISA::MISCREG_PRRR_NS, gem5::ArmISA::MISCREG_SCTLR_RST, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::ArmISA::MISCREG_TLBTR, miscRegs, gem5::VegaISA::p, gem5::SimObject::params(), system, and gem5::BaseISA::tc.

Referenced by ISA().

clear32()

void gem5::ArmISA::ISA::clear32 ( const ArmISAParams &  p, const SCTLR &  sctlr_rst  )

protected

Definition at line 222 of file isa.cc.

References gem5::FullSystem, gem5::ArmRelease::has(), gem5::ArmISA::MISCREG_CPACR, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_FPSID, gem5::ArmISA::MISCREG_HCPTR, gem5::ArmISA::MISCREG_ID_MMFR0, gem5::ArmISA::MISCREG_MVBAR, gem5::ArmISA::MISCREG_SCR, gem5::ArmISA::MISCREG_SCTLR_NS, gem5::ArmISA::MISCREG_SCTLR_RST, gem5::ArmISA::MISCREG_SCTLR_S, gem5::ArmISA::MISCREG_TTBCR_NS, gem5::ArmISA::MISCREG_VBAR_S, miscRegs, gem5::ArmISA::MODE_USER, gem5::VegaISA::p, release, gem5::ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by clear().

clear64()

void gem5::ArmISA::ISA::clear64 ( const ArmISAParams &  p )

protected

Definition at line 274 of file isa.cc.

References gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmRelease::has(), gem5::ArmSystem::highestEL(), gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_MPIDR_EL1, gem5::ArmISA::MISCREG_RVBAR_EL1, gem5::ArmISA::MISCREG_RVBAR_EL2, gem5::ArmISA::MISCREG_RVBAR_EL3, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_SCTLR_NS, miscRegs, gem5::ArmISA::MODE_EL1H, gem5::ArmISA::MODE_EL2H, gem5::ArmISA::MODE_EL3H, panic, release, gem5::ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by clear().

copyRegsFrom()

void gem5::ArmISA::ISA::copyRegsFrom ( ThreadContext *  src )

overridevirtual

Implements gem5::BaseISA.

Definition at line 541 of file isa.cc.

References gem5::ArmISA::ccRegClass(), gem5::ArmISA::flatIntRegClass, gem5::ThreadContext::getMMUPtr(), gem5::ThreadContext::getReg(), gem5::ArmISA::i, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::NUM_MISCREGS, gem5::ThreadContext::pcState(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::BaseISA::tc, gem5::ArmISA::vecElemClass, and gem5::ArmISA::vecRegClass.

currEL()

ExceptionLevel gem5::ArmISA::ISA::currEL

(

)

const

Returns the current Exception Level (EL) of the ISA object.

Definition at line 2053 of file isa.cc.

References gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::opModeToEL(), and readMiscRegNoEffect().

Referenced by redirectRegVHE().

decoderFlavor()

enums::DecoderFlavor gem5::ArmISA::ISA::decoderFlavor ( ) const

inline

Definition at line 394 of file isa.hh.

References _decoderFlavor.

flattenMiscIndex()

int gem5::ArmISA::ISA::flattenMiscIndex ( int  reg ) const

inline

Definition at line 201 of file isa.hh.

References highestELIs64, inSecureState(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::MISCREG_BANKED, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_MAIR0, gem5::ArmISA::MISCREG_MAIR1, gem5::ArmISA::MISCREG_MUTEX, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_NMRR_MAIR1, gem5::ArmISA::MISCREG_NMRR_MAIR1_NS, gem5::ArmISA::MISCREG_NMRR_MAIR1_S, gem5::ArmISA::MISCREG_PMCCFILTR, gem5::ArmISA::MISCREG_PMSELR, gem5::ArmISA::MISCREG_PMXEVTYPER, gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_PRRR_MAIR0, gem5::ArmISA::MISCREG_PRRR_MAIR0_NS, gem5::ArmISA::MISCREG_PRRR_MAIR0_S, gem5::ArmISA::MISCREG_SPSR, gem5::ArmISA::MISCREG_SPSR_ABT, gem5::ArmISA::MISCREG_SPSR_EL1, gem5::ArmISA::MISCREG_SPSR_EL2, gem5::ArmISA::MISCREG_SPSR_EL3, gem5::ArmISA::MISCREG_SPSR_FIQ, gem5::ArmISA::MISCREG_SPSR_HYP, gem5::ArmISA::MISCREG_SPSR_IRQ, gem5::ArmISA::MISCREG_SPSR_MON, gem5::ArmISA::MISCREG_SPSR_SVC, gem5::ArmISA::MISCREG_SPSR_UND, gem5::ArmISA::MISCREG_TTBCR, miscRegs, gem5::ArmISA::MODE_ABORT, gem5::ArmISA::MODE_EL0T, gem5::ArmISA::MODE_EL1H, gem5::ArmISA::MODE_EL1T, gem5::ArmISA::MODE_EL2H, gem5::ArmISA::MODE_EL2T, gem5::ArmISA::MODE_EL3H, gem5::ArmISA::MODE_EL3T, gem5::ArmISA::MODE_FIQ, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_IRQ, gem5::ArmISA::MODE_MON, gem5::ArmISA::MODE_SVC, gem5::ArmISA::MODE_UNDEFINED, gem5::ArmISA::MODE_USER, panic, readMiscRegNoEffect(), gem5::X86ISA::reg, snsBankedIndex64(), and warn.

Referenced by getMiscIndices().

getCurSveVecLenInBits()

unsigned gem5::ArmISA::ISA::getCurSveVecLenInBits

(

)

const

Definition at line 2061 of file isa.cc.

References gem5::ArmISA::el, gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::ELIsInHost(), gem5::FullSystem, gem5::ArmRelease::has(), gem5::ArmISA::isSecure(), gem5::ArmISA::len, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::MISCREG_ZCR_EL2, gem5::ArmISA::MISCREG_ZCR_EL3, miscRegs, panic_if, release, sveVL, and gem5::BaseISA::tc.

Referenced by gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits(), and setMiscReg().

getCurSveVecLenInBitsAtReset()

unsigned gem5::ArmISA::ISA::getCurSveVecLenInBitsAtReset ( ) const

inline

Definition at line 364 of file isa.hh.

References sveVL.

getExecutingAsid()

uint64_t gem5::ArmISA::ISA::getExecutingAsid ( ) const

inlineoverridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 401 of file isa.hh.

References gem5::ArmISA::MISCREG_CONTEXTIDR, and readMiscRegNoEffect().

getGenericTimer()

BaseISADevice & gem5::ArmISA::ISA::getGenericTimer ( )

protected

Definition at line 1983 of file isa.cc.

References gem5::ThreadContext::contextId(), gem5::ArmSystem::getGenericTimer(), panic, system, gem5::BaseISA::tc, and timer.

Referenced by readMiscReg(), and setMiscReg().

getGICv3CPUInterface() [1/2]

BaseISADevice & gem5::ArmISA::ISA::getGICv3CPUInterface ( )

protected

Definition at line 2004 of file isa.cc.

References gicv3CpuInterface, panic_if, and gem5::BaseISA::tc.

Referenced by readMiscReg(), setMiscReg(), and setupThreadContext().

getGICv3CPUInterface() [2/2]

BaseISADevice * gem5::ArmISA::ISA::getGICv3CPUInterface ( ThreadContext *  tc )

protected

Definition at line 2017 of file isa.cc.

References gem5::ThreadContext::contextId(), gem5::Gicv3::getCPUInterface(), gem5::ArmSystem::getGIC(), system, and gem5::BaseISA::tc.

getMiscIndices()

std::pair<int,int> gem5::ArmISA::ISA::getMiscIndices ( int  misc_reg ) const

inline

Definition at line 334 of file isa.hh.

References flattenMiscIndex(), highestELIs64, inSecureState(), gem5::ArmISA::lookUpMiscReg, and gem5::ArmISA::MISCREG_BANKED_CHILD.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

getRelease()

const ArmRelease* gem5::ArmISA::ISA::getRelease ( ) const

inline

Definition at line 193 of file isa.hh.

References release.

Referenced by gem5::ArmISA::HaveExt(), gem5::TlbiOp::performTlbi(), and gem5::TlbiOp64::performTlbi().

getSelfDebug() [1/2]

SelfDebug* gem5::ArmISA::ISA::getSelfDebug ( ) const

inline

Definition at line 181 of file isa.hh.

References selfDebug.

Referenced by gem5::ArmISA::ArmStaticInst::activateBreakpoint(), gem5::DebugStep::execute(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), getSelfDebug(), gem5::ArmISA::MMU::translateFs(), and gem5::ArmISA::ArmFault::vectorCatch().

getSelfDebug() [2/2]

static SelfDebug* gem5::ArmISA::ISA::getSelfDebug ( ThreadContext *  tc )

inlinestatic

Definition at line 187 of file isa.hh.

References gem5::ThreadContext::getIsaPtr(), getSelfDebug(), and gem5::BaseISA::tc.

globalClearExclusive() [1/2]

void gem5::ArmISA::ISA::globalClearExclusive ( )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2372 of file isa.cc.

References DPRINTF, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::ArmISA::sendEvent(), gem5::ThreadContext::setMiscReg(), and gem5::BaseISA::tc.

globalClearExclusive() [2/2]

void gem5::ArmISA::ISA::globalClearExclusive ( ExecContext *  xc )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2386 of file isa.cc.

References DPRINTF, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::ArmISA::sendEvent(), gem5::ExecContext::setMiscReg(), and gem5::ExecContext::tcBase().

handleLockedRead() [1/2]

void gem5::ArmISA::ISA::handleLockedRead ( const RequestPtr &  req )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2282 of file isa.cc.

References DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ArmISA::MISCREG_LOCKADDR, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::Named::name(), gem5::ThreadContext::setMiscReg(), and gem5::BaseISA::tc.

handleLockedRead() [2/2]

void gem5::ArmISA::ISA::handleLockedRead ( ExecContext *  xc, const RequestPtr &  req  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2291 of file isa.cc.

References DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ArmISA::MISCREG_LOCKADDR, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::Named::name(), gem5::ExecContext::setMiscReg(), and gem5::ExecContext::tcBase().

handleLockedSnoop() [1/2]

void gem5::ArmISA::ISA::handleLockedSnoop ( ExecContext *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2276 of file isa.cc.

References gem5::ArmISA::lockedSnoopHandler(), and gem5::ExecContext::tcBase().

handleLockedSnoop() [2/2]

void gem5::ArmISA::ISA::handleLockedSnoop ( PacketPtr  pkt, Addr  cacheBlockMask  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2270 of file isa.cc.

References gem5::ArmISA::lockedSnoopHandler(), and gem5::BaseISA::tc.

handleLockedSnoopHit() [1/2]

void gem5::ArmISA::ISA::handleLockedSnoopHit ( )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2300 of file isa.cc.

References DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ArmISA::MISCREG_LOCKADDR, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::Named::name(), gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::setMiscReg(), and gem5::BaseISA::tc.

handleLockedSnoopHit() [2/2]

void gem5::ArmISA::ISA::handleLockedSnoopHit ( ExecContext *  xc )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2309 of file isa.cc.

References DPRINTF, gem5::ThreadContext::getCpuPtr(), gem5::ArmISA::MISCREG_LOCKADDR, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::Named::name(), gem5::ExecContext::readMiscReg(), gem5::ExecContext::setMiscReg(), and gem5::ExecContext::tcBase().

handleLockedWrite() [1/2]

bool gem5::ArmISA::ISA::handleLockedWrite ( const RequestPtr &  req, Addr  cacheBlockMask  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2359 of file isa.cc.

References gem5::ArmISA::lockedWriteHandler(), and gem5::BaseISA::tc.

handleLockedWrite() [2/2]

bool gem5::ArmISA::ISA::handleLockedWrite ( ExecContext *  xc, const RequestPtr &  req, Addr  cacheBlockMask  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 2365 of file isa.cc.

References gem5::ArmISA::lockedWriteHandler(), and gem5::ExecContext::tcBase().

initializeMiscRegMetadata()

void gem5::ArmISA::ISA::initializeMiscRegMetadata ( )

protected

Some registers alias with others, and therefore need to be translated. When two mapping registers are given, they are the 32b lower and upper halves, respectively, of the 64b register being mapped. aligned with reference documentation ARM DDI 0487A.i pp 1540-1543

NAM = "not architecturally mandated", from ARM DDI 0487A.i, template text "AArch64 System register ___ can be mapped to AArch32 System register ___, but this is not architecturally mandated."

Definition at line 2070 of file misc.cc.

References gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges(), gem5::ArmISA::at, gem5::ArmISA::MiscRegLUTEntryInitializer::banked(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked64(), gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild(), gem5::ArmISA::defaultFaultE2H_EL2(), gem5::ArmISA::defaultFaultE2H_EL3(), gem5::ArmISA::EL0, gem5::ArmISA::EL1, gem5::ArmISA::EL2, gem5::ArmISA::EL3, gem5::ArmISA::MiscRegLUTEntryInitializer::exceptUserMode(), gem5::ArmISA::MiscRegLUTEntryInitializer::fault(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite(), gem5::FullSystem, gem5::ArmRelease::has(), HCR_TRAP, gem5::ArmISA::MiscRegLUTEntryInitializer::highest(), gem5::ArmSystem::highestEL(), highestELIs64, gem5::ArmISA::MiscRegLUTEntryInitializer::hyp(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite(), impdefAsNop, InitReg(), gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo(), gem5::ArmISA::MISCREG_ACTLR, gem5::ArmISA::MISCREG_ACTLR_EL1, gem5::ArmISA::MISCREG_ACTLR_EL2, gem5::ArmISA::MISCREG_ACTLR_EL3, gem5::ArmISA::MISCREG_ACTLR_NS, gem5::ArmISA::MISCREG_ACTLR_S, gem5::ArmISA::MISCREG_ADFSR, gem5::ArmISA::MISCREG_ADFSR_NS, gem5::ArmISA::MISCREG_ADFSR_S, gem5::ArmISA::MISCREG_AFSR0_EL1, gem5::ArmISA::MISCREG_AFSR0_EL12, gem5::ArmISA::MISCREG_AFSR0_EL2, gem5::ArmISA::MISCREG_AFSR0_EL3, gem5::ArmISA::MISCREG_AFSR1_EL1, gem5::ArmISA::MISCREG_AFSR1_EL12, gem5::ArmISA::MISCREG_AFSR1_EL2, gem5::ArmISA::MISCREG_AFSR1_EL3, gem5::ArmISA::MISCREG_AIDR, gem5::ArmISA::MISCREG_AIDR_EL1, gem5::ArmISA::MISCREG_AIFSR, gem5::ArmISA::MISCREG_AIFSR_NS, gem5::ArmISA::MISCREG_AIFSR_S, gem5::ArmISA::MISCREG_AMAIR0, gem5::ArmISA::MISCREG_AMAIR0_NS, gem5::ArmISA::MISCREG_AMAIR0_S, gem5::ArmISA::MISCREG_AMAIR1, gem5::ArmISA::MISCREG_AMAIR1_NS, gem5::ArmISA::MISCREG_AMAIR1_S, gem5::ArmISA::MISCREG_AMAIR_EL1, gem5::ArmISA::MISCREG_AMAIR_EL12, gem5::ArmISA::MISCREG_AMAIR_EL2, gem5::ArmISA::MISCREG_AMAIR_EL3, gem5::ArmISA::MISCREG_APDAKeyHi_EL1, gem5::ArmISA::MISCREG_APDAKeyLo_EL1, gem5::ArmISA::MISCREG_APDBKeyHi_EL1, gem5::ArmISA::MISCREG_APDBKeyLo_EL1, gem5::ArmISA::MISCREG_APGAKeyHi_EL1, gem5::ArmISA::MISCREG_APGAKeyLo_EL1, gem5::ArmISA::MISCREG_APIAKeyHi_EL1, gem5::ArmISA::MISCREG_APIAKeyLo_EL1, gem5::ArmISA::MISCREG_APIBKeyHi_EL1, gem5::ArmISA::MISCREG_APIBKeyLo_EL1, gem5::ArmISA::MISCREG_AT_S12E0R_Xt, gem5::ArmISA::MISCREG_AT_S12E0W_Xt, gem5::ArmISA::MISCREG_AT_S12E1R_Xt, gem5::ArmISA::MISCREG_AT_S12E1W_Xt, gem5::ArmISA::MISCREG_AT_S1E0R_Xt, gem5::ArmISA::MISCREG_AT_S1E0W_Xt, gem5::ArmISA::MISCREG_AT_S1E1R_Xt, gem5::ArmISA::MISCREG_AT_S1E1W_Xt, gem5::ArmISA::MISCREG_AT_S1E2R_Xt, gem5::ArmISA::MISCREG_AT_S1E2W_Xt, gem5::ArmISA::MISCREG_AT_S1E3R_Xt, gem5::ArmISA::MISCREG_AT_S1E3W_Xt, gem5::ArmISA::MISCREG_ATS12NSOPR, gem5::ArmISA::MISCREG_ATS12NSOPW, gem5::ArmISA::MISCREG_ATS12NSOUR, gem5::ArmISA::MISCREG_ATS12NSOUW, gem5::ArmISA::MISCREG_ATS1CPR, gem5::ArmISA::MISCREG_ATS1CPW, gem5::ArmISA::MISCREG_ATS1CUR, gem5::ArmISA::MISCREG_ATS1CUW, gem5::ArmISA::MISCREG_ATS1HR, gem5::ArmISA::MISCREG_ATS1HW, gem5::ArmISA::MISCREG_BPIALL, gem5::ArmISA::MISCREG_BPIALLIS, gem5::ArmISA::MISCREG_BPIMVA, gem5::ArmISA::MISCREG_CBAR, gem5::ArmISA::MISCREG_CBAR_EL1, gem5::ArmISA::MISCREG_CCSIDR, gem5::ArmISA::MISCREG_CCSIDR_EL1, gem5::ArmISA::MISCREG_CLIDR, gem5::ArmISA::MISCREG_CLIDR_EL1, gem5::ArmISA::MISCREG_CNTFRQ, gem5::ArmISA::MISCREG_CNTFRQ_EL0, gem5::ArmISA::MISCREG_CNTHCTL, gem5::ArmISA::MISCREG_CNTHCTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CTL, gem5::ArmISA::MISCREG_CNTHP_CTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CVAL, gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHP_TVAL, gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_CTL_EL2, gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTKCTL, gem5::ArmISA::MISCREG_CNTKCTL_EL1, gem5::ArmISA::MISCREG_CNTKCTL_EL12, gem5::ArmISA::MISCREG_CNTP_CTL, gem5::ArmISA::MISCREG_CNTP_CTL_EL0, gem5::ArmISA::MISCREG_CNTP_CTL_EL02, gem5::ArmISA::MISCREG_CNTP_CTL_NS, gem5::ArmISA::MISCREG_CNTP_CTL_S, gem5::ArmISA::MISCREG_CNTP_CVAL, gem5::ArmISA::MISCREG_CNTP_CVAL_EL0, gem5::ArmISA::MISCREG_CNTP_CVAL_EL02, gem5::ArmISA::MISCREG_CNTP_CVAL_NS, gem5::ArmISA::MISCREG_CNTP_CVAL_S, gem5::ArmISA::MISCREG_CNTP_TVAL, gem5::ArmISA::MISCREG_CNTP_TVAL_EL0, gem5::ArmISA::MISCREG_CNTP_TVAL_EL02, gem5::ArmISA::MISCREG_CNTP_TVAL_NS, gem5::ArmISA::MISCREG_CNTP_TVAL_S, gem5::ArmISA::MISCREG_CNTPCT, gem5::ArmISA::MISCREG_CNTPCT_EL0, gem5::ArmISA::MISCREG_CNTPS_CTL_EL1, gem5::ArmISA::MISCREG_CNTPS_CVAL_EL1, gem5::ArmISA::MISCREG_CNTPS_TVAL_EL1, gem5::ArmISA::MISCREG_CNTV_CTL, gem5::ArmISA::MISCREG_CNTV_CTL_EL0, gem5::ArmISA::MISCREG_CNTV_CTL_EL02, gem5::ArmISA::MISCREG_CNTV_CVAL, gem5::ArmISA::MISCREG_CNTV_CVAL_EL0, gem5::ArmISA::MISCREG_CNTV_CVAL_EL02, gem5::ArmISA::MISCREG_CNTV_TVAL, gem5::ArmISA::MISCREG_CNTV_TVAL_EL0, gem5::ArmISA::MISCREG_CNTV_TVAL_EL02, gem5::ArmISA::MISCREG_CNTVCT, gem5::ArmISA::MISCREG_CNTVCT_EL0, gem5::ArmISA::MISCREG_CNTVOFF, gem5::ArmISA::MISCREG_CNTVOFF_EL2, gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CONTEXTIDR_EL1, gem5::ArmISA::MISCREG_CONTEXTIDR_EL12, gem5::ArmISA::MISCREG_CONTEXTIDR_EL2, gem5::ArmISA::MISCREG_CONTEXTIDR_NS, gem5::ArmISA::MISCREG_CONTEXTIDR_S, gem5::ArmISA::MISCREG_CP15DMB, gem5::ArmISA::MISCREG_CP15DSB, gem5::ArmISA::MISCREG_CP15ISB, gem5::ArmISA::MISCREG_CPACR, gem5::ArmISA::MISCREG_CPACR_EL1, gem5::ArmISA::MISCREG_CPACR_EL12, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_CPSR_MODE, gem5::ArmISA::MISCREG_CPSR_Q, gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_CPTR_EL3, gem5::ArmISA::MISCREG_CPUACTLR_EL1, gem5::ArmISA::MISCREG_CPUECTLR_EL1, gem5::ArmISA::MISCREG_CPUMERRSR, gem5::ArmISA::MISCREG_CPUMERRSR_EL1, gem5::ArmISA::MISCREG_CSSELR, gem5::ArmISA::MISCREG_CSSELR_EL1, gem5::ArmISA::MISCREG_CSSELR_NS, gem5::ArmISA::MISCREG_CSSELR_S, gem5::ArmISA::MISCREG_CTR, gem5::ArmISA::MISCREG_CTR_EL0, gem5::ArmISA::MISCREG_CURRENTEL, gem5::ArmISA::MISCREG_DACR, gem5::ArmISA::MISCREG_DACR32_EL2, gem5::ArmISA::MISCREG_DACR_NS, gem5::ArmISA::MISCREG_DACR_S, gem5::ArmISA::MISCREG_DAIF, gem5::ArmISA::MISCREG_DBGAUTHSTATUS, gem5::ArmISA::MISCREG_DBGAUTHSTATUS_EL1, gem5::ArmISA::MISCREG_DBGBCR0, gem5::ArmISA::MISCREG_DBGBCR0_EL1, gem5::ArmISA::MISCREG_DBGBCR1, gem5::ArmISA::MISCREG_DBGBCR10, gem5::ArmISA::MISCREG_DBGBCR10_EL1, gem5::ArmISA::MISCREG_DBGBCR11, gem5::ArmISA::MISCREG_DBGBCR11_EL1, gem5::ArmISA::MISCREG_DBGBCR12, gem5::ArmISA::MISCREG_DBGBCR12_EL1, gem5::ArmISA::MISCREG_DBGBCR13, gem5::ArmISA::MISCREG_DBGBCR13_EL1, gem5::ArmISA::MISCREG_DBGBCR14, gem5::ArmISA::MISCREG_DBGBCR14_EL1, gem5::ArmISA::MISCREG_DBGBCR15, gem5::ArmISA::MISCREG_DBGBCR15_EL1, gem5::ArmISA::MISCREG_DBGBCR1_EL1, gem5::ArmISA::MISCREG_DBGBCR2, gem5::ArmISA::MISCREG_DBGBCR2_EL1, gem5::ArmISA::MISCREG_DBGBCR3, gem5::ArmISA::MISCREG_DBGBCR3_EL1, gem5::ArmISA::MISCREG_DBGBCR4, gem5::ArmISA::MISCREG_DBGBCR4_EL1, gem5::ArmISA::MISCREG_DBGBCR5, gem5::ArmISA::MISCREG_DBGBCR5_EL1, gem5::ArmISA::MISCREG_DBGBCR6, gem5::ArmISA::MISCREG_DBGBCR6_EL1, gem5::ArmISA::MISCREG_DBGBCR7, gem5::ArmISA::MISCREG_DBGBCR7_EL1, gem5::ArmISA::MISCREG_DBGBCR8, gem5::ArmISA::MISCREG_DBGBCR8_EL1, gem5::ArmISA::MISCREG_DBGBCR9, gem5::ArmISA::MISCREG_DBGBCR9_EL1, gem5::ArmISA::MISCREG_DBGBVR0, gem5::ArmISA::MISCREG_DBGBVR0_EL1, gem5::ArmISA::MISCREG_DBGBVR1, gem5::ArmISA::MISCREG_DBGBVR10, gem5::ArmISA::MISCREG_DBGBVR10_EL1, gem5::ArmISA::MISCREG_DBGBVR11, gem5::ArmISA::MISCREG_DBGBVR11_EL1, gem5::ArmISA::MISCREG_DBGBVR12, gem5::ArmISA::MISCREG_DBGBVR12_EL1, gem5::ArmISA::MISCREG_DBGBVR13, gem5::ArmISA::MISCREG_DBGBVR13_EL1, gem5::ArmISA::MISCREG_DBGBVR14, gem5::ArmISA::MISCREG_DBGBVR14_EL1, gem5::ArmISA::MISCREG_DBGBVR15, gem5::ArmISA::MISCREG_DBGBVR15_EL1, gem5::ArmISA::MISCREG_DBGBVR1_EL1, gem5::ArmISA::MISCREG_DBGBVR2, gem5::ArmISA::MISCREG_DBGBVR2_EL1, gem5::ArmISA::MISCREG_DBGBVR3, gem5::ArmISA::MISCREG_DBGBVR3_EL1, gem5::ArmISA::MISCREG_DBGBVR4, gem5::ArmISA::MISCREG_DBGBVR4_EL1, gem5::ArmISA::MISCREG_DBGBVR5, gem5::ArmISA::MISCREG_DBGBVR5_EL1, gem5::ArmISA::MISCREG_DBGBVR6, gem5::ArmISA::MISCREG_DBGBVR6_EL1, gem5::ArmISA::MISCREG_DBGBVR7, gem5::ArmISA::MISCREG_DBGBVR7_EL1, gem5::ArmISA::MISCREG_DBGBVR8, gem5::ArmISA::MISCREG_DBGBVR8_EL1, gem5::ArmISA::MISCREG_DBGBVR9, gem5::ArmISA::MISCREG_DBGBVR9_EL1, gem5::ArmISA::MISCREG_DBGBXVR0, gem5::ArmISA::MISCREG_DBGBXVR1, gem5::ArmISA::MISCREG_DBGBXVR10, gem5::ArmISA::MISCREG_DBGBXVR11, gem5::ArmISA::MISCREG_DBGBXVR12, gem5::ArmISA::MISCREG_DBGBXVR13, gem5::ArmISA::MISCREG_DBGBXVR14, gem5::ArmISA::MISCREG_DBGBXVR15, gem5::ArmISA::MISCREG_DBGBXVR2, gem5::ArmISA::MISCREG_DBGBXVR3, gem5::ArmISA::MISCREG_DBGBXVR4, gem5::ArmISA::MISCREG_DBGBXVR5, gem5::ArmISA::MISCREG_DBGBXVR6, gem5::ArmISA::MISCREG_DBGBXVR7, gem5::ArmISA::MISCREG_DBGBXVR8, gem5::ArmISA::MISCREG_DBGBXVR9, gem5::ArmISA::MISCREG_DBGCLAIMCLR, gem5::ArmISA::MISCREG_DBGCLAIMCLR_EL1, gem5::ArmISA::MISCREG_DBGCLAIMSET, gem5::ArmISA::MISCREG_DBGCLAIMSET_EL1, gem5::ArmISA::MISCREG_DBGDCCINT, gem5::ArmISA::MISCREG_DBGDEVID0, gem5::ArmISA::MISCREG_DBGDEVID1, gem5::ArmISA::MISCREG_DBGDEVID2, gem5::ArmISA::MISCREG_DBGDIDR, gem5::ArmISA::MISCREG_DBGDRAR, gem5::ArmISA::MISCREG_DBGDSAR, gem5::ArmISA::MISCREG_DBGDSCRext, gem5::ArmISA::MISCREG_DBGDSCRint, gem5::ArmISA::MISCREG_DBGDTRRXext, gem5::ArmISA::MISCREG_DBGDTRRXint, gem5::ArmISA::MISCREG_DBGDTRTXext, gem5::ArmISA::MISCREG_DBGDTRTXint, gem5::ArmISA::MISCREG_DBGOSDLR, gem5::ArmISA::MISCREG_DBGOSECCR, gem5::ArmISA::MISCREG_DBGOSLAR, gem5::ArmISA::MISCREG_DBGOSLSR, gem5::ArmISA::MISCREG_DBGPRCR, gem5::ArmISA::MISCREG_DBGPRCR_EL1, gem5::ArmISA::MISCREG_DBGVCR, gem5::ArmISA::MISCREG_DBGVCR32_EL2, gem5::ArmISA::MISCREG_DBGWCR0, gem5::ArmISA::MISCREG_DBGWCR0_EL1, gem5::ArmISA::MISCREG_DBGWCR1, gem5::ArmISA::MISCREG_DBGWCR10, gem5::ArmISA::MISCREG_DBGWCR10_EL1, gem5::ArmISA::MISCREG_DBGWCR11, gem5::ArmISA::MISCREG_DBGWCR11_EL1, gem5::ArmISA::MISCREG_DBGWCR12, gem5::ArmISA::MISCREG_DBGWCR12_EL1, gem5::ArmISA::MISCREG_DBGWCR13, gem5::ArmISA::MISCREG_DBGWCR13_EL1, gem5::ArmISA::MISCREG_DBGWCR14, gem5::ArmISA::MISCREG_DBGWCR14_EL1, gem5::ArmISA::MISCREG_DBGWCR15, gem5::ArmISA::MISCREG_DBGWCR15_EL1, gem5::ArmISA::MISCREG_DBGWCR1_EL1, gem5::ArmISA::MISCREG_DBGWCR2, gem5::ArmISA::MISCREG_DBGWCR2_EL1, gem5::ArmISA::MISCREG_DBGWCR3, gem5::ArmISA::MISCREG_DBGWCR3_EL1, gem5::ArmISA::MISCREG_DBGWCR4, gem5::ArmISA::MISCREG_DBGWCR4_EL1, gem5::ArmISA::MISCREG_DBGWCR5, gem5::ArmISA::MISCREG_DBGWCR5_EL1, gem5::ArmISA::MISCREG_DBGWCR6, gem5::ArmISA::MISCREG_DBGWCR6_EL1, gem5::ArmISA::MISCREG_DBGWCR7, gem5::ArmISA::MISCREG_DBGWCR7_EL1, gem5::ArmISA::MISCREG_DBGWCR8, gem5::ArmISA::MISCREG_DBGWCR8_EL1, gem5::ArmISA::MISCREG_DBGWCR9, gem5::ArmISA::MISCREG_DBGWCR9_EL1, gem5::ArmISA::MISCREG_DBGWFAR, gem5::ArmISA::MISCREG_DBGWVR0, gem5::ArmISA::MISCREG_DBGWVR0_EL1, gem5::ArmISA::MISCREG_DBGWVR1, gem5::ArmISA::MISCREG_DBGWVR10, gem5::ArmISA::MISCREG_DBGWVR10_EL1, gem5::ArmISA::MISCREG_DBGWVR11, gem5::ArmISA::MISCREG_DBGWVR11_EL1, gem5::ArmISA::MISCREG_DBGWVR12, gem5::ArmISA::MISCREG_DBGWVR12_EL1, gem5::ArmISA::MISCREG_DBGWVR13, gem5::ArmISA::MISCREG_DBGWVR13_EL1, gem5::ArmISA::MISCREG_DBGWVR14, gem5::ArmISA::MISCREG_DBGWVR14_EL1, gem5::ArmISA::MISCREG_DBGWVR15, gem5::ArmISA::MISCREG_DBGWVR15_EL1, gem5::ArmISA::MISCREG_DBGWVR1_EL1, gem5::ArmISA::MISCREG_DBGWVR2, gem5::ArmISA::MISCREG_DBGWVR2_EL1, gem5::ArmISA::MISCREG_DBGWVR3, gem5::ArmISA::MISCREG_DBGWVR3_EL1, gem5::ArmISA::MISCREG_DBGWVR4, gem5::ArmISA::MISCREG_DBGWVR4_EL1, gem5::ArmISA::MISCREG_DBGWVR5, gem5::ArmISA::MISCREG_DBGWVR5_EL1, gem5::ArmISA::MISCREG_DBGWVR6, gem5::ArmISA::MISCREG_DBGWVR6_EL1, gem5::ArmISA::MISCREG_DBGWVR7, gem5::ArmISA::MISCREG_DBGWVR7_EL1, gem5::ArmISA::MISCREG_DBGWVR8, gem5::ArmISA::MISCREG_DBGWVR8_EL1, gem5::ArmISA::MISCREG_DBGWVR9, gem5::ArmISA::MISCREG_DBGWVR9_EL1, gem5::ArmISA::MISCREG_DC_CISW_Xt, gem5::ArmISA::MISCREG_DC_CIVAC_Xt, gem5::ArmISA::MISCREG_DC_CSW_Xt, gem5::ArmISA::MISCREG_DC_CVAC_Xt, gem5::ArmISA::MISCREG_DC_CVAU_Xt, gem5::ArmISA::MISCREG_DC_ISW_Xt, gem5::ArmISA::MISCREG_DC_IVAC_Xt, gem5::ArmISA::MISCREG_DC_ZVA_Xt, gem5::ArmISA::MISCREG_DCCIMVAC, gem5::ArmISA::MISCREG_DCCISW, gem5::ArmISA::MISCREG_DCCMVAC, gem5::ArmISA::MISCREG_DCCMVAU, gem5::ArmISA::MISCREG_DCCSW, gem5::ArmISA::MISCREG_DCIMVAC, gem5::ArmISA::MISCREG_DCISW, gem5::ArmISA::MISCREG_DCZID_EL0, gem5::ArmISA::MISCREG_DFAR, gem5::ArmISA::MISCREG_DFAR_NS, gem5::ArmISA::MISCREG_DFAR_S, gem5::ArmISA::MISCREG_DFSR, gem5::ArmISA::MISCREG_DFSR_NS, gem5::ArmISA::MISCREG_DFSR_S, gem5::ArmISA::MISCREG_DISR_EL1, gem5::ArmISA::MISCREG_DL1DATA0, gem5::ArmISA::MISCREG_DL1DATA0_EL1, gem5::ArmISA::MISCREG_DL1DATA1, gem5::ArmISA::MISCREG_DL1DATA1_EL1, gem5::ArmISA::MISCREG_DL1DATA2, gem5::ArmISA::MISCREG_DL1DATA2_EL1, gem5::ArmISA::MISCREG_DL1DATA3, gem5::ArmISA::MISCREG_DL1DATA3_EL1, gem5::ArmISA::MISCREG_DL1DATA4, gem5::ArmISA::MISCREG_DL1DATA4_EL1, gem5::ArmISA::MISCREG_DLR_EL0, gem5::ArmISA::MISCREG_DSPSR_EL0, gem5::ArmISA::MISCREG_DTLBIALL, gem5::ArmISA::MISCREG_DTLBIASID, gem5::ArmISA::MISCREG_DTLBIMVA, gem5::ArmISA::MISCREG_ELR_EL1, gem5::ArmISA::MISCREG_ELR_EL12, gem5::ArmISA::MISCREG_ELR_EL2, gem5::ArmISA::MISCREG_ELR_EL3, gem5::ArmISA::MISCREG_ELR_HYP, gem5::ArmISA::MISCREG_ERRIDR_EL1, gem5::ArmISA::MISCREG_ERRSELR_EL1, gem5::ArmISA::MISCREG_ERXADDR_EL1, gem5::ArmISA::MISCREG_ERXCTLR_EL1, gem5::ArmISA::MISCREG_ERXFR_EL1, gem5::ArmISA::MISCREG_ERXMISC0_EL1, gem5::ArmISA::MISCREG_ERXMISC1_EL1, gem5::ArmISA::MISCREG_ERXSTATUS_EL1, gem5::ArmISA::MISCREG_ESR_EL1, gem5::ArmISA::MISCREG_ESR_EL12, gem5::ArmISA::MISCREG_ESR_EL2, gem5::ArmISA::MISCREG_ESR_EL3, gem5::ArmISA::MISCREG_FAR_EL1, gem5::ArmISA::MISCREG_FAR_EL12, gem5::ArmISA::MISCREG_FAR_EL2, gem5::ArmISA::MISCREG_FAR_EL3, gem5::ArmISA::MISCREG_FCSEIDR, gem5::ArmISA::MISCREG_FPCR, gem5::ArmISA::MISCREG_FPEXC, gem5::ArmISA::MISCREG_FPEXC32_EL2, gem5::ArmISA::MISCREG_FPSCR, gem5::ArmISA::MISCREG_FPSCR_EXC, gem5::ArmISA::MISCREG_FPSCR_QC, gem5::ArmISA::MISCREG_FPSID, gem5::ArmISA::MISCREG_FPSR, gem5::ArmISA::MISCREG_HACR, gem5::ArmISA::MISCREG_HACR_EL2, gem5::ArmISA::MISCREG_HACTLR, gem5::ArmISA::MISCREG_HADFSR, gem5::ArmISA::MISCREG_HAIFSR, gem5::ArmISA::MISCREG_HAMAIR0, gem5::ArmISA::MISCREG_HAMAIR1, gem5::ArmISA::MISCREG_HCPTR, gem5::ArmISA::MISCREG_HCR, gem5::ArmISA::MISCREG_HCR2, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HDCR, gem5::ArmISA::MISCREG_HDFAR, gem5::ArmISA::MISCREG_HIFAR, gem5::ArmISA::MISCREG_HMAIR0, gem5::ArmISA::MISCREG_HMAIR1, gem5::ArmISA::MISCREG_HPFAR, gem5::ArmISA::MISCREG_HPFAR_EL2, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_HSR, gem5::ArmISA::MISCREG_HSTR, gem5::ArmISA::MISCREG_HSTR_EL2, gem5::ArmISA::MISCREG_HTCR, gem5::ArmISA::MISCREG_HTPIDR, gem5::ArmISA::MISCREG_HTTBR, gem5::ArmISA::MISCREG_HVBAR, gem5::ArmISA::MISCREG_IC_IALLU, gem5::ArmISA::MISCREG_IC_IALLUIS, gem5::ArmISA::MISCREG_IC_IVAU_Xt, gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_AP0R0_EL1, gem5::ArmISA::MISCREG_ICC_AP0R1, gem5::ArmISA::MISCREG_ICC_AP0R1_EL1, gem5::ArmISA::MISCREG_ICC_AP0R2, gem5::ArmISA::MISCREG_ICC_AP0R2_EL1, gem5::ArmISA::MISCREG_ICC_AP0R3, gem5::ArmISA::MISCREG_ICC_AP0R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R0_NS, gem5::ArmISA::MISCREG_ICC_AP1R0_S, gem5::ArmISA::MISCREG_ICC_AP1R1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R1_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R1_NS, gem5::ArmISA::MISCREG_ICC_AP1R1_S, gem5::ArmISA::MISCREG_ICC_AP1R2, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R2_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R2_NS, gem5::ArmISA::MISCREG_ICC_AP1R2_S, gem5::ArmISA::MISCREG_ICC_AP1R3, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_NS, gem5::ArmISA::MISCREG_ICC_AP1R3_EL1_S, gem5::ArmISA::MISCREG_ICC_AP1R3_NS, gem5::ArmISA::MISCREG_ICC_AP1R3_S, gem5::ArmISA::MISCREG_ICC_ASGI1R, gem5::ArmISA::MISCREG_ICC_ASGI1R_EL1, gem5::ArmISA::MISCREG_ICC_BPR0, gem5::ArmISA::MISCREG_ICC_BPR0_EL1, gem5::ArmISA::MISCREG_ICC_BPR1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_EL1_S, gem5::ArmISA::MISCREG_ICC_BPR1_NS, gem5::ArmISA::MISCREG_ICC_BPR1_S, gem5::ArmISA::MISCREG_ICC_CTLR, gem5::ArmISA::MISCREG_ICC_CTLR_EL1, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_NS, gem5::ArmISA::MISCREG_ICC_CTLR_EL1_S, gem5::ArmISA::MISCREG_ICC_CTLR_EL3, gem5::ArmISA::MISCREG_ICC_CTLR_NS, gem5::ArmISA::MISCREG_ICC_CTLR_S, gem5::ArmISA::MISCREG_ICC_DIR, gem5::ArmISA::MISCREG_ICC_DIR_EL1, gem5::ArmISA::MISCREG_ICC_EOIR0, gem5::ArmISA::MISCREG_ICC_EOIR0_EL1, gem5::ArmISA::MISCREG_ICC_EOIR1, gem5::ArmISA::MISCREG_ICC_EOIR1_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR0, gem5::ArmISA::MISCREG_ICC_HPPIR0_EL1, gem5::ArmISA::MISCREG_ICC_HPPIR1, gem5::ArmISA::MISCREG_ICC_HPPIR1_EL1, gem5::ArmISA::MISCREG_ICC_HSRE, gem5::ArmISA::MISCREG_ICC_IAR0, gem5::ArmISA::MISCREG_ICC_IAR0_EL1, gem5::ArmISA::MISCREG_ICC_IAR1, gem5::ArmISA::MISCREG_ICC_IAR1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN0, gem5::ArmISA::MISCREG_ICC_IGRPEN0_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_IGRPEN1_NS, gem5::ArmISA::MISCREG_ICC_IGRPEN1_S, gem5::ArmISA::MISCREG_ICC_MCTLR, gem5::ArmISA::MISCREG_ICC_MGRPEN1, gem5::ArmISA::MISCREG_ICC_MSRE, gem5::ArmISA::MISCREG_ICC_PMR, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICC_RPR, gem5::ArmISA::MISCREG_ICC_RPR_EL1, gem5::ArmISA::MISCREG_ICC_SGI0R, gem5::ArmISA::MISCREG_ICC_SGI0R_EL1, gem5::ArmISA::MISCREG_ICC_SGI1R, gem5::ArmISA::MISCREG_ICC_SGI1R_EL1, gem5::ArmISA::MISCREG_ICC_SRE, gem5::ArmISA::MISCREG_ICC_SRE_EL1, gem5::ArmISA::MISCREG_ICC_SRE_EL1_NS, gem5::ArmISA::MISCREG_ICC_SRE_EL1_S, gem5::ArmISA::MISCREG_ICC_SRE_EL2, gem5::ArmISA::MISCREG_ICC_SRE_EL3, gem5::ArmISA::MISCREG_ICC_SRE_NS, gem5::ArmISA::MISCREG_ICC_SRE_S, gem5::ArmISA::MISCREG_ICH_AP0R0, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_AP0R1, gem5::ArmISA::MISCREG_ICH_AP0R1_EL2, gem5::ArmISA::MISCREG_ICH_AP0R2, gem5::ArmISA::MISCREG_ICH_AP0R2_EL2, gem5::ArmISA::MISCREG_ICH_AP0R3, gem5::ArmISA::MISCREG_ICH_AP0R3_EL2, gem5::ArmISA::MISCREG_ICH_AP1R0, gem5::ArmISA::MISCREG_ICH_AP1R0_EL2, gem5::ArmISA::MISCREG_ICH_AP1R1, gem5::ArmISA::MISCREG_ICH_AP1R1_EL2, gem5::ArmISA::MISCREG_ICH_AP1R2, gem5::ArmISA::MISCREG_ICH_AP1R2_EL2, gem5::ArmISA::MISCREG_ICH_AP1R3, gem5::ArmISA::MISCREG_ICH_AP1R3_EL2, gem5::ArmISA::MISCREG_ICH_EISR, gem5::ArmISA::MISCREG_ICH_EISR_EL2, gem5::ArmISA::MISCREG_ICH_ELRSR, gem5::ArmISA::MISCREG_ICH_ELRSR_EL2, gem5::ArmISA::MISCREG_ICH_HCR, gem5::ArmISA::MISCREG_ICH_HCR_EL2, gem5::ArmISA::MISCREG_ICH_LR0, gem5::ArmISA::MISCREG_ICH_LR0_EL2, gem5::ArmISA::MISCREG_ICH_LR1, gem5::ArmISA::MISCREG_ICH_LR10, gem5::ArmISA::MISCREG_ICH_LR10_EL2, gem5::ArmISA::MISCREG_ICH_LR11, gem5::ArmISA::MISCREG_ICH_LR11_EL2, gem5::ArmISA::MISCREG_ICH_LR12, gem5::ArmISA::MISCREG_ICH_LR12_EL2, gem5::ArmISA::MISCREG_ICH_LR13, gem5::ArmISA::MISCREG_ICH_LR13_EL2, gem5::ArmISA::MISCREG_ICH_LR14, gem5::ArmISA::MISCREG_ICH_LR14_EL2, gem5::ArmISA::MISCREG_ICH_LR15, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LR1_EL2, gem5::ArmISA::MISCREG_ICH_LR2, gem5::ArmISA::MISCREG_ICH_LR2_EL2, gem5::ArmISA::MISCREG_ICH_LR3, gem5::ArmISA::MISCREG_ICH_LR3_EL2, gem5::ArmISA::MISCREG_ICH_LR4, gem5::ArmISA::MISCREG_ICH_LR4_EL2, gem5::ArmISA::MISCREG_ICH_LR5, gem5::ArmISA::MISCREG_ICH_LR5_EL2, gem5::ArmISA::MISCREG_ICH_LR6, gem5::ArmISA::MISCREG_ICH_LR6_EL2, gem5::ArmISA::MISCREG_ICH_LR7, gem5::ArmISA::MISCREG_ICH_LR7_EL2, gem5::ArmISA::MISCREG_ICH_LR8, gem5::ArmISA::MISCREG_ICH_LR8_EL2, gem5::ArmISA::MISCREG_ICH_LR9, gem5::ArmISA::MISCREG_ICH_LR9_EL2, gem5::ArmISA::MISCREG_ICH_LRC0, gem5::ArmISA::MISCREG_ICH_LRC1, gem5::ArmISA::MISCREG_ICH_LRC10, gem5::ArmISA::MISCREG_ICH_LRC11, gem5::ArmISA::MISCREG_ICH_LRC12, gem5::ArmISA::MISCREG_ICH_LRC13, gem5::ArmISA::MISCREG_ICH_LRC14, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ICH_LRC2, gem5::ArmISA::MISCREG_ICH_LRC3, gem5::ArmISA::MISCREG_ICH_LRC4, gem5::ArmISA::MISCREG_ICH_LRC5, gem5::ArmISA::MISCREG_ICH_LRC6, gem5::ArmISA::MISCREG_ICH_LRC7, gem5::ArmISA::MISCREG_ICH_LRC8, gem5::ArmISA::MISCREG_ICH_LRC9, gem5::ArmISA::MISCREG_ICH_MISR, gem5::ArmISA::MISCREG_ICH_MISR_EL2, gem5::ArmISA::MISCREG_ICH_VMCR, gem5::ArmISA::MISCREG_ICH_VMCR_EL2, gem5::ArmISA::MISCREG_ICH_VTR, gem5::ArmISA::MISCREG_ICH_VTR_EL2, gem5::ArmISA::MISCREG_ICIALLU, gem5::ArmISA::MISCREG_ICIALLUIS, gem5::ArmISA::MISCREG_ICIMVAU, gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1, gem5::ArmISA::MISCREG_ID_AFR0, gem5::ArmISA::MISCREG_ID_AFR0_EL1, gem5::ArmISA::MISCREG_ID_DFR0, gem5::ArmISA::MISCREG_ID_DFR0_EL1, gem5::ArmISA::MISCREG_ID_ISAR0, gem5::ArmISA::MISCREG_ID_ISAR0_EL1, gem5::ArmISA::MISCREG_ID_ISAR1, gem5::ArmISA::MISCREG_ID_ISAR1_EL1, gem5::ArmISA::MISCREG_ID_ISAR2, gem5::ArmISA::MISCREG_ID_ISAR2_EL1, gem5::ArmISA::MISCREG_ID_ISAR3, gem5::ArmISA::MISCREG_ID_ISAR3_EL1, gem5::ArmISA::MISCREG_ID_ISAR4, gem5::ArmISA::MISCREG_ID_ISAR4_EL1, gem5::ArmISA::MISCREG_ID_ISAR5, gem5::ArmISA::MISCREG_ID_ISAR5_EL1, gem5::ArmISA::MISCREG_ID_ISAR6, gem5::ArmISA::MISCREG_ID_ISAR6_EL1, gem5::ArmISA::MISCREG_ID_MMFR0, gem5::ArmISA::MISCREG_ID_MMFR0_EL1, gem5::ArmISA::MISCREG_ID_MMFR1, gem5::ArmISA::MISCREG_ID_MMFR1_EL1, gem5::ArmISA::MISCREG_ID_MMFR2, gem5::ArmISA::MISCREG_ID_MMFR2_EL1, gem5::ArmISA::MISCREG_ID_MMFR3, gem5::ArmISA::MISCREG_ID_MMFR3_EL1, gem5::ArmISA::MISCREG_ID_MMFR4, gem5::ArmISA::MISCREG_ID_MMFR4_EL1, gem5::ArmISA::MISCREG_ID_PFR0, gem5::ArmISA::MISCREG_ID_PFR0_EL1, gem5::ArmISA::MISCREG_ID_PFR1, gem5::ArmISA::MISCREG_ID_PFR1_EL1, gem5::ArmISA::MISCREG_IFAR, gem5::ArmISA::MISCREG_IFAR_NS, gem5::ArmISA::MISCREG_IFAR_S, gem5::ArmISA::MISCREG_IFSR, gem5::ArmISA::MISCREG_IFSR32_EL2, gem5::ArmISA::MISCREG_IFSR_NS, gem5::ArmISA::MISCREG_IFSR_S, gem5::ArmISA::MISCREG_IL1DATA0, gem5::ArmISA::MISCREG_IL1DATA0_EL1, gem5::ArmISA::MISCREG_IL1DATA1, gem5::ArmISA::MISCREG_IL1DATA1_EL1, gem5::ArmISA::MISCREG_IL1DATA2, gem5::ArmISA::MISCREG_IL1DATA2_EL1, gem5::ArmISA::MISCREG_IL1DATA3, gem5::ArmISA::MISCREG_IL1DATA3_EL1, gem5::ArmISA::MISCREG_IMPDEF_UNIMPL, gem5::ArmISA::MISCREG_ISR, gem5::ArmISA::MISCREG_ISR_EL1, gem5::ArmISA::MISCREG_ITLBIALL, gem5::ArmISA::MISCREG_ITLBIASID, gem5::ArmISA::MISCREG_ITLBIMVA, gem5::ArmISA::MISCREG_JIDR, gem5::ArmISA::MISCREG_JMCR, gem5::ArmISA::MISCREG_JOSCR, gem5::ArmISA::MISCREG_L2ACTLR, gem5::ArmISA::MISCREG_L2ACTLR_EL1, gem5::ArmISA::MISCREG_L2CTLR, gem5::ArmISA::MISCREG_L2CTLR_EL1, gem5::ArmISA::MISCREG_L2ECTLR, gem5::ArmISA::MISCREG_L2ECTLR_EL1, gem5::ArmISA::MISCREG_L2MERRSR, gem5::ArmISA::MISCREG_L2MERRSR_EL1, gem5::ArmISA::MISCREG_LOCKADDR, gem5::ArmISA::MISCREG_LOCKFLAG, gem5::ArmISA::MISCREG_MAIR0, gem5::ArmISA::MISCREG_MAIR0_NS, gem5::ArmISA::MISCREG_MAIR0_S, gem5::ArmISA::MISCREG_MAIR1, gem5::ArmISA::MISCREG_MAIR1_NS, gem5::ArmISA::MISCREG_MAIR1_S, gem5::ArmISA::MISCREG_MAIR_EL1, gem5::ArmISA::MISCREG_MAIR_EL12, gem5::ArmISA::MISCREG_MAIR_EL2, gem5::ArmISA::MISCREG_MAIR_EL3, gem5::ArmISA::MISCREG_MDCCINT_EL1, gem5::ArmISA::MISCREG_MDCCSR_EL0, gem5::ArmISA::MISCREG_MDCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL3, gem5::ArmISA::MISCREG_MDDTR_EL0, gem5::ArmISA::MISCREG_MDDTRRX_EL0, gem5::ArmISA::MISCREG_MDDTRTX_EL0, gem5::ArmISA::MISCREG_MDRAR_EL1, gem5::ArmISA::MISCREG_MDSCR_EL1, gem5::ArmISA::MISCREG_MIDR, gem5::ArmISA::MISCREG_MIDR_EL1, gem5::ArmISA::MISCREG_MPIDR, gem5::ArmISA::MISCREG_MPIDR_EL1, gem5::ArmISA::MISCREG_MVBAR, gem5::ArmISA::MISCREG_MVFR0, gem5::ArmISA::MISCREG_MVFR0_EL1, gem5::ArmISA::MISCREG_MVFR1, gem5::ArmISA::MISCREG_MVFR1_EL1, gem5::ArmISA::MISCREG_MVFR2_EL1, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_NMRR_MAIR1, gem5::ArmISA::MISCREG_NMRR_MAIR1_NS, gem5::ArmISA::MISCREG_NMRR_MAIR1_S, gem5::ArmISA::MISCREG_NMRR_NS, gem5::ArmISA::MISCREG_NMRR_S, gem5::ArmISA::MISCREG_NOP, gem5::ArmISA::MISCREG_NSACR, gem5::ArmISA::MISCREG_NZCV, gem5::ArmISA::MISCREG_OSDLR_EL1, gem5::ArmISA::MISCREG_OSDTRRX_EL1, gem5::ArmISA::MISCREG_OSDTRTX_EL1, gem5::ArmISA::MISCREG_OSECCR_EL1, gem5::ArmISA::MISCREG_OSLAR_EL1, gem5::ArmISA::MISCREG_OSLSR_EL1, gem5::ArmISA::MISCREG_PAN, gem5::ArmISA::MISCREG_PAR, gem5::ArmISA::MISCREG_PAR_EL1, gem5::ArmISA::MISCREG_PAR_NS, gem5::ArmISA::MISCREG_PAR_S, gem5::ArmISA::MISCREG_PMCCFILTR, gem5::ArmISA::MISCREG_PMCCFILTR_EL0, gem5::ArmISA::MISCREG_PMCCNTR, gem5::ArmISA::MISCREG_PMCCNTR_EL0, gem5::ArmISA::MISCREG_PMCEID0, gem5::ArmISA::MISCREG_PMCEID0_EL0, gem5::ArmISA::MISCREG_PMCEID1, gem5::ArmISA::MISCREG_PMCEID1_EL0, gem5::ArmISA::MISCREG_PMCNTENCLR, gem5::ArmISA::MISCREG_PMCNTENCLR_EL0, gem5::ArmISA::MISCREG_PMCNTENSET, gem5::ArmISA::MISCREG_PMCNTENSET_EL0, gem5::ArmISA::MISCREG_PMCR, gem5::ArmISA::MISCREG_PMCR_EL0, gem5::ArmISA::MISCREG_PMEVCNTR0_EL0, gem5::ArmISA::MISCREG_PMEVCNTR1_EL0, gem5::ArmISA::MISCREG_PMEVCNTR2_EL0, gem5::ArmISA::MISCREG_PMEVCNTR3_EL0, gem5::ArmISA::MISCREG_PMEVCNTR4_EL0, gem5::ArmISA::MISCREG_PMEVCNTR5_EL0, gem5::ArmISA::MISCREG_PMEVTYPER0_EL0, gem5::ArmISA::MISCREG_PMEVTYPER1_EL0, gem5::ArmISA::MISCREG_PMEVTYPER2_EL0, gem5::ArmISA::MISCREG_PMEVTYPER3_EL0, gem5::ArmISA::MISCREG_PMEVTYPER4_EL0, gem5::ArmISA::MISCREG_PMEVTYPER5_EL0, gem5::ArmISA::MISCREG_PMINTENCLR, gem5::ArmISA::MISCREG_PMINTENCLR_EL1, gem5::ArmISA::MISCREG_PMINTENSET, gem5::ArmISA::MISCREG_PMINTENSET_EL1, gem5::ArmISA::MISCREG_PMOVSCLR_EL0, gem5::ArmISA::MISCREG_PMOVSR, gem5::ArmISA::MISCREG_PMOVSSET, gem5::ArmISA::MISCREG_PMOVSSET_EL0, gem5::ArmISA::MISCREG_PMSELR, gem5::ArmISA::MISCREG_PMSELR_EL0, gem5::ArmISA::MISCREG_PMSWINC, gem5::ArmISA::MISCREG_PMSWINC_EL0, gem5::ArmISA::MISCREG_PMUSERENR, gem5::ArmISA::MISCREG_PMUSERENR_EL0, gem5::ArmISA::MISCREG_PMXEVCNTR, gem5::ArmISA::MISCREG_PMXEVCNTR_EL0, gem5::ArmISA::MISCREG_PMXEVTYPER, gem5::ArmISA::MISCREG_PMXEVTYPER_EL0, gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_PRRR_MAIR0, gem5::ArmISA::MISCREG_PRRR_MAIR0_NS, gem5::ArmISA::MISCREG_PRRR_MAIR0_S, gem5::ArmISA::MISCREG_PRRR_NS, gem5::ArmISA::MISCREG_PRRR_S, gem5::ArmISA::MISCREG_RAMINDEX, gem5::ArmISA::MISCREG_RAZ, gem5::ArmISA::MISCREG_REVIDR, gem5::ArmISA::MISCREG_REVIDR_EL1, gem5::ArmISA::MISCREG_RMR, gem5::ArmISA::MISCREG_RMR_EL3, gem5::ArmISA::MISCREG_RVBAR_EL1, gem5::ArmISA::MISCREG_RVBAR_EL2, gem5::ArmISA::MISCREG_RVBAR_EL3, gem5::ArmISA::MISCREG_SCR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL12, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_SCTLR_NS, gem5::ArmISA::MISCREG_SCTLR_RST, gem5::ArmISA::MISCREG_SCTLR_S, gem5::ArmISA::MISCREG_SDCR, gem5::ArmISA::MISCREG_SDER, gem5::ArmISA::MISCREG_SDER32_EL3, gem5::ArmISA::MISCREG_SEV_MAILBOX, gem5::ArmISA::MISCREG_SP_EL0, gem5::ArmISA::MISCREG_SP_EL1, gem5::ArmISA::MISCREG_SP_EL2, gem5::ArmISA::MISCREG_SPSEL, gem5::ArmISA::MISCREG_SPSR, gem5::ArmISA::MISCREG_SPSR_ABT, gem5::ArmISA::MISCREG_SPSR_ABT_AA64, gem5::ArmISA::MISCREG_SPSR_EL1, gem5::ArmISA::MISCREG_SPSR_EL12, gem5::ArmISA::MISCREG_SPSR_EL2, gem5::ArmISA::MISCREG_SPSR_EL3, gem5::ArmISA::MISCREG_SPSR_FIQ, gem5::ArmISA::MISCREG_SPSR_FIQ_AA64, gem5::ArmISA::MISCREG_SPSR_HYP, gem5::ArmISA::MISCREG_SPSR_IRQ, gem5::ArmISA::MISCREG_SPSR_IRQ_AA64, gem5::ArmISA::MISCREG_SPSR_MON, gem5::ArmISA::MISCREG_SPSR_SVC, gem5::ArmISA::MISCREG_SPSR_UND, gem5::ArmISA::MISCREG_SPSR_UND_AA64, gem5::ArmISA::MISCREG_TCMTR, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL12, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_TEECR, gem5::ArmISA::MISCREG_TEECR32_EL1, gem5::ArmISA::MISCREG_TEEHBR, gem5::ArmISA::MISCREG_TEEHBR32_EL1, gem5::ArmISA::MISCREG_TLBI_ALLE1, gem5::ArmISA::MISCREG_TLBI_ALLE1IS, gem5::ArmISA::MISCREG_TLBI_ALLE2, gem5::ArmISA::MISCREG_TLBI_ALLE2IS, gem5::ArmISA::MISCREG_TLBI_ALLE3, gem5::ArmISA::MISCREG_TLBI_ALLE3IS, gem5::ArmISA::MISCREG_TLBI_ASIDE1_Xt, gem5::ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2E1_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, gem5::ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAAE1_Xt, gem5::ArmISA::MISCREG_TLBI_VAAE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAALE1_Xt, gem5::ArmISA::MISCREG_TLBI_VAALE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAE1_Xt, gem5::ArmISA::MISCREG_TLBI_VAE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAE2_Xt, gem5::ArmISA::MISCREG_TLBI_VAE2IS_Xt, gem5::ArmISA::MISCREG_TLBI_VAE3_Xt, gem5::ArmISA::MISCREG_TLBI_VAE3IS_Xt, gem5::ArmISA::MISCREG_TLBI_VALE1_Xt, gem5::ArmISA::MISCREG_TLBI_VALE1IS_Xt, gem5::ArmISA::MISCREG_TLBI_VALE2_Xt, gem5::ArmISA::MISCREG_TLBI_VALE2IS_Xt, gem5::ArmISA::MISCREG_TLBI_VALE3_Xt, gem5::ArmISA::MISCREG_TLBI_VALE3IS_Xt, gem5::ArmISA::MISCREG_TLBI_VMALLE1, gem5::ArmISA::MISCREG_TLBI_VMALLE1IS, gem5::ArmISA::MISCREG_TLBI_VMALLS12E1, gem5::ArmISA::MISCREG_TLBI_VMALLS12E1IS, gem5::ArmISA::MISCREG_TLBIALL, gem5::ArmISA::MISCREG_TLBIALLH, gem5::ArmISA::MISCREG_TLBIALLHIS, gem5::ArmISA::MISCREG_TLBIALLIS, gem5::ArmISA::MISCREG_TLBIALLNSNH, gem5::ArmISA::MISCREG_TLBIALLNSNHIS, gem5::ArmISA::MISCREG_TLBIASID, gem5::ArmISA::MISCREG_TLBIASIDIS, gem5::ArmISA::MISCREG_TLBIIPAS2, gem5::ArmISA::MISCREG_TLBIIPAS2IS, gem5::ArmISA::MISCREG_TLBIIPAS2L, gem5::ArmISA::MISCREG_TLBIIPAS2LIS, gem5::ArmISA::MISCREG_TLBIMVA, gem5::ArmISA::MISCREG_TLBIMVAA, gem5::ArmISA::MISCREG_TLBIMVAAIS, gem5::ArmISA::MISCREG_TLBIMVAAL, gem5::ArmISA::MISCREG_TLBIMVAALIS, gem5::ArmISA::MISCREG_TLBIMVAH, gem5::ArmISA::MISCREG_TLBIMVAHIS, gem5::ArmISA::MISCREG_TLBIMVAIS, gem5::ArmISA::MISCREG_TLBIMVAL, gem5::ArmISA::MISCREG_TLBIMVALH, gem5::ArmISA::MISCREG_TLBIMVALHIS, gem5::ArmISA::MISCREG_TLBIMVALIS, gem5::ArmISA::MISCREG_TLBINEEDSYNC, gem5::ArmISA::MISCREG_TLBTR, gem5::ArmISA::MISCREG_TPIDR_EL0, gem5::ArmISA::MISCREG_TPIDR_EL1, gem5::ArmISA::MISCREG_TPIDR_EL2, gem5::ArmISA::MISCREG_TPIDR_EL3, gem5::ArmISA::MISCREG_TPIDRPRW, gem5::ArmISA::MISCREG_TPIDRPRW_NS, gem5::ArmISA::MISCREG_TPIDRPRW_S, gem5::ArmISA::MISCREG_TPIDRRO_EL0, gem5::ArmISA::MISCREG_TPIDRURO, gem5::ArmISA::MISCREG_TPIDRURO_NS, gem5::ArmISA::MISCREG_TPIDRURO_S, gem5::ArmISA::MISCREG_TPIDRURW, gem5::ArmISA::MISCREG_TPIDRURW_NS, gem5::ArmISA::MISCREG_TPIDRURW_S, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBCR_NS, gem5::ArmISA::MISCREG_TTBCR_S, gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL12, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR0_EL3, gem5::ArmISA::MISCREG_TTBR0_NS, gem5::ArmISA::MISCREG_TTBR0_S, gem5::ArmISA::MISCREG_TTBR1, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL12, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_TTBR1_NS, gem5::ArmISA::MISCREG_TTBR1_S, gem5::ArmISA::MISCREG_UAO, gem5::ArmISA::MISCREG_UNKNOWN, gem5::ArmISA::MISCREG_VBAR, gem5::ArmISA::MISCREG_VBAR_EL1, gem5::ArmISA::MISCREG_VBAR_EL12, gem5::ArmISA::MISCREG_VBAR_EL2, gem5::ArmISA::MISCREG_VBAR_EL3, gem5::ArmISA::MISCREG_VBAR_NS, gem5::ArmISA::MISCREG_VBAR_S, gem5::ArmISA::MISCREG_VDISR_EL2, gem5::ArmISA::MISCREG_VMPIDR, gem5::ArmISA::MISCREG_VMPIDR_EL2, gem5::ArmISA::MISCREG_VPIDR, gem5::ArmISA::MISCREG_VPIDR_EL2, gem5::ArmISA::MISCREG_VSESR_EL2, gem5::ArmISA::MISCREG_VSTCR_EL2, gem5::ArmISA::MISCREG_VSTTBR_EL2, gem5::ArmISA::MISCREG_VTCR, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VTTBR, gem5::ArmISA::MISCREG_VTTBR_EL2, gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::MISCREG_ZCR_EL12, gem5::ArmISA::MISCREG_ZCR_EL2, gem5::ArmISA::MISCREG_ZCR_EL3, gem5::ArmISA::MiscRegLUTEntryInitializer::mon(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::mutex(), gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::privRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::reads(), release, gem5::ArmISA::MiscRegLUTEntryInitializer::res0(), gem5::ArmISA::MiscRegLUTEntryInitializer::res1(), gem5::ArmISA::MiscRegLUTEntryInitializer::secure(), system, gem5::ArmISA::tacr, gem5::ArmISA::tdz, gem5::ArmISA::tid1, gem5::ArmISA::tid2, gem5::ArmISA::tid3, gem5::ArmISA::tpc, gem5::ArmISA::trvm, gem5::ArmISA::tsw, gem5::ArmISA::ttlb, gem5::ArmISA::tvm, gem5::ArmISA::MiscRegLUTEntryInitializer::unimplemented(), gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable(), gem5::ArmISA::MiscRegLUTEntryInitializer::user(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite(), gem5::X86ISA::val, gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail(), and gem5::ArmISA::MiscRegLUTEntryInitializer::writes().

Referenced by ISA().

initID32()

void gem5::ArmISA::ISA::initID32 ( const ArmISAParams &  p )

protected

MISCREG_ID_ISAR5

ID_ISAR6

Definition at line 323 of file isa.cc.

References gem5::ArmRelease::has(), highestELIs64, gem5::insertBits(), gem5::ArmISA::MISCREG_ID_ISAR0, gem5::ArmISA::MISCREG_ID_ISAR1, gem5::ArmISA::MISCREG_ID_ISAR2, gem5::ArmISA::MISCREG_ID_ISAR3, gem5::ArmISA::MISCREG_ID_ISAR4, gem5::ArmISA::MISCREG_ID_ISAR5, gem5::ArmISA::MISCREG_ID_ISAR6, gem5::ArmISA::MISCREG_ID_MMFR0, gem5::ArmISA::MISCREG_ID_MMFR1, gem5::ArmISA::MISCREG_ID_MMFR2, gem5::ArmISA::MISCREG_ID_MMFR3, gem5::ArmISA::MISCREG_ID_MMFR4, gem5::ArmISA::MISCREG_MIDR, gem5::ArmISA::MISCREG_MIDR_EL1, gem5::ArmISA::MISCREG_VPIDR, miscRegs, gem5::VegaISA::p, and release.

Referenced by clear().

initID64()

void gem5::ArmISA::ISA::initID64 ( const ArmISAParams &  p )

protected

MISCREG_ID_AA64ISAR0_EL1

MISCREG_ID_AA64ISAR1_EL1

MISCREG_ID_AA64MMFR1_EL1

MISCREG_ID_AA64MMFR2_EL1

Definition at line 376 of file isa.cc.

References gem5::ArmISA::encodePhysAddrRange64(), gem5::ArmRelease::has(), haveLargeAsid64, gem5::insertBits(), gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64ZFR0_EL1, gem5::ArmISA::MISCREG_ID_DFR0, gem5::ArmISA::MISCREG_ID_DFR0_EL1, gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::MISCREG_ZCR_EL2, gem5::ArmISA::MISCREG_ZCR_EL3, miscRegs, gem5::VegaISA::p, physAddrRange, release, and sveVL.

Referenced by clear().

InitReg()

const MiscRegLUTEntryInitializer gem5::ArmISA::ISA::InitReg ( uint32_t  reg )

inlineprotected

Definition at line 110 of file isa.hh.

References gem5::ArmISA::lookUpMiscReg, and gem5::X86ISA::reg.

Referenced by initializeMiscRegMetadata().

inSecureState()

bool gem5::ArmISA::ISA::inSecureState

(

)

const

Return true if the PE is in Secure state.

Definition at line 2029 of file isa.cc.

References gem5::ArmRelease::has(), gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_SCR, miscRegs, gem5::ArmISA::MODE_EL2H, gem5::ArmISA::MODE_EL2T, gem5::ArmISA::MODE_EL3H, gem5::ArmISA::MODE_EL3T, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_MON, and release.

Referenced by flattenMiscIndex(), and getMiscIndices().

inUserMode()

bool gem5::ArmISA::ISA::inUserMode ( ) const

inlineoverridevirtual

Implements gem5::BaseISA.

Definition at line 407 of file isa.hh.

References gem5::ArmISA::inUserMode(), gem5::ArmISA::MISCREG_CPSR, and miscRegs.

mapIntRegId()

const RegId& gem5::ArmISA::ISA::mapIntRegId ( RegIndex  idx ) const

inline

Definition at line 163 of file isa.hh.

References intRegMap.

newPCState()

PCStateBase* gem5::ArmISA::ISA::newPCState ( Addr  new_inst_addr = 0 ) const

inlineoverridevirtual

Implements gem5::BaseISA.

Definition at line 386 of file isa.hh.

PARAMS()

gem5::ArmISA::ISA::PARAMS

(

ArmISA

)

readMiscReg()

RegVal gem5::ArmISA::ISA::readMiscReg ( RegIndex  idx )

overridevirtual

Implements gem5::BaseISA.

Definition at line 747 of file isa.cc.

References gem5::PCStateBase::as(), gem5::ArmISA::cc_reg::C, gem5::System::cacheLineSize(), gem5::ArmISA::daif, DPRINTF, gem5::ArmISA::EL3, gem5::ArmISA::ELIs32(), gem5::ArmISA::FpscrExcMask, gem5::ArmISA::FpscrQcMask, gem5::ThreadContext::getCpuPtr(), getGenericTimer(), gem5::ArmSystem::getGenericTimer(), getGICv3CPUInterface(), gem5::BaseCPU::getInterruptController(), gem5::ThreadContext::getReg(), gem5::ThreadContext::getSystemPtr(), gicv3CpuInterface, gem5::ArmRelease::has(), gem5::igbreg::txd_op::ic(), gem5::ArmISA::isSecure(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::mask, gem5::ArmISA::MISCREG_ACTLR, gem5::ArmISA::MISCREG_AIDR, gem5::ArmISA::MISCREG_CCSIDR, gem5::ArmISA::MISCREG_CLIDR, gem5::ArmISA::MISCREG_CNTFRQ, gem5::ArmISA::MISCREG_CNTFRQ_EL0, gem5::ArmISA::MISCREG_CNTVOFF, gem5::ArmISA::MISCREG_CNTVOFF_EL2, gem5::ArmISA::MISCREG_CPACR, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_CPSR_Q, gem5::ArmISA::MISCREG_CTR, gem5::ArmISA::MISCREG_CTR_EL0, gem5::ArmISA::MISCREG_CURRENTEL, gem5::ArmISA::MISCREG_DAIF, gem5::ArmISA::MISCREG_DBGDIDR, gem5::ArmISA::MISCREG_DBGDSCRint, gem5::ArmISA::MISCREG_DCZID_EL0, gem5::ArmISA::MISCREG_DFAR_S, gem5::ArmISA::MISCREG_FPCR, gem5::ArmISA::MISCREG_FPSCR, gem5::ArmISA::MISCREG_FPSCR_EXC, gem5::ArmISA::MISCREG_FPSCR_QC, gem5::ArmISA::MISCREG_FPSR, gem5::ArmISA::MISCREG_HCPTR, gem5::ArmISA::MISCREG_HCR, gem5::ArmISA::MISCREG_HCR2, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HDFAR, gem5::ArmISA::MISCREG_HIFAR, gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1, gem5::ArmISA::MISCREG_ID_AFR0, gem5::ArmISA::MISCREG_ID_PFR0, gem5::ArmISA::MISCREG_ID_PFR1, gem5::ArmISA::MISCREG_IFAR_S, gem5::ArmISA::MISCREG_IMPLEMENTED, gem5::ArmISA::MISCREG_ISR, gem5::ArmISA::MISCREG_ISR_EL1, gem5::ArmISA::MISCREG_JIDR, gem5::ArmISA::MISCREG_JMCR, gem5::ArmISA::MISCREG_JOSCR, gem5::ArmISA::MISCREG_L2CTLR, gem5::ArmISA::MISCREG_MIDR, gem5::ArmISA::MISCREG_MPIDR, gem5::ArmISA::MISCREG_MPIDR_EL1, gem5::ArmISA::MISCREG_NSACR, gem5::ArmISA::MISCREG_NZCV, gem5::ArmISA::MISCREG_PAN, gem5::ArmISA::MISCREG_PMCR, gem5::ArmISA::MISCREG_PMEVCNTR0_EL0, gem5::ArmISA::MISCREG_PMEVTYPER5_EL0, gem5::ArmISA::MISCREG_PMINTENSET_EL1, gem5::ArmISA::MISCREG_PMOVSSET, gem5::ArmISA::MISCREG_PMOVSSET_EL0, gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, gem5::ArmISA::MISCREG_REVIDR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SP_EL0, gem5::ArmISA::MISCREG_SP_EL1, gem5::ArmISA::MISCREG_SP_EL2, gem5::ArmISA::MISCREG_SPSEL, gem5::ArmISA::MISCREG_TCMTR, gem5::ArmISA::MISCREG_UAO, gem5::ArmISA::MISCREG_VMPIDR, gem5::ArmISA::MISCREG_VMPIDR_EL2, gem5::ArmISA::MISCREG_VPIDR, gem5::ArmISA::MISCREG_WARN_NOT_FAIL, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_MON, gem5::ArmISA::cc_reg::Nz, panic, gem5::MipsISA::pc, gem5::ThreadContext::pcState(), pmu, gem5::ArmISA::BaseISADevice::readMiscReg(), readMiscRegNoEffect(), gem5::ArmISA::readMPIDR(), redirectRegVHE(), release, gem5::System::Threads::size(), gem5::ArmISA::int_reg::Sp0, gem5::ArmISA::int_reg::Sp1, gem5::ArmISA::int_reg::Sp2, system, gem5::BaseISA::tc, gem5::ThreadContext::threadId(), gem5::System::threads, gem5::ArmISA::unflattenMiscReg(), gem5::ArmISA::cc_reg::V, gem5::X86ISA::val, warn, and warn_once.

readMiscRegNoEffect()

RegVal gem5::ArmISA::ISA::readMiscRegNoEffect ( RegIndex  idx ) const

overridevirtual

Implements gem5::BaseISA.

Definition at line 723 of file isa.cc.

References DPRINTF, getMiscIndices(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::mask, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::NUM_MISCREGS, gem5::X86ISA::reg, and gem5::X86ISA::val.

Referenced by addressTranslation(), gem5::Gicv3CPUInterface::bpr1(), currEL(), gem5::Gicv3CPUInterface::dropPriority(), gem5::Gicv3CPUInterface::eoiMaintenanceInterruptStatus(), gem5::ArmISA::IntRegClassOps::flatten(), flattenMiscIndex(), getExecutingAsid(), gem5::Gicv3CPUInterface::getHPPIR1(), gem5::Gicv3CPUInterface::getHPPVILR(), gem5::Gicv3CPUInterface::groupEnabled(), gem5::Gicv3CPUInterface::groupPriorityMask(), gem5::Gicv3CPUInterface::highestActiveGroup(), gem5::Gicv3CPUInterface::highestActivePriority(), gem5::Gicv3CPUInterface::hppiCanPreempt(), gem5::Gicv3CPUInterface::hppviCanPreempt(), gem5::Gicv3CPUInterface::isEOISplitMode(), gem5::Gicv3CPUInterface::maintenanceInterruptStatus(), gem5::Gicv3CPUInterface::readBankedMiscReg(), gem5::Gicv3CPUInterface::readMiscReg(), readMiscReg(), redirectRegVHE(), gem5::Gicv3CPUInterface::setMiscReg(), setMiscReg(), gem5::Gicv3CPUInterface::virtualActivateIRQ(), gem5::Gicv3CPUInterface::virtualDeactivateIRQ(), gem5::Gicv3CPUInterface::virtualDropPriority(), gem5::Gicv3CPUInterface::virtualFindActive(), gem5::Gicv3CPUInterface::virtualGroupPriorityMask(), gem5::Gicv3CPUInterface::virtualHighestActivePriority(), gem5::Gicv3CPUInterface::virtualIncrementEOICount(), gem5::Gicv3CPUInterface::virtualIsEOISplitMode(), and gem5::Gicv3CPUInterface::virtualUpdate().

redirectRegVHE()

int gem5::ArmISA::ISA::redirectRegVHE

(

int

misc_reg

)

Returns the enconcing equivalent when VHE is implemented and HCR_EL2.E2H is enabled and executing at EL2.

Definition at line 577 of file isa.cc.

References currEL(), gem5::ArmISA::EL2, gem5::ArmISA::ELIsInHost(), gem5::ArmRelease::has(), gem5::ArmISA::MISCREG_AFSR0_EL1, gem5::ArmISA::MISCREG_AFSR0_EL12, gem5::ArmISA::MISCREG_AFSR0_EL2, gem5::ArmISA::MISCREG_AFSR1_EL1, gem5::ArmISA::MISCREG_AFSR1_EL12, gem5::ArmISA::MISCREG_AFSR1_EL2, gem5::ArmISA::MISCREG_AMAIR_EL1, gem5::ArmISA::MISCREG_AMAIR_EL12, gem5::ArmISA::MISCREG_AMAIR_EL2, gem5::ArmISA::MISCREG_CNTHCTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CTL_EL2, gem5::ArmISA::MISCREG_CNTHP_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHP_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHPS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHPS_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHPS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_CTL_EL2, gem5::ArmISA::MISCREG_CNTHV_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHV_TVAL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CTL_EL2, gem5::ArmISA::MISCREG_CNTHVS_CVAL_EL2, gem5::ArmISA::MISCREG_CNTHVS_TVAL_EL2, gem5::ArmISA::MISCREG_CNTKCTL_EL1, gem5::ArmISA::MISCREG_CNTKCTL_EL12, gem5::ArmISA::MISCREG_CNTP_CTL, gem5::ArmISA::MISCREG_CNTP_CTL_EL0, gem5::ArmISA::MISCREG_CNTP_CTL_EL02, gem5::ArmISA::MISCREG_CNTP_CVAL, gem5::ArmISA::MISCREG_CNTP_CVAL_EL0, gem5::ArmISA::MISCREG_CNTP_CVAL_EL02, gem5::ArmISA::MISCREG_CNTP_TVAL, gem5::ArmISA::MISCREG_CNTP_TVAL_EL0, gem5::ArmISA::MISCREG_CNTP_TVAL_EL02, gem5::ArmISA::MISCREG_CNTPCT_EL0, gem5::ArmISA::MISCREG_CNTV_CTL, gem5::ArmISA::MISCREG_CNTV_CTL_EL0, gem5::ArmISA::MISCREG_CNTV_CTL_EL02, gem5::ArmISA::MISCREG_CNTV_CVAL, gem5::ArmISA::MISCREG_CNTV_CVAL_EL0, gem5::ArmISA::MISCREG_CNTV_CVAL_EL02, gem5::ArmISA::MISCREG_CNTV_TVAL, gem5::ArmISA::MISCREG_CNTV_TVAL_EL0, gem5::ArmISA::MISCREG_CNTV_TVAL_EL02, gem5::ArmISA::MISCREG_CNTVCT, gem5::ArmISA::MISCREG_CNTVCT_EL0, gem5::ArmISA::MISCREG_CONTEXTIDR_EL1, gem5::ArmISA::MISCREG_CONTEXTIDR_EL12, gem5::ArmISA::MISCREG_CONTEXTIDR_EL2, gem5::ArmISA::MISCREG_CPACR_EL1, gem5::ArmISA::MISCREG_CPACR_EL12, gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_ELR_EL1, gem5::ArmISA::MISCREG_ELR_EL12, gem5::ArmISA::MISCREG_ELR_EL2, gem5::ArmISA::MISCREG_ESR_EL1, gem5::ArmISA::MISCREG_ESR_EL12, gem5::ArmISA::MISCREG_ESR_EL2, gem5::ArmISA::MISCREG_FAR_EL1, gem5::ArmISA::MISCREG_FAR_EL12, gem5::ArmISA::MISCREG_FAR_EL2, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_MAIR_EL1, gem5::ArmISA::MISCREG_MAIR_EL12, gem5::ArmISA::MISCREG_MAIR_EL2, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL12, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SPSR_EL1, gem5::ArmISA::MISCREG_SPSR_EL12, gem5::ArmISA::MISCREG_SPSR_EL2, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL12, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL12, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL12, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_VBAR_EL1, gem5::ArmISA::MISCREG_VBAR_EL12, gem5::ArmISA::MISCREG_VBAR_EL2, gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::MISCREG_ZCR_EL12, readMiscRegNoEffect(), release, and gem5::BaseISA::tc.

Referenced by readMiscReg(), and setMiscReg().

serialize()

void gem5::ArmISA::ISA::serialize ( CheckpointOut &  cp ) const

overridevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 2105 of file isa.cc.

References DPRINTF, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::NUM_PHYS_MISCREGS, and SERIALIZE_MAPPING.

setMiscReg()

void gem5::ArmISA::ISA::setMiscReg ( RegIndex  idx, RegVal  val  )

overridevirtual

Implements gem5::BaseISA.

Definition at line 1074 of file isa.cc.

References addressTranslation(), addressTranslation64(), gem5::loader::Arm, gem5::InstDecoder::as(), gem5::PCStateBase::as(), gem5::bits(), gem5::ArmISA::cc_reg::C, gem5::ArmISA::CpsrMaskQ, gem5::ArmISA::daif, DPRINTF, gem5::ArmISA::el, gem5::ArmISA::EL3, gem5::ArmISA::ELIs32(), gem5::ArmISA::FpscrExcMask, gem5::ArmISA::FpscrQcMask, gem5::ThreadContext::getCheckerCpuPtr(), getCurSveVecLenInBits(), gem5::ThreadContext::getDecoderPtr(), getGenericTimer(), getGICv3CPUInterface(), gem5::ArmISA::getMMUPtr(), gicv3CpuInterface, gem5::ArmRelease::has(), highestELIs64, gem5::ArmISA::MMU::HypMode, gem5::ArmISA::MMU::invalidateMiscReg(), gem5::ArmISA::isSecure(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::mask, gem5::ArmISA::MISCREG_ACTLR, gem5::ArmISA::MISCREG_AMAIR0, gem5::ArmISA::MISCREG_AMAIR1, gem5::ArmISA::MISCREG_AT_S12E0R_Xt, gem5::ArmISA::MISCREG_AT_S12E0W_Xt, gem5::ArmISA::MISCREG_AT_S12E1R_Xt, gem5::ArmISA::MISCREG_AT_S12E1W_Xt, gem5::ArmISA::MISCREG_AT_S1E0R_Xt, gem5::ArmISA::MISCREG_AT_S1E0W_Xt, gem5::ArmISA::MISCREG_AT_S1E1R_Xt, gem5::ArmISA::MISCREG_AT_S1E1W_Xt, gem5::ArmISA::MISCREG_AT_S1E2R_Xt, gem5::ArmISA::MISCREG_AT_S1E2W_Xt, gem5::ArmISA::MISCREG_AT_S1E3R_Xt, gem5::ArmISA::MISCREG_AT_S1E3W_Xt, gem5::ArmISA::MISCREG_ATS12NSOPR, gem5::ArmISA::MISCREG_ATS12NSOPW, gem5::ArmISA::MISCREG_ATS12NSOUR, gem5::ArmISA::MISCREG_ATS12NSOUW, gem5::ArmISA::MISCREG_ATS1CPR, gem5::ArmISA::MISCREG_ATS1CPW, gem5::ArmISA::MISCREG_ATS1CUR, gem5::ArmISA::MISCREG_ATS1CUW, gem5::ArmISA::MISCREG_ATS1HR, gem5::ArmISA::MISCREG_ATS1HW, gem5::ArmISA::MISCREG_CNTFRQ, gem5::ArmISA::MISCREG_CNTFRQ_EL0, gem5::ArmISA::MISCREG_CNTVOFF, gem5::ArmISA::MISCREG_CNTVOFF_EL2, gem5::ArmISA::MISCREG_CONTEXTIDR, gem5::ArmISA::MISCREG_CPACR, gem5::ArmISA::MISCREG_CPACR_EL1, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::MISCREG_CPSR_Q, gem5::ArmISA::MISCREG_CPTR_EL2, gem5::ArmISA::MISCREG_CPTR_EL3, gem5::ArmISA::MISCREG_CSSELR, gem5::ArmISA::MISCREG_CURRENTEL, gem5::ArmISA::MISCREG_DACR, gem5::ArmISA::MISCREG_DAIF, gem5::ArmISA::MISCREG_DBGBCR0, gem5::ArmISA::MISCREG_DBGBCR0_EL1, gem5::ArmISA::MISCREG_DBGBCR1, gem5::ArmISA::MISCREG_DBGBCR10, gem5::ArmISA::MISCREG_DBGBCR10_EL1, gem5::ArmISA::MISCREG_DBGBCR11, gem5::ArmISA::MISCREG_DBGBCR11_EL1, gem5::ArmISA::MISCREG_DBGBCR12, gem5::ArmISA::MISCREG_DBGBCR12_EL1, gem5::ArmISA::MISCREG_DBGBCR13, gem5::ArmISA::MISCREG_DBGBCR13_EL1, gem5::ArmISA::MISCREG_DBGBCR14, gem5::ArmISA::MISCREG_DBGBCR14_EL1, gem5::ArmISA::MISCREG_DBGBCR15, gem5::ArmISA::MISCREG_DBGBCR15_EL1, gem5::ArmISA::MISCREG_DBGBCR1_EL1, gem5::ArmISA::MISCREG_DBGBCR2, gem5::ArmISA::MISCREG_DBGBCR2_EL1, gem5::ArmISA::MISCREG_DBGBCR3, gem5::ArmISA::MISCREG_DBGBCR3_EL1, gem5::ArmISA::MISCREG_DBGBCR4, gem5::ArmISA::MISCREG_DBGBCR4_EL1, gem5::ArmISA::MISCREG_DBGBCR5, gem5::ArmISA::MISCREG_DBGBCR5_EL1, gem5::ArmISA::MISCREG_DBGBCR6, gem5::ArmISA::MISCREG_DBGBCR6_EL1, gem5::ArmISA::MISCREG_DBGBCR7, gem5::ArmISA::MISCREG_DBGBCR7_EL1, gem5::ArmISA::MISCREG_DBGBCR8, gem5::ArmISA::MISCREG_DBGBCR8_EL1, gem5::ArmISA::MISCREG_DBGBCR9, gem5::ArmISA::MISCREG_DBGBCR9_EL1, gem5::ArmISA::MISCREG_DBGDSCRext, gem5::ArmISA::MISCREG_DBGDSCRint, gem5::ArmISA::MISCREG_DBGOSLAR, gem5::ArmISA::MISCREG_DBGOSLSR, gem5::ArmISA::MISCREG_DBGWCR0, gem5::ArmISA::MISCREG_DBGWCR0_EL1, gem5::ArmISA::MISCREG_DBGWCR1, gem5::ArmISA::MISCREG_DBGWCR10, gem5::ArmISA::MISCREG_DBGWCR10_EL1, gem5::ArmISA::MISCREG_DBGWCR11, gem5::ArmISA::MISCREG_DBGWCR11_EL1, gem5::ArmISA::MISCREG_DBGWCR12, gem5::ArmISA::MISCREG_DBGWCR12_EL1, gem5::ArmISA::MISCREG_DBGWCR13, gem5::ArmISA::MISCREG_DBGWCR13_EL1, gem5::ArmISA::MISCREG_DBGWCR14, gem5::ArmISA::MISCREG_DBGWCR14_EL1, gem5::ArmISA::MISCREG_DBGWCR15, gem5::ArmISA::MISCREG_DBGWCR15_EL1, gem5::ArmISA::MISCREG_DBGWCR1_EL1, gem5::ArmISA::MISCREG_DBGWCR2, gem5::ArmISA::MISCREG_DBGWCR2_EL1, gem5::ArmISA::MISCREG_DBGWCR3, gem5::ArmISA::MISCREG_DBGWCR3_EL1, gem5::ArmISA::MISCREG_DBGWCR4, gem5::ArmISA::MISCREG_DBGWCR4_EL1, gem5::ArmISA::MISCREG_DBGWCR5, gem5::ArmISA::MISCREG_DBGWCR5_EL1, gem5::ArmISA::MISCREG_DBGWCR6, gem5::ArmISA::MISCREG_DBGWCR6_EL1, gem5::ArmISA::MISCREG_DBGWCR7, gem5::ArmISA::MISCREG_DBGWCR7_EL1, gem5::ArmISA::MISCREG_DBGWCR8, gem5::ArmISA::MISCREG_DBGWCR8_EL1, gem5::ArmISA::MISCREG_DBGWCR9, gem5::ArmISA::MISCREG_DBGWCR9_EL1, gem5::ArmISA::MISCREG_DC_ZVA_Xt, gem5::ArmISA::MISCREG_DFAR_S, gem5::ArmISA::MISCREG_DFSR, gem5::ArmISA::MISCREG_FPCR, gem5::ArmISA::MISCREG_FPEXC, gem5::ArmISA::MISCREG_FPSCR, gem5::ArmISA::MISCREG_FPSCR_EXC, gem5::ArmISA::MISCREG_FPSCR_QC, gem5::ArmISA::MISCREG_FPSID, gem5::ArmISA::MISCREG_FPSR, gem5::ArmISA::MISCREG_HCPTR, gem5::ArmISA::MISCREG_HCR, gem5::ArmISA::MISCREG_HCR2, gem5::ArmISA::MISCREG_HCR_EL2, gem5::ArmISA::MISCREG_HDCR, gem5::ArmISA::MISCREG_HDFAR, gem5::ArmISA::MISCREG_HIFAR, gem5::ArmISA::MISCREG_HSCTLR, gem5::ArmISA::MISCREG_HSTR, gem5::ArmISA::MISCREG_ICC_AP0R0, gem5::ArmISA::MISCREG_ICC_IGRPEN1_EL3, gem5::ArmISA::MISCREG_ICC_PMR_EL1, gem5::ArmISA::MISCREG_ICH_AP0R0_EL2, gem5::ArmISA::MISCREG_ICH_LR15_EL2, gem5::ArmISA::MISCREG_ICH_LRC15, gem5::ArmISA::MISCREG_ID_AA64AFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64AFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64DFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR0_EL1, gem5::ArmISA::MISCREG_ID_AA64ISAR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR1_EL1, gem5::ArmISA::MISCREG_ID_AA64MMFR2_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR0_EL1, gem5::ArmISA::MISCREG_ID_AA64PFR1_EL1, gem5::ArmISA::MISCREG_ID_DFR0, gem5::ArmISA::MISCREG_ID_ISAR0, gem5::ArmISA::MISCREG_ID_ISAR1, gem5::ArmISA::MISCREG_ID_ISAR2, gem5::ArmISA::MISCREG_ID_ISAR3, gem5::ArmISA::MISCREG_ID_ISAR4, gem5::ArmISA::MISCREG_ID_ISAR5, gem5::ArmISA::MISCREG_ID_MMFR0, gem5::ArmISA::MISCREG_ID_MMFR1, gem5::ArmISA::MISCREG_ID_MMFR2, gem5::ArmISA::MISCREG_ID_MMFR3, gem5::ArmISA::MISCREG_ID_MMFR4, gem5::ArmISA::MISCREG_ID_PFR0, gem5::ArmISA::MISCREG_ID_PFR1, gem5::ArmISA::MISCREG_IFAR_S, gem5::ArmISA::MISCREG_IFSR, gem5::ArmISA::MISCREG_IMPLEMENTED, gem5::ArmISA::MISCREG_L2CTLR, gem5::ArmISA::MISCREG_MAIR0, gem5::ArmISA::MISCREG_MAIR1, gem5::ArmISA::MISCREG_MDCR_EL2, gem5::ArmISA::MISCREG_MDCR_EL3, gem5::ArmISA::MISCREG_MDSCR_EL1, gem5::ArmISA::MISCREG_MIDR, gem5::ArmISA::MISCREG_MPIDR, gem5::ArmISA::MISCREG_MVFR0, gem5::ArmISA::MISCREG_MVFR1, gem5::ArmISA::MISCREG_NMRR, gem5::ArmISA::MISCREG_NSACR, gem5::ArmISA::MISCREG_NZCV, gem5::ArmISA::MISCREG_OSLAR_EL1, gem5::ArmISA::MISCREG_OSLSR_EL1, gem5::ArmISA::MISCREG_PAN, gem5::ArmISA::MISCREG_PMCR, gem5::ArmISA::MISCREG_PMEVCNTR0_EL0, gem5::ArmISA::MISCREG_PMEVTYPER5_EL0, gem5::ArmISA::MISCREG_PMINTENSET_EL1, gem5::ArmISA::MISCREG_PMOVSSET, gem5::ArmISA::MISCREG_PMOVSSET_EL0, gem5::ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, gem5::ArmISA::MISCREG_PRRR, gem5::ArmISA::MISCREG_SCR, gem5::ArmISA::MISCREG_SCR_EL3, gem5::ArmISA::MISCREG_SCTLR, gem5::ArmISA::MISCREG_SCTLR_EL1, gem5::ArmISA::MISCREG_SCTLR_EL2, gem5::ArmISA::MISCREG_SCTLR_EL3, gem5::ArmISA::MISCREG_SCTLR_NS, gem5::ArmISA::MISCREG_SCTLR_S, gem5::ArmISA::MISCREG_SDCR, gem5::ArmISA::MISCREG_SP_EL0, gem5::ArmISA::MISCREG_SP_EL1, gem5::ArmISA::MISCREG_SP_EL2, gem5::ArmISA::MISCREG_SPSEL, gem5::ArmISA::MISCREG_TCR_EL1, gem5::ArmISA::MISCREG_TCR_EL2, gem5::ArmISA::MISCREG_TCR_EL3, gem5::ArmISA::MISCREG_TLBTR, gem5::ArmISA::MISCREG_TTBCR, gem5::ArmISA::MISCREG_TTBR0, gem5::ArmISA::MISCREG_TTBR0_EL1, gem5::ArmISA::MISCREG_TTBR0_EL2, gem5::ArmISA::MISCREG_TTBR0_EL3, gem5::ArmISA::MISCREG_TTBR1, gem5::ArmISA::MISCREG_TTBR1_EL1, gem5::ArmISA::MISCREG_TTBR1_EL2, gem5::ArmISA::MISCREG_UAO, gem5::ArmISA::MISCREG_VTCR_EL2, gem5::ArmISA::MISCREG_VTTBR, gem5::ArmISA::MISCREG_WARN_NOT_FAIL, gem5::ArmISA::MISCREG_ZCR_EL1, gem5::ArmISA::MISCREG_ZCR_EL2, gem5::ArmISA::MISCREG_ZCR_EL3, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::MODE_MON, gem5::ArmISA::cc_reg::Nz, gem5::ArmISA::pan, panic, gem5::MipsISA::pc, gem5::ThreadContext::pcState(), gem5::ThreadContext::pcStateNoRecord(), pmu, gem5::VegaISA::r, gem5::BaseMMU::Read, gem5::ThreadContext::readMiscReg(), readMiscRegNoEffect(), gem5::ThreadContext::readMiscRegNoEffect(), redirectRegVHE(), release, gem5::ArmISA::MMU::S12E0Tran, gem5::ArmISA::MMU::S12E1Tran, gem5::ArmISA::MMU::S1CTran, gem5::ArmISA::MMU::S1E0Tran, gem5::ArmISA::MMU::S1E1Tran, gem5::ArmISA::MMU::S1E2Tran, gem5::ArmISA::MMU::S1E3Tran, gem5::ArmISA::MMU::S1S2NsTran, selfDebug, gem5::ArmISA::SelfDebug::setbSDD(), gem5::ArmISA::SelfDebug::setDebugMask(), gem5::ArmISA::SelfDebug::setenableTDETGE(), gem5::ArmISA::SelfDebug::setMDBGen(), gem5::ArmISA::SelfDebug::setMDSCRvals(), gem5::ArmISA::BaseISADevice::setMiscReg(), gem5::ThreadContext::setMiscReg(), setMiscRegNoEffect(), gem5::ThreadContext::setReg(), gem5::ArmISA::sp, gem5::ArmISA::int_reg::Sp0, gem5::ArmISA::int_reg::Sp1, gem5::ArmISA::int_reg::Sp2, gem5::BaseISA::tc, gem5::ArmISA::uao, gem5::ArmISA::unflattenMiscReg(), gem5::ArmISA::SelfDebug::updateDBGBCR(), gem5::ArmISA::SelfDebug::updateDBGWCR(), gem5::ArmISA::SelfDebug::updateOSLock(), updateRegMap(), gem5::ArmISA::MMU::UserMode, gem5::ArmISA::cc_reg::V, gem5::ArmISA::v, gem5::X86ISA::val, warn, warn_once, and gem5::BaseMMU::Write.

setMiscRegNoEffect()

void gem5::ArmISA::ISA::setMiscRegNoEffect ( RegIndex  idx, RegVal  val  )

overridevirtual

Implements gem5::BaseISA.

Definition at line 1052 of file isa.cc.

References gem5::bits(), DPRINTF, getMiscIndices(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::NUM_MISCREGS, gem5::X86ISA::reg, gem5::ArmISA::v, and gem5::X86ISA::val.

Referenced by addressTranslation(), addressTranslation64(), gem5::Gicv3CPUInterface::dropPriority(), gem5::Clint::raiseInterruptPin(), gem5::Gicv3CPUInterface::readMiscReg(), gem5::Gicv3CPUInterface::setBankedMiscReg(), gem5::Gicv3CPUInterface::setMiscReg(), setMiscReg(), gem5::Gicv3CPUInterface::virtualActivateIRQ(), gem5::Gicv3CPUInterface::virtualDeactivateIRQ(), gem5::Gicv3CPUInterface::virtualDropPriority(), and gem5::Gicv3CPUInterface::virtualIncrementEOICount().

setupThreadContext()

void gem5::ArmISA::ISA::setupThreadContext

(

)

Definition at line 518 of file isa.cc.

References getGICv3CPUInterface(), gem5::ArmISA::SelfDebug::init(), pmu, selfDebug, gem5::ArmISA::BaseISADevice::setThreadContext(), system, and gem5::BaseISA::tc.

Referenced by startup(), and takeOverFrom().

snsBankedIndex64()

int gem5::ArmISA::ISA::snsBankedIndex64 ( MiscRegIndex  reg, bool  ns  ) const

inline

Definition at line 323 of file isa.hh.

References gem5::ArmRelease::has(), gem5::ArmISA::lookUpMiscReg, gem5::ArmISA::MISCREG_BANKED64, gem5::ArmISA::ns, gem5::X86ISA::reg, and release.

Referenced by flattenMiscIndex(), gem5::Gicv3CPUInterface::readBankedMiscReg(), and gem5::Gicv3CPUInterface::setBankedMiscReg().

startup()

void gem5::ArmISA::ISA::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from gem5::SimObject.

Definition at line 503 of file isa.cc.

References gem5::ArmRelease::has(), release, gem5::ThreadContext::setHtmCheckpointPtr(), setupThreadContext(), gem5::SimObject::startup(), and gem5::BaseISA::tc.

takeOverFrom()

void gem5::ArmISA::ISA::takeOverFrom ( ThreadContext *  new_tc, ThreadContext *  old_tc  )

overridevirtual

Reimplemented from gem5::BaseISA.

Definition at line 534 of file isa.cc.

References setupThreadContext(), and gem5::BaseISA::tc.

unserialize()

void gem5::ArmISA::ISA::unserialize ( CheckpointIn &  cp )

overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements gem5::Serializable.

Definition at line 2112 of file isa.cc.

References DPRINTF, gem5::ArmISA::MISCREG_CPSR, gem5::ArmISA::miscRegName, miscRegs, gem5::ArmISA::NUM_PHYS_MISCREGS, UNSERIALIZE_MAPPING, and updateRegMap().

updateRegMap()

void gem5::ArmISA::ISA::updateRegMap ( CPSR  cpsr )

inlineprotected

Definition at line 125 of file isa.hh.

References intRegMap, gem5::ArmISA::MODE_ABORT, gem5::ArmISA::MODE_FIQ, gem5::ArmISA::MODE_HYP, gem5::ArmISA::MODE_IRQ, gem5::ArmISA::MODE_MON, gem5::ArmISA::MODE_SVC, gem5::ArmISA::MODE_SYSTEM, gem5::ArmISA::MODE_UNDEFINED, gem5::ArmISA::MODE_USER, panic, gem5::ArmISA::int_reg::Reg64Map, gem5::ArmISA::int_reg::RegAbtMap, gem5::ArmISA::int_reg::RegFiqMap, gem5::ArmISA::int_reg::RegHypMap, gem5::ArmISA::int_reg::RegIrqMap, gem5::ArmISA::int_reg::RegMonMap, gem5::ArmISA::int_reg::RegSvcMap, gem5::ArmISA::int_reg::RegUndMap, and gem5::ArmISA::int_reg::RegUsrMap.

Referenced by clear32(), clear64(), setMiscReg(), and unserialize().

zeroSveVecRegUpperPart()

template<typename Elem >

static void gem5::ArmISA::ISA::zeroSveVecRegUpperPart ( Elem *  v, unsigned  eCount  )

inlinestatic

Definition at line 368 of file isa.hh.

References gem5::ArmISA::i, and gem5::ArmISA::v.

Member Data Documentation

_decoderFlavor

const enums::DecoderFlavor gem5::ArmISA::ISA::_decoderFlavor

protected

Definition at line 76 of file isa.hh.

Referenced by decoderFlavor().

dummyDevice

DummyISADevice gem5::ArmISA::ISA::dummyDevice

protected

Dummy device for to handle non-existing ISA devices.

Definition at line 79 of file isa.hh.

Referenced by ISA().

gicv3CpuInterface

std::unique_ptr<BaseISADevice> gem5::ArmISA::ISA::gicv3CpuInterface

protected

Definition at line 88 of file isa.hh.

Referenced by getGICv3CPUInterface(), readMiscReg(), and setMiscReg().

haveLargeAsid64

bool gem5::ArmISA::ISA::haveLargeAsid64

protected

Definition at line 92 of file isa.hh.

Referenced by initID64(), and ISA().

highestELIs64

bool gem5::ArmISA::ISA::highestELIs64

protected

Definition at line 91 of file isa.hh.

Referenced by flattenMiscIndex(), getMiscIndices(), initializeMiscRegMetadata(), initID32(), ISA(), and setMiscReg().

impdefAsNop

bool gem5::ArmISA::ISA::impdefAsNop

protected

If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION.

Definition at line 105 of file isa.hh.

Referenced by initializeMiscRegMetadata().

intRegMap

const RegId* gem5::ArmISA::ISA::intRegMap

protected

Definition at line 122 of file isa.hh.

Referenced by mapIntRegId(), and updateRegMap().

miscRegs

RegVal gem5::ArmISA::ISA::miscRegs[NUM_MISCREGS]

protected

Definition at line 121 of file isa.hh.

Referenced by clear(), clear32(), clear64(), flattenMiscIndex(), getCurSveVecLenInBits(), initID32(), initID64(), inSecureState(), inUserMode(), ISA(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), and unserialize().

physAddrRange

uint8_t gem5::ArmISA::ISA::physAddrRange

protected

Definition at line 93 of file isa.hh.

Referenced by initID64(), and ISA().

pmu

BaseISADevice* gem5::ArmISA::ISA::pmu

protected

Definition at line 82 of file isa.hh.

Referenced by ISA(), readMiscReg(), setMiscReg(), and setupThreadContext().

release

const ArmRelease* gem5::ArmISA::ISA::release

protected

This could be either a FS or a SE release.

Definition at line 99 of file isa.hh.

Referenced by addressTranslation(), clear32(), clear64(), getCurSveVecLenInBits(), getRelease(), initializeMiscRegMetadata(), initID32(), initID64(), inSecureState(), ISA(), readMiscReg(), redirectRegVHE(), setMiscReg(), snsBankedIndex64(), and startup().

selfDebug

SelfDebug* gem5::ArmISA::ISA::selfDebug

protected

Definition at line 107 of file isa.hh.

Referenced by getSelfDebug(), ISA(), setMiscReg(), and setupThreadContext().

sveVL

unsigned gem5::ArmISA::ISA::sveVL

protected

SVE vector length in quadwords.

Definition at line 96 of file isa.hh.

Referenced by getCurSveVecLenInBits(), getCurSveVecLenInBitsAtReset(), initID64(), and ISA().

system

ArmSystem* gem5::ArmISA::ISA::system

protected

Definition at line 73 of file isa.hh.

Referenced by clear(), clear32(), clear64(), getGenericTimer(), getGICv3CPUInterface(), initializeMiscRegMetadata(), ISA(), readMiscReg(), and setupThreadContext().

timer

std::unique_ptr<BaseISADevice> gem5::ArmISA::ISA::timer

protected

Definition at line 85 of file isa.hh.

Referenced by getGenericTimer().

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The documentation for this class was generated from the following files:

• arch/arm/isa.hh
• arch/arm/isa.cc
• arch/arm/regs/misc.cc