gem5 v24.0.0.0
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Namespaces | Typedefs | Enumerations | Functions | Variables
types.hh File Reference
#include <cstdint>
#include "arch/arm/pcstate.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"

Go to the source code of this file.

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::ArmISA
 

Typedefs

typedef uint32_t gem5::ArmISA::MachInst
 
typedef uint16_t gem5::ArmISA::vmid_t
 
typedef int gem5::ArmISA::RegContextParam
 
typedef int gem5::ArmISA::RegContextVal
 

Enumerations

enum  gem5::ArmISA::ArmExtendType {
  gem5::ArmISA::UXTB = 0 , gem5::ArmISA::UXTH = 1 , gem5::ArmISA::UXTW = 2 , gem5::ArmISA::UXTX = 3 ,
  gem5::ArmISA::SXTB = 4 , gem5::ArmISA::SXTH = 5 , gem5::ArmISA::SXTW = 6 , gem5::ArmISA::SXTX = 7
}
 
enum  gem5::ArmISA::ConvertType {
  gem5::ArmISA::SINGLE_TO_DOUBLE , gem5::ArmISA::SINGLE_TO_WORD , gem5::ArmISA::SINGLE_TO_LONG , gem5::ArmISA::DOUBLE_TO_SINGLE ,
  gem5::ArmISA::DOUBLE_TO_WORD , gem5::ArmISA::DOUBLE_TO_LONG , gem5::ArmISA::LONG_TO_SINGLE , gem5::ArmISA::LONG_TO_DOUBLE ,
  gem5::ArmISA::LONG_TO_WORD , gem5::ArmISA::LONG_TO_PS , gem5::ArmISA::WORD_TO_SINGLE , gem5::ArmISA::WORD_TO_DOUBLE ,
  gem5::ArmISA::WORD_TO_LONG , gem5::ArmISA::WORD_TO_PS , gem5::ArmISA::PL_TO_SINGLE , gem5::ArmISA::PU_TO_SINGLE
}
 
enum  gem5::ArmISA::RoundMode { gem5::ArmISA::RND_ZERO , gem5::ArmISA::RND_DOWN , gem5::ArmISA::RND_UP , gem5::ArmISA::RND_NEAREST }
 
enum  gem5::ArmISA::ExceptionLevel { gem5::ArmISA::EL0 = 0 , gem5::ArmISA::EL1 , gem5::ArmISA::EL2 , gem5::ArmISA::EL3 }
 
enum class  gem5::ArmISA::TranslationRegime { gem5::ArmISA::EL10 , gem5::ArmISA::EL20 , gem5::ArmISA::EL2 , gem5::ArmISA::EL3 }
 
enum  gem5::ArmISA::OperatingMode {
  gem5::ArmISA::MODE_EL0T = 0x0 , gem5::ArmISA::MODE_EL1T = 0x4 , gem5::ArmISA::MODE_EL1H = 0x5 , gem5::ArmISA::MODE_EL2T = 0x8 ,
  gem5::ArmISA::MODE_EL2H = 0x9 , gem5::ArmISA::MODE_EL3T = 0xC , gem5::ArmISA::MODE_EL3H = 0xD , gem5::ArmISA::MODE_USER = 16 ,
  gem5::ArmISA::MODE_FIQ = 17 , gem5::ArmISA::MODE_IRQ = 18 , gem5::ArmISA::MODE_SVC = 19 , gem5::ArmISA::MODE_MON = 22 ,
  gem5::ArmISA::MODE_ABORT = 23 , gem5::ArmISA::MODE_HYP = 26 , gem5::ArmISA::MODE_UNDEFINED = 27 , gem5::ArmISA::MODE_SYSTEM = 31 ,
  gem5::ArmISA::MODE_MAXMODE = MODE_SYSTEM
}
 
enum class  gem5::ArmISA::ExceptionClass {
  gem5::ArmISA::INVALID = -1 , gem5::ArmISA::UNKNOWN = 0x0 , gem5::ArmISA::TRAPPED_WFI_WFE = 0x1 , gem5::ArmISA::TRAPPED_CP15_MCR_MRC = 0x3 ,
  gem5::ArmISA::TRAPPED_CP15_MCRR_MRRC = 0x4 , gem5::ArmISA::TRAPPED_CP14_MCR_MRC = 0x5 , gem5::ArmISA::TRAPPED_CP14_LDC_STC = 0x6 , gem5::ArmISA::TRAPPED_HCPTR = 0x7 ,
  gem5::ArmISA::TRAPPED_SIMD_FP = 0x7 , gem5::ArmISA::TRAPPED_CP10_MRC_VMRS = 0x8 , gem5::ArmISA::TRAPPED_PAC = 0x9 , gem5::ArmISA::TRAPPED_BXJ = 0xA ,
  gem5::ArmISA::TRAPPED_CP14_MCRR_MRRC = 0xC , gem5::ArmISA::ILLEGAL_INST = 0xE , gem5::ArmISA::SVC_TO_HYP = 0x11 , gem5::ArmISA::SVC = 0x11 ,
  gem5::ArmISA::HVC = 0x12 , gem5::ArmISA::SMC_TO_HYP = 0x13 , gem5::ArmISA::SMC = 0x13 , gem5::ArmISA::SVC_64 = 0x15 ,
  gem5::ArmISA::HVC_64 = 0x16 , gem5::ArmISA::SMC_64 = 0x17 , gem5::ArmISA::TRAPPED_MSR_MRS_64 = 0x18 , gem5::ArmISA::TRAPPED_SVE = 0x19 ,
  gem5::ArmISA::TRAPPED_ERET = 0x1A , gem5::ArmISA::TRAPPED_SME = 0x1D , gem5::ArmISA::PREFETCH_ABORT_TO_HYP = 0x20 , gem5::ArmISA::PREFETCH_ABORT_LOWER_EL = 0x20 ,
  gem5::ArmISA::PREFETCH_ABORT_FROM_HYP = 0x21 , gem5::ArmISA::PREFETCH_ABORT_CURR_EL = 0x21 , gem5::ArmISA::PC_ALIGNMENT = 0x22 , gem5::ArmISA::DATA_ABORT_TO_HYP = 0x24 ,
  gem5::ArmISA::DATA_ABORT_LOWER_EL = 0x24 , gem5::ArmISA::DATA_ABORT_FROM_HYP = 0x25 , gem5::ArmISA::DATA_ABORT_CURR_EL = 0x25 , gem5::ArmISA::STACK_PTR_ALIGNMENT = 0x26 ,
  gem5::ArmISA::FP_EXCEPTION = 0x28 , gem5::ArmISA::FP_EXCEPTION_64 = 0x2C , gem5::ArmISA::SERROR = 0x2F , gem5::ArmISA::HW_BREAKPOINT = 0x30 ,
  gem5::ArmISA::HW_BREAKPOINT_LOWER_EL = 0x30 , gem5::ArmISA::HW_BREAKPOINT_CURR_EL = 0x31 , gem5::ArmISA::SOFTWARE_STEP = 0x32 , gem5::ArmISA::SOFTWARE_STEP_LOWER_EL = 0x32 ,
  gem5::ArmISA::SOFTWARE_STEP_CURR_EL = 0x33 , gem5::ArmISA::WATCHPOINT = 0x34 , gem5::ArmISA::WATCHPOINT_LOWER_EL = 0x34 , gem5::ArmISA::WATCHPOINT_CURR_EL = 0x35 ,
  gem5::ArmISA::SOFTWARE_BREAKPOINT = 0x38 , gem5::ArmISA::VECTOR_CATCH = 0x3A , gem5::ArmISA::SOFTWARE_BREAKPOINT_64 = 0x3C
}
 
enum  gem5::ArmISA::DecoderFault : std::uint8_t { gem5::ArmISA::OK = 0x0 , gem5::ArmISA::UNALIGNED = 0x1 , gem5::ArmISA::PANIC = 0x3 }
 Instruction decoder fault codes in ExtMachInst. More...
 

Functions

 gem5::ArmISA::BitUnion64 (ExtMachInst) Bitfield< 63
 
 gem5::ArmISA::SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
 
 gem5::ArmISA::EndSubBitUnion (puswl) Bitfield< 24
 
 gem5::ArmISA::EndBitUnion (ExtMachInst) BitUnion32(Affinity) Bitfield< 31
 
 gem5::ArmISA::EndBitUnion (Affinity) enum ArmShiftType
 
 gem5::ArmISA::BitUnion8 (OperatingMode64) Bitfield< 0 > spX
 
 gem5::ArmISA::EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
 
static bool gem5::ArmISA::opModeIsH (OperatingMode mode)
 
static bool gem5::ArmISA::opModeIsT (OperatingMode mode)
 
static ExceptionLevel gem5::ArmISA::opModeToEL (OperatingMode mode)
 
static bool gem5::ArmISA::unknownMode (OperatingMode mode)
 
static bool gem5::ArmISA::unknownMode32 (OperatingMode mode)
 
static const char * gem5::ArmISA::regimeToStr (TranslationRegime regime)
 

Variables

 gem5::ArmISA::decoderFault
 
Bitfield< 61 > gem5::ArmISA::illegalExecution
 
Bitfield< 60 > gem5::ArmISA::debugStep
 
Bitfield< 59, 56 > gem5::ArmISA::sveLen
 
Bitfield< 55, 48 > gem5::ArmISA::itstate
 
Bitfield< 55, 52 > gem5::ArmISA::itstateCond
 
Bitfield< 51, 48 > gem5::ArmISA::itstateMask
 
Bitfield< 41, 40 > gem5::ArmISA::fpscrStride
 
Bitfield< 39, 37 > gem5::ArmISA::fpscrLen
 
Bitfield< 36 > gem5::ArmISA::thumb
 
Bitfield< 35 > gem5::ArmISA::bigThumb
 
Bitfield< 34 > gem5::ArmISA::aarch64
 
Bitfield< 33 > gem5::ArmISA::sevenAndFour
 
Bitfield< 32 > gem5::ArmISA::isMisc
 
uint32_t gem5::ArmISA::instBits
 
Bitfield< 27, 25 > gem5::ArmISA::encoding
 
Bitfield< 25 > gem5::ArmISA::useImm
 
Bitfield< 24, 21 > gem5::ArmISA::opcode
 
Bitfield< 24, 20 > gem5::ArmISA::mediaOpcode
 
Bitfield< 24 > gem5::ArmISA::opcode24
 
Bitfield< 24, 23 > gem5::ArmISA::opcode24_23
 
Bitfield< 23, 20 > gem5::ArmISA::opcode23_20
 
Bitfield< 23, 21 > gem5::ArmISA::opcode23_21
 
Bitfield< 20 > gem5::ArmISA::opcode20
 
Bitfield< 22 > gem5::ArmISA::opcode22
 
Bitfield< 19, 16 > gem5::ArmISA::opcode19_16
 
Bitfield< 19 > gem5::ArmISA::opcode19
 
Bitfield< 18 > gem5::ArmISA::opcode18
 
Bitfield< 15, 12 > gem5::ArmISA::opcode15_12
 
Bitfield< 15 > gem5::ArmISA::opcode15
 
Bitfield< 7, 4 > gem5::ArmISA::miscOpcode
 
Bitfield< 7, 5 > gem5::ArmISA::opc2
 
Bitfield< 7 > gem5::ArmISA::opcode7
 
Bitfield< 6 > gem5::ArmISA::opcode6
 
Bitfield< 4 > gem5::ArmISA::opcode4
 
Bitfield< 31, 28 > gem5::ArmISA::condCode
 
Bitfield< 20 > gem5::ArmISA::sField
 
Bitfield< 19, 16 > gem5::ArmISA::rn
 
Bitfield< 15, 12 > gem5::ArmISA::rd
 
Bitfield< 15, 12 > gem5::ArmISA::rt
 
Bitfield< 11, 7 > gem5::ArmISA::shiftSize
 
Bitfield< 6, 5 > gem5::ArmISA::shift
 
Bitfield< 3, 0 > gem5::ArmISA::rm
 
Bitfield< 23 > gem5::ArmISA::up
 
Bitfield< 22 > gem5::ArmISA::psruser
 
Bitfield< 21 > gem5::ArmISA::writeback
 
Bitfield< 20 > gem5::ArmISA::loadOp
 
 gem5::ArmISA::pubwl
 
Bitfield< 7, 0 > gem5::ArmISA::imm
 
Bitfield< 11, 8 > gem5::ArmISA::rotate
 
Bitfield< 11, 0 > gem5::ArmISA::immed11_0
 
Bitfield< 7, 0 > gem5::ArmISA::immed7_0
 
Bitfield< 11, 8 > gem5::ArmISA::immedHi11_8
 
Bitfield< 3, 0 > gem5::ArmISA::immedLo3_0
 
Bitfield< 15, 0 > gem5::ArmISA::regList
 
Bitfield< 23, 0 > gem5::ArmISA::offset
 
Bitfield< 23, 0 > gem5::ArmISA::immed23_0
 
Bitfield< 11, 8 > gem5::ArmISA::cpNum
 
Bitfield< 18, 16 > gem5::ArmISA::fn
 
Bitfield< 14, 12 > gem5::ArmISA::fd
 
Bitfield< 3 > gem5::ArmISA::fpRegImm
 
Bitfield< 3, 0 > gem5::ArmISA::fm
 
Bitfield< 2, 0 > gem5::ArmISA::fpImm
 
Bitfield< 24, 20 > gem5::ArmISA::punwl
 
Bitfield< 15, 8 > gem5::ArmISA::m5Func
 
Bitfield< 15, 13 > gem5::ArmISA::topcode15_13
 
Bitfield< 13, 11 > gem5::ArmISA::topcode13_11
 
Bitfield< 12, 11 > gem5::ArmISA::topcode12_11
 
Bitfield< 12, 10 > gem5::ArmISA::topcode12_10
 
Bitfield< 11, 9 > gem5::ArmISA::topcode11_9
 
Bitfield< 11, 8 > gem5::ArmISA::topcode11_8
 
Bitfield< 10, 9 > gem5::ArmISA::topcode10_9
 
Bitfield< 10, 8 > gem5::ArmISA::topcode10_8
 
Bitfield< 9, 6 > gem5::ArmISA::topcode9_6
 
Bitfield< 7 > gem5::ArmISA::topcode7
 
Bitfield< 7, 6 > gem5::ArmISA::topcode7_6
 
Bitfield< 7, 5 > gem5::ArmISA::topcode7_5
 
Bitfield< 7, 4 > gem5::ArmISA::topcode7_4
 
Bitfield< 3, 0 > gem5::ArmISA::topcode3_0
 
Bitfield< 28, 27 > gem5::ArmISA::htopcode12_11
 
Bitfield< 26, 25 > gem5::ArmISA::htopcode10_9
 
Bitfield< 25 > gem5::ArmISA::htopcode9
 
Bitfield< 25, 24 > gem5::ArmISA::htopcode9_8
 
Bitfield< 25, 21 > gem5::ArmISA::htopcode9_5
 
Bitfield< 25, 20 > gem5::ArmISA::htopcode9_4
 
Bitfield< 24 > gem5::ArmISA::htopcode8
 
Bitfield< 24, 23 > gem5::ArmISA::htopcode8_7
 
Bitfield< 24, 22 > gem5::ArmISA::htopcode8_6
 
Bitfield< 24, 21 > gem5::ArmISA::htopcode8_5
 
Bitfield< 23 > gem5::ArmISA::htopcode7
 
Bitfield< 23, 21 > gem5::ArmISA::htopcode7_5
 
Bitfield< 22 > gem5::ArmISA::htopcode6
 
Bitfield< 22, 21 > gem5::ArmISA::htopcode6_5
 
Bitfield< 21, 20 > gem5::ArmISA::htopcode5_4
 
Bitfield< 20 > gem5::ArmISA::htopcode4
 
Bitfield< 19, 16 > gem5::ArmISA::htrn
 
Bitfield< 20 > gem5::ArmISA::hts
 
Bitfield< 15 > gem5::ArmISA::ltopcode15
 
Bitfield< 11, 8 > gem5::ArmISA::ltopcode11_8
 
Bitfield< 7, 6 > gem5::ArmISA::ltopcode7_6
 
Bitfield< 7, 4 > gem5::ArmISA::ltopcode7_4
 
Bitfield< 4 > gem5::ArmISA::ltopcode4
 
Bitfield< 11, 8 > gem5::ArmISA::ltrd
 
Bitfield< 11, 8 > gem5::ArmISA::ltcoproc
 
 gem5::ArmISA::aff3
 
Bitfield< 23, 16 > gem5::ArmISA::aff2
 
Bitfield< 15, 8 > gem5::ArmISA::aff1
 
Bitfield< 7, 0 > gem5::ArmISA::aff0
 
constexpr unsigned gem5::ArmISA::MaxSveVecLenInBits = 2048
 
constexpr unsigned gem5::ArmISA::MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
 
constexpr unsigned gem5::ArmISA::MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
 
constexpr unsigned gem5::ArmISA::MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
 
constexpr unsigned gem5::ArmISA::VecRegSizeBytes = MaxSveVecLenInBytes
 
constexpr unsigned gem5::ArmISA::VecPredRegSizeBits = MaxSveVecLenInBytes
 
constexpr unsigned gem5::ArmISA::MaxSmeVecLenInBits = 2048
 
constexpr unsigned gem5::ArmISA::MaxSmeVecLenInBytes = MaxSmeVecLenInBits >> 3
 
constexpr unsigned gem5::ArmISA::MaxSmeVecLenInWords = MaxSmeVecLenInBits >> 5
 
constexpr unsigned gem5::ArmISA::MaxSmeVecLenInDWords = MaxSmeVecLenInBits >> 6
 
Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0