gem5  v21.1.0.2
pcstate.hh
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40 
41 #ifndef __ARCH_ARM_PCSTATE_HH__
42 #define __ARCH_ARM_PCSTATE_HH__
43 
44 #include "arch/generic/types.hh"
45 #include "base/bitunion.hh"
46 #include "base/types.hh"
47 #include "debug/Decoder.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
55 BitUnion8(ITSTATE)
56  /* Note that the split (cond, mask) below is not as in ARM ARM.
57  * But it is more convenient for simulation. The condition
58  * is always the concatenation of the top 3 bits and the next bit,
59  * which applies when one of the bottom 4 bits is set.
60  * Refer to predecoder.cc for the use case.
61  */
62  Bitfield<7, 4> cond;
63  Bitfield<3, 0> mask;
64  // Bitfields for moving to/from CPSR
65  Bitfield<7, 2> top6;
66  Bitfield<1, 0> bottom2;
67 EndBitUnion(ITSTATE)
68 
69 class PCState : public GenericISA::UPCState<4>
70 {
71  protected:
72 
74 
75  enum FlagBits
76  {
77  ThumbBit = (1 << 0),
78  JazelleBit = (1 << 1),
79  AArch64Bit = (1 << 2)
80  };
81 
82  uint8_t flags;
83  uint8_t nextFlags;
84  uint8_t _itstate;
85  uint8_t _nextItstate;
86  uint8_t _size;
87  bool _illegalExec;
88 
89  // Software Step flags
90  bool _debugStep;
91  bool _stepped;
92 
93  public:
94  PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
95  _size(0), _illegalExec(false), _debugStep(false),
96  _stepped(false)
97  {}
98 
99  void
100  set(Addr val)
101  {
102  Base::set(val);
103  npc(val + (thumb() ? 2 : 4));
104  }
105 
106  PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
107  _nextItstate(0), _size(0), _illegalExec(false),
108  _debugStep(false), _stepped(false)
109  { set(val); }
110 
111  bool
112  illegalExec() const
113  {
114  return _illegalExec;
115  }
116 
117  void
118  illegalExec(bool val)
119  {
120  _illegalExec = val;
121  }
122 
123  bool
124  debugStep() const
125  {
126  return _debugStep;
127  }
128 
129  void
130  debugStep(bool val)
131  {
132  _debugStep = val;
133  }
134 
135  bool
136  stepped() const
137  {
138  return _stepped;
139  }
140 
141  void
142  stepped(bool val)
143  {
144  _stepped = val;
145  }
146 
147  bool
148  thumb() const
149  {
150  return flags & ThumbBit;
151  }
152 
153  void
154  thumb(bool val)
155  {
156  if (val)
157  flags |= ThumbBit;
158  else
159  flags &= ~ThumbBit;
160  }
161 
162  bool
163  nextThumb() const
164  {
165  return nextFlags & ThumbBit;
166  }
167 
168  void
169  nextThumb(bool val)
170  {
171  if (val)
172  nextFlags |= ThumbBit;
173  else
174  nextFlags &= ~ThumbBit;
175  }
176 
177  void size(uint8_t s) { _size = s; }
178  uint8_t size() const { return _size; }
179 
180  bool
181  branching() const
182  {
183  return ((this->pc() + this->size()) != this->npc());
184  }
185 
186 
187  bool
188  jazelle() const
189  {
190  return flags & JazelleBit;
191  }
192 
193  void
194  jazelle(bool val)
195  {
196  if (val)
197  flags |= JazelleBit;
198  else
199  flags &= ~JazelleBit;
200  }
201 
202  bool
203  nextJazelle() const
204  {
205  return nextFlags & JazelleBit;
206  }
207 
208  void
209  nextJazelle(bool val)
210  {
211  if (val)
212  nextFlags |= JazelleBit;
213  else
214  nextFlags &= ~JazelleBit;
215  }
216 
217  bool
218  aarch64() const
219  {
220  return flags & AArch64Bit;
221  }
222 
223  void
224  aarch64(bool val)
225  {
226  if (val)
227  flags |= AArch64Bit;
228  else
229  flags &= ~AArch64Bit;
230  }
231 
232  bool
233  nextAArch64() const
234  {
235  return nextFlags & AArch64Bit;
236  }
237 
238  void
239  nextAArch64(bool val)
240  {
241  if (val)
242  nextFlags |= AArch64Bit;
243  else
244  nextFlags &= ~AArch64Bit;
245  }
246 
247 
248  uint8_t
249  itstate() const
250  {
251  return _itstate;
252  }
253 
254  void
255  itstate(uint8_t value)
256  {
257  _itstate = value;
258  }
259 
260  uint8_t
261  nextItstate() const
262  {
263  return _nextItstate;
264  }
265 
266  void
267  nextItstate(uint8_t value)
268  {
269  _nextItstate = value;
270  }
271 
272  void
273  advance()
274  {
275  Base::advance();
276  flags = nextFlags;
277  npc(pc() + (thumb() ? 2 : 4));
278 
279  if (_nextItstate) {
280  _itstate = _nextItstate;
281  _nextItstate = 0;
282  } else if (_itstate) {
283  ITSTATE it = _itstate;
284  uint8_t cond_mask = it.mask;
285  uint8_t thumb_cond = it.cond;
286  DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
287  thumb_cond, cond_mask);
288  cond_mask <<= 1;
289  uint8_t new_bit = bits(cond_mask, 4);
290  cond_mask &= mask(4);
291  if (cond_mask == 0)
292  thumb_cond = 0;
293  else
294  replaceBits(thumb_cond, 0, new_bit);
295  DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
296  thumb_cond, cond_mask);
297  it.mask = cond_mask;
298  it.cond = thumb_cond;
299  _itstate = it;
300  }
301  }
302 
303  void
304  uEnd()
305  {
306  advance();
307  upc(0);
308  nupc(1);
309  }
310 
311  Addr
312  instPC() const
313  {
314  return pc() + (thumb() ? 4 : 8);
315  }
316 
317  void
318  instNPC(Addr val)
319  {
320  // @todo: review this when AArch32/64 interprocessing is
321  // supported
322  if (aarch64())
323  npc(val); // AArch64 doesn't force PC alignment, a PC
324  // Alignment Fault can be raised instead
325  else
326  npc(val &~ mask(nextThumb() ? 1 : 2));
327  }
328 
329  Addr
330  instNPC() const
331  {
332  return npc();
333  }
334 
335  // Perform an interworking branch.
336  void
337  instIWNPC(Addr val)
338  {
339  bool thumbEE = (thumb() && jazelle());
340 
341  Addr newPC = val;
342  if (thumbEE) {
343  if (bits(newPC, 0)) {
344  newPC = newPC & ~mask(1);
345  } // else we have a bad interworking address; do not call
346  // panic() since the instruction could be executed
347  // speculatively
348  } else {
349  if (bits(newPC, 0)) {
350  nextThumb(true);
351  newPC = newPC & ~mask(1);
352  } else if (!bits(newPC, 1)) {
353  nextThumb(false);
354  } else {
355  // This state is UNPREDICTABLE in the ARM architecture
356  // The easy thing to do is just mask off the bit and
357  // stay in the current mode, so we'll do that.
358  newPC &= ~mask(2);
359  }
360  }
361  npc(newPC);
362  }
363 
364  // Perform an interworking branch in ARM mode, a regular branch
365  // otherwise.
366  void
367  instAIWNPC(Addr val)
368  {
369  if (!thumb() && !jazelle())
370  instIWNPC(val);
371  else
372  instNPC(val);
373  }
374 
375  bool
376  operator == (const PCState &opc) const
377  {
378  return Base::operator == (opc) &&
379  flags == opc.flags && nextFlags == opc.nextFlags &&
380  _itstate == opc._itstate &&
381  _nextItstate == opc._nextItstate &&
382  _illegalExec == opc._illegalExec &&
383  _debugStep == opc._debugStep &&
384  _stepped == opc._stepped;
385  }
386 
387  bool
388  operator != (const PCState &opc) const
389  {
390  return !(*this == opc);
391  }
392 
393  void
394  serialize(CheckpointOut &cp) const override
395  {
396  Base::serialize(cp);
397  SERIALIZE_SCALAR(flags);
398  SERIALIZE_SCALAR(_size);
399  SERIALIZE_SCALAR(nextFlags);
400  SERIALIZE_SCALAR(_itstate);
401  SERIALIZE_SCALAR(_nextItstate);
402  SERIALIZE_SCALAR(_illegalExec);
403  SERIALIZE_SCALAR(_debugStep);
404  SERIALIZE_SCALAR(_stepped);
405  }
406 
407  void
408  unserialize(CheckpointIn &cp) override
409  {
410  Base::unserialize(cp);
411  UNSERIALIZE_SCALAR(flags);
412  UNSERIALIZE_SCALAR(_size);
413  UNSERIALIZE_SCALAR(nextFlags);
414  UNSERIALIZE_SCALAR(_itstate);
415  UNSERIALIZE_SCALAR(_nextItstate);
416  UNSERIALIZE_SCALAR(_illegalExec);
417  UNSERIALIZE_SCALAR(_debugStep);
418  UNSERIALIZE_SCALAR(_stepped);
419  }
420 };
421 
422 } // namespace ArmISA
423 } // namespace gem5
424 
425 #endif
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::operator!=
bool operator!=(const RefCountingPtr< T > &l, const RefCountingPtr< T > &r)
Check for inequality of two reference counting pointers.
Definition: refcnt.hh:294
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::ArmISA::aarch64
Bitfield< 34 > aarch64
Definition: types.hh:81
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::GenericISA::UPCState< 4 >
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ArmISA::bottom2
Bitfield< 1, 0 > bottom2
Definition: pcstate.hh:66
gem5::ArmISA::debugStep
Bitfield< 60 > debugStep
Definition: types.hh:63
gem5::PowerISA::PCState
Definition: pcstate.hh:42
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@ Base
Definition: aux_vector.hh:76
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::operator==
static bool operator==(const ExtMachInst &emi1, const ExtMachInst &emi2)
Definition: types.hh:260
gem5::ArmISA::BitUnion8
BitUnion8(ITSTATE) Bitfield< 7
bitunion.hh
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::operator==
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Definition: pixel.hh:73
gem5::ArmISA::Decoder
Definition: decoder.hh:62
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
types.hh
gem5::ArmISA::EndBitUnion
EndBitUnion(PackedIntReg) enum IntRegIndex
Definition: int.hh:63
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Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::top6
Bitfield< 7, 2 > top6
Definition: pcstate.hh:65
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::SparcISA::PCState
GenericISA::DelaySlotUPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::thumb
Bitfield< 36 > thumb
Definition: types.hh:79
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::itstate
Bitfield< 55, 48 > itstate
Definition: types.hh:70
gem5::ArmISA::cond
cond
Definition: pcstate.hh:62

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