gem5  v22.1.0.0
types.hh
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40 
41 #ifndef __ARCH_ARM_TYPES_HH__
42 #define __ARCH_ARM_TYPES_HH__
43 
44 #include <cstdint>
45 
46 #include "arch/arm/pcstate.hh"
47 #include "base/bitunion.hh"
48 #include "base/logging.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ArmISA
54 {
55  typedef uint32_t MachInst;
56 
57  typedef uint16_t vmid_t;
58 
60  // Decoder state
61  Bitfield<63, 62> decoderFault; // See DecoderFault
62  Bitfield<61> illegalExecution;
63  Bitfield<60> debugStep;
64 
65  // SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
66  // bitfields
67  Bitfield<59, 56> sveLen;
68 
69  // ITSTATE bits
70  Bitfield<55, 48> itstate;
71  Bitfield<55, 52> itstateCond;
72  Bitfield<51, 48> itstateMask;
73 
74  // FPSCR fields
75  Bitfield<41, 40> fpscrStride;
76  Bitfield<39, 37> fpscrLen;
77 
78  // Bitfields to select mode.
79  Bitfield<36> thumb;
80  Bitfield<35> bigThumb;
81  Bitfield<34> aarch64;
82 
83  // Made up bitfields that make life easier.
84  Bitfield<33> sevenAndFour;
85  Bitfield<32> isMisc;
86 
87  uint32_t instBits;
88 
89  // All the different types of opcode fields.
90  Bitfield<27, 25> encoding;
91  Bitfield<25> useImm;
92  Bitfield<24, 21> opcode;
93  Bitfield<24, 20> mediaOpcode;
94  Bitfield<24> opcode24;
95  Bitfield<24, 23> opcode24_23;
96  Bitfield<23, 20> opcode23_20;
97  Bitfield<23, 21> opcode23_21;
98  Bitfield<20> opcode20;
99  Bitfield<22> opcode22;
100  Bitfield<19, 16> opcode19_16;
101  Bitfield<19> opcode19;
102  Bitfield<18> opcode18;
103  Bitfield<15, 12> opcode15_12;
104  Bitfield<15> opcode15;
105  Bitfield<7, 4> miscOpcode;
106  Bitfield<7,5> opc2;
107  Bitfield<7> opcode7;
108  Bitfield<6> opcode6;
109  Bitfield<4> opcode4;
110 
111  Bitfield<31, 28> condCode;
112  Bitfield<20> sField;
113  Bitfield<19, 16> rn;
114  Bitfield<15, 12> rd;
115  Bitfield<15, 12> rt;
116  Bitfield<11, 7> shiftSize;
117  Bitfield<6, 5> shift;
118  Bitfield<3, 0> rm;
119 
120  Bitfield<11, 8> rs;
121 
122  SubBitUnion(puswl, 24, 20)
123  Bitfield<24> prepost;
124  Bitfield<23> up;
125  Bitfield<22> psruser;
126  Bitfield<21> writeback;
127  Bitfield<20> loadOp;
129 
130  Bitfield<24, 20> pubwl;
131 
132  Bitfield<7, 0> imm;
133 
134  Bitfield<11, 8> rotate;
135 
136  Bitfield<11, 0> immed11_0;
137  Bitfield<7, 0> immed7_0;
138 
139  Bitfield<11, 8> immedHi11_8;
140  Bitfield<3, 0> immedLo3_0;
141 
142  Bitfield<15, 0> regList;
143 
144  Bitfield<23, 0> offset;
145 
146  Bitfield<23, 0> immed23_0;
147 
148  Bitfield<11, 8> cpNum;
149  Bitfield<18, 16> fn;
150  Bitfield<14, 12> fd;
151  Bitfield<3> fpRegImm;
152  Bitfield<3, 0> fm;
153  Bitfield<2, 0> fpImm;
154  Bitfield<24, 20> punwl;
155 
156  Bitfield<15, 8> m5Func;
157 
158  // 16 bit thumb bitfields
159  Bitfield<15, 13> topcode15_13;
160  Bitfield<13, 11> topcode13_11;
161  Bitfield<12, 11> topcode12_11;
162  Bitfield<12, 10> topcode12_10;
163  Bitfield<11, 9> topcode11_9;
164  Bitfield<11, 8> topcode11_8;
165  Bitfield<10, 9> topcode10_9;
166  Bitfield<10, 8> topcode10_8;
167  Bitfield<9, 6> topcode9_6;
168  Bitfield<7> topcode7;
169  Bitfield<7, 6> topcode7_6;
170  Bitfield<7, 5> topcode7_5;
171  Bitfield<7, 4> topcode7_4;
172  Bitfield<3, 0> topcode3_0;
173 
174  // 32 bit thumb bitfields
175  Bitfield<28, 27> htopcode12_11;
176  Bitfield<26, 25> htopcode10_9;
177  Bitfield<25> htopcode9;
178  Bitfield<25, 24> htopcode9_8;
179  Bitfield<25, 21> htopcode9_5;
180  Bitfield<25, 20> htopcode9_4;
181  Bitfield<24> htopcode8;
182  Bitfield<24, 23> htopcode8_7;
183  Bitfield<24, 22> htopcode8_6;
184  Bitfield<24, 21> htopcode8_5;
185  Bitfield<23> htopcode7;
186  Bitfield<23, 21> htopcode7_5;
187  Bitfield<22> htopcode6;
188  Bitfield<22, 21> htopcode6_5;
189  Bitfield<21, 20> htopcode5_4;
190  Bitfield<20> htopcode4;
191 
192  Bitfield<19, 16> htrn;
193  Bitfield<20> hts;
194 
195  Bitfield<15> ltopcode15;
196  Bitfield<11, 8> ltopcode11_8;
197  Bitfield<7, 6> ltopcode7_6;
198  Bitfield<7, 4> ltopcode7_4;
199  Bitfield<4> ltopcode4;
200 
201  Bitfield<11, 8> ltrd;
202  Bitfield<11, 8> ltcoproc;
204 
205  BitUnion32(Affinity)
206  Bitfield<31, 24> aff3;
207  Bitfield<23, 16> aff2;
208  Bitfield<15, 8> aff1;
209  Bitfield<7, 0> aff0;
210  EndBitUnion(Affinity)
211 
212  // Shift types for ARM instructions
213  enum ArmShiftType
214  {
215  LSL = 0,
216  LSR,
217  ASR,
218  ROR
219  };
220 
221  // Extension types for ARM instructions
223  {
224  UXTB = 0,
225  UXTH = 1,
226  UXTW = 2,
227  UXTX = 3,
228  SXTB = 4,
229  SXTH = 5,
230  SXTW = 6,
231  SXTX = 7
232  };
233 
234  typedef int RegContextParam;
235  typedef int RegContextVal;
236 
237  //used in FP convert & round function
239  {
243 
247 
252 
257 
260  };
261 
262  //used in FP convert & round function
264  {
269  };
270 
272  {
273  EL0 = 0,
276  EL3
277  };
278 
280  {
281  MODE_EL0T = 0x0,
282  MODE_EL1T = 0x4,
283  MODE_EL1H = 0x5,
284  MODE_EL2T = 0x8,
285  MODE_EL2H = 0x9,
286  MODE_EL3T = 0xC,
287  MODE_EL3H = 0xD,
288  MODE_USER = 16,
289  MODE_FIQ = 17,
290  MODE_IRQ = 18,
291  MODE_SVC = 19,
292  MODE_MON = 22,
294  MODE_HYP = 26,
298  };
299 
300  enum class ExceptionClass
301  {
302  INVALID = -1,
303  UNKNOWN = 0x0,
304  TRAPPED_WFI_WFE = 0x1,
305  TRAPPED_CP15_MCR_MRC = 0x3,
307  TRAPPED_CP14_MCR_MRC = 0x5,
308  TRAPPED_CP14_LDC_STC = 0x6,
309  TRAPPED_HCPTR = 0x7,
310  TRAPPED_SIMD_FP = 0x7, // AArch64 alias
311  TRAPPED_CP10_MRC_VMRS = 0x8,
312  TRAPPED_PAC = 0x9,
313  TRAPPED_BXJ = 0xA,
315  ILLEGAL_INST = 0xE,
316  SVC_TO_HYP = 0x11,
317  SVC = 0x11, // AArch64 alias
318  HVC = 0x12,
319  SMC_TO_HYP = 0x13,
320  SMC = 0x13, // AArch64 alias
321  SVC_64 = 0x15,
322  HVC_64 = 0x16,
323  SMC_64 = 0x17,
324  TRAPPED_MSR_MRS_64 = 0x18,
325  TRAPPED_SVE = 0x19,
326  PREFETCH_ABORT_TO_HYP = 0x20,
327  PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
329  PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
330  PC_ALIGNMENT = 0x22,
331  DATA_ABORT_TO_HYP = 0x24,
332  DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
333  DATA_ABORT_FROM_HYP = 0x25,
334  DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
335  STACK_PTR_ALIGNMENT = 0x26,
336  FP_EXCEPTION = 0x28,
337  FP_EXCEPTION_64 = 0x2C,
338  SERROR = 0x2F,
339  HW_BREAKPOINT = 0x30,
340  HW_BREAKPOINT_LOWER_EL = 0x30,
341  HW_BREAKPOINT_CURR_EL = 0x31,
342  SOFTWARE_STEP = 0x32,
343  SOFTWARE_STEP_LOWER_EL = 0x32,
344  SOFTWARE_STEP_CURR_EL = 0x33,
345  WATCHPOINT = 0x34,
346  WATCHPOINT_LOWER_EL = 0x34,
347  WATCHPOINT_CURR_EL = 0x35,
348  SOFTWARE_BREAKPOINT = 0x38,
349  VECTOR_CATCH = 0x3A,
350  SOFTWARE_BREAKPOINT_64 = 0x3C,
351  };
352 
356  enum DecoderFault : std::uint8_t
357  {
358  OK = 0x0,
359  UNALIGNED = 0x1,
360 
361  PANIC = 0x3,
362  };
363 
364  BitUnion8(OperatingMode64)
365  Bitfield<0> spX;
366  Bitfield<3, 2> el;
367  Bitfield<4> width;
368  EndBitUnion(OperatingMode64)
369 
370  static bool inline
371  opModeIs64(OperatingMode mode)
372  {
373  return ((OperatingMode64)(uint8_t)mode).width == 0;
374  }
375 
376  static bool inline
378  {
379  return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H);
380  }
381 
382  static bool inline
384  {
385  return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T ||
386  mode == MODE_EL3T);
387  }
388 
389  static ExceptionLevel inline
391  {
392  bool aarch32 = ((mode >> 4) & 1) ? true : false;
393  if (aarch32) {
394  switch (mode) {
395  case MODE_USER:
396  return EL0;
397  case MODE_FIQ:
398  case MODE_IRQ:
399  case MODE_SVC:
400  case MODE_ABORT:
401  case MODE_UNDEFINED:
402  case MODE_SYSTEM:
403  return EL1;
404  case MODE_HYP:
405  return EL2;
406  case MODE_MON:
407  return EL3;
408  default:
409  panic("Invalid operating mode: %d", mode);
410  break;
411  }
412  } else {
413  // aarch64
414  return (ExceptionLevel) ((mode >> 2) & 3);
415  }
416  }
417 
418  static inline bool
420  {
421  switch (mode) {
422  case MODE_EL0T:
423  case MODE_EL1T:
424  case MODE_EL1H:
425  case MODE_EL2T:
426  case MODE_EL2H:
427  case MODE_EL3T:
428  case MODE_EL3H:
429  case MODE_USER:
430  case MODE_FIQ:
431  case MODE_IRQ:
432  case MODE_SVC:
433  case MODE_MON:
434  case MODE_ABORT:
435  case MODE_HYP:
436  case MODE_UNDEFINED:
437  case MODE_SYSTEM:
438  return false;
439  default:
440  return true;
441  }
442  }
443 
444  static inline bool
446  {
447  switch (mode) {
448  case MODE_USER:
449  case MODE_FIQ:
450  case MODE_IRQ:
451  case MODE_SVC:
452  case MODE_MON:
453  case MODE_ABORT:
454  case MODE_HYP:
455  case MODE_UNDEFINED:
456  case MODE_SYSTEM:
457  return false;
458  default:
459  return true;
460  }
461  }
462 
463  constexpr unsigned MaxSveVecLenInBits = 2048;
464  static_assert(MaxSveVecLenInBits >= 128 &&
465  MaxSveVecLenInBits <= 2048 &&
466  MaxSveVecLenInBits % 128 == 0,
467  "Unsupported max. SVE vector length");
468  constexpr unsigned MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3;
469  constexpr unsigned MaxSveVecLenInWords = MaxSveVecLenInBits >> 5;
470  constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6;
471 
472  constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes;
474 
475 } // namespace ArmISA
476 } // namespace gem5
477 
478 #endif
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
Bitfield< 24 > htopcode8
Definition: types.hh:181
Bitfield< 18, 16 > fn
Definition: types.hh:149
Bitfield< 11, 8 > cpNum
Definition: types.hh:148
Bitfield< 33 > sevenAndFour
Definition: types.hh:84
@ MODE_SYSTEM
Definition: types.hh:296
@ MODE_ABORT
Definition: types.hh:293
@ MODE_UNDEFINED
Definition: types.hh:295
@ MODE_MAXMODE
Definition: types.hh:297
Bitfield< 14, 12 > fd
Definition: types.hh:150
int RegContextVal
Definition: types.hh:235
Bitfield< 7, 6 > topcode7_6
Definition: types.hh:169
Bitfield< 10, 8 > topcode10_8
Definition: types.hh:166
Bitfield< 25 > htopcode9
Definition: types.hh:177
static bool opModeIsT(OperatingMode mode)
Definition: types.hh:383
Bitfield< 15, 8 > aff1
Definition: types.hh:208
Bitfield< 11, 9 > topcode11_9
Definition: types.hh:163
Bitfield< 11, 0 > immed11_0
Definition: types.hh:136
@ RND_NEAREST
Definition: types.hh:268
Bitfield< 15, 12 > rd
Definition: types.hh:114
Bitfield< 15, 12 > rt
Definition: types.hh:115
Bitfield< 32 > isMisc
Definition: types.hh:85
Bitfield< 24, 20 > punwl
Definition: types.hh:154
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
Bitfield< 4 > width
Definition: misc_types.hh:72
Bitfield< 3 > fpRegImm
Definition: types.hh:151
Bitfield< 11, 8 > immedHi11_8
Definition: types.hh:139
Bitfield< 3, 0 > rm
Definition: types.hh:118
Bitfield< 11, 8 > ltrd
Definition: types.hh:201
Bitfield< 3, 0 > topcode3_0
Definition: types.hh:172
Bitfield< 7, 0 > immed7_0
Definition: types.hh:137
Bitfield< 31, 28 > condCode
Definition: types.hh:111
EndSubBitUnion(cond_iss) SubBitUnion(data_abort_iss
Bitfield< 24, 23 > htopcode8_7
Definition: types.hh:182
Bitfield< 9, 6 > topcode9_6
Definition: types.hh:167
Bitfield< 13, 11 > topcode13_11
Definition: types.hh:160
Bitfield< 4 > opcode4
Definition: types.hh:109
Bitfield< 7, 0 > imm
Definition: types.hh:132
Bitfield< 23 > htopcode7
Definition: types.hh:185
Bitfield< 51, 48 > itstateMask
Definition: types.hh:72
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:445
Bitfield< 21 > writeback
Definition: types.hh:126
Bitfield< 15, 0 > regList
Definition: types.hh:142
Bitfield< 7, 4 > miscOpcode
Definition: types.hh:105
static bool unknownMode(OperatingMode mode)
Definition: types.hh:419
constexpr unsigned VecPredRegSizeBits
Definition: types.hh:473
Bitfield< 18 > opcode18
Definition: types.hh:102
Bitfield< 15 > ltopcode15
Definition: types.hh:195
Bitfield< 23, 0 > offset
Definition: types.hh:144
Bitfield< 24, 21 > htopcode8_5
Definition: types.hh:184
Bitfield< 9, 8 > rs
Definition: misc_types.hh:383
Bitfield< 60 > debugStep
Definition: types.hh:63
Bitfield< 3, 0 > fm
Definition: types.hh:152
Bitfield< 24 > opcode24
Definition: types.hh:94
Bitfield< 26, 25 > htopcode10_9
Definition: types.hh:176
Bitfield< 36 > thumb
Definition: types.hh:79
Bitfield< 22 > htopcode6
Definition: types.hh:187
Bitfield< 23 > up
Definition: types.hh:124
Bitfield< 19, 16 > rn
Definition: types.hh:113
Bitfield< 22 > psruser
Definition: types.hh:125
Bitfield< 10, 9 > topcode10_9
Definition: types.hh:165
Bitfield< 7, 5 > opc2
Definition: types.hh:106
Bitfield< 25, 21 > htopcode9_5
Definition: types.hh:179
Bitfield< 7, 5 > topcode7_5
Definition: types.hh:170
Bitfield< 15, 13 > topcode15_13
Definition: types.hh:159
Bitfield< 15 > opcode15
Definition: types.hh:104
DecoderFault
Instruction decoder fault codes in ExtMachInst.
Definition: types.hh:357
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:359
@ OK
No fault.
Definition: types.hh:358
@ PANIC
Internal gem5 error.
Definition: types.hh:361
Bitfield< 7, 4 > topcode7_4
Definition: types.hh:171
Bitfield< 41, 40 > fpscrStride
Definition: types.hh:75
Bitfield< 39, 37 > fpscrLen
Definition: types.hh:76
Bitfield< 11, 8 > ltcoproc
Definition: types.hh:202
Bitfield< 15, 8 > m5Func
Definition: types.hh:156
Bitfield< 20 > opcode20
Definition: types.hh:98
Bitfield< 6 > opcode6
Definition: types.hh:108
Bitfield< 22, 21 > htopcode6_5
Definition: types.hh:188
uint32_t MachInst
Definition: types.hh:55
Bitfield< 23, 20 > opcode23_20
Definition: types.hh:96
constexpr unsigned MaxSveVecLenInWords
Definition: types.hh:469
static bool opModeIsH(OperatingMode mode)
Definition: types.hh:377
constexpr unsigned VecRegSizeBytes
Definition: types.hh:472
Bitfield< 25 > useImm
Definition: types.hh:91
Bitfield< 55, 52 > itstateCond
Definition: types.hh:71
SubBitUnion(cond_iss, 24, 0) Bitfield< 24 > cv
constexpr unsigned MaxSveVecLenInDWords
Definition: types.hh:470
Bitfield< 55, 48 > itstate
Definition: types.hh:70
Bitfield< 24, 23 > opcode24_23
Definition: types.hh:95
Bitfield< 23, 16 > aff2
Definition: types.hh:207
Bitfield< 25, 24 > htopcode9_8
Definition: types.hh:178
constexpr unsigned MaxSveVecLenInBits
Definition: types.hh:463
Bitfield< 7, 0 > aff0
Definition: types.hh:209
Bitfield< 23, 21 > opcode23_21
Definition: types.hh:97
uint32_t instBits
Definition: types.hh:87
Bitfield< 20 > sField
Definition: types.hh:112
Bitfield< 19 > opcode19
Definition: types.hh:101
EndBitUnion(PackedIntReg) namespace int_reg
Definition: int.hh:65
Bitfield< 7 > topcode7
Definition: types.hh:168
Bitfield< 3, 0 > immedLo3_0
Definition: types.hh:140
int RegContextParam
Definition: types.hh:234
Bitfield< 2, 0 > fpImm
Definition: types.hh:153
Bitfield< 22 > opcode22
Definition: types.hh:99
Bitfield< 24, 21 > opcode
Definition: types.hh:92
Bitfield< 21, 20 > htopcode5_4
Definition: types.hh:189
Bitfield< 20 > htopcode4
Definition: types.hh:190
Bitfield< 23, 21 > htopcode7_5
Definition: types.hh:186
Bitfield< 25, 20 > htopcode9_4
Definition: types.hh:180
Bitfield< 35 > bigThumb
Definition: types.hh:80
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
uint16_t vmid_t
Definition: types.hh:57
Bitfield< 28, 27 > htopcode12_11
Definition: types.hh:175
Bitfield< 12, 10 > topcode12_10
Definition: types.hh:162
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:390
Bitfield< 23, 0 > immed23_0
Definition: types.hh:146
Bitfield< 7 > opcode7
Definition: types.hh:107
Bitfield< 34 > aarch64
Definition: types.hh:81
Bitfield< 11, 8 > ltopcode11_8
Definition: types.hh:196
Bitfield< 27, 25 > encoding
Definition: types.hh:90
BitUnion64(ExtMachInst) Bitfield< 63
Bitfield< 19, 16 > htrn
Definition: types.hh:192
Bitfield< 24, 22 > htopcode8_6
Definition: types.hh:183
Bitfield< 11, 8 > rotate
Definition: types.hh:134
Bitfield< 11, 7 > shiftSize
Definition: types.hh:116
Bitfield< 15, 12 > opcode15_12
Definition: types.hh:103
Bitfield< 59, 56 > sveLen
Definition: types.hh:67
Bitfield< 7, 4 > ltopcode7_4
Definition: types.hh:198
Bitfield< 7, 6 > ltopcode7_6
Definition: types.hh:197
Bitfield< 11, 8 > topcode11_8
Definition: types.hh:164
Bitfield< 12, 11 > topcode12_11
Definition: types.hh:161
Bitfield< 6, 5 > shift
Definition: types.hh:117
Bitfield< 61 > illegalExecution
Definition: types.hh:62
@ SINGLE_TO_LONG
Definition: types.hh:242
@ DOUBLE_TO_WORD
Definition: types.hh:245
@ SINGLE_TO_DOUBLE
Definition: types.hh:240
@ DOUBLE_TO_LONG
Definition: types.hh:246
@ WORD_TO_SINGLE
Definition: types.hh:253
@ PU_TO_SINGLE
Definition: types.hh:259
@ WORD_TO_DOUBLE
Definition: types.hh:254
@ LONG_TO_PS
Definition: types.hh:251
@ LONG_TO_DOUBLE
Definition: types.hh:249
@ WORD_TO_PS
Definition: types.hh:256
@ LONG_TO_WORD
Definition: types.hh:250
@ LONG_TO_SINGLE
Definition: types.hh:248
@ WORD_TO_LONG
Definition: types.hh:255
@ SINGLE_TO_WORD
Definition: types.hh:241
@ PL_TO_SINGLE
Definition: types.hh:258
@ DOUBLE_TO_SINGLE
Definition: types.hh:244
Bitfield< 19, 16 > opcode19_16
Definition: types.hh:100
Bitfield< 20 > hts
Definition: types.hh:193
constexpr unsigned MaxSveVecLenInBytes
Definition: types.hh:468
BitUnion8(ITSTATE) Bitfield< 7
Bitfield< 20 > loadOp
Definition: types.hh:127
Bitfield< 4 > ltopcode4
Definition: types.hh:199
Bitfield< 24, 20 > mediaOpcode
Definition: types.hh:93
BitUnion32(PackedIntReg) Bitfield< 31
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....

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