gem5  v21.1.0.2
Classes | Namespaces | Enumerations
faults.hh File Reference
#include <cstdint>
#include <string>
#include "arch/riscv/isa.hh"
#include "cpu/null_static_inst.hh"
#include "sim/faults.hh"

Go to the source code of this file.

Classes

class  gem5::RiscvISA::RiscvFault
 
class  gem5::RiscvISA::Reset
 
class  gem5::RiscvISA::InterruptFault
 
class  gem5::RiscvISA::InstFault
 
class  gem5::RiscvISA::UnknownInstFault
 
class  gem5::RiscvISA::IllegalInstFault
 
class  gem5::RiscvISA::UnimplementedFault
 
class  gem5::RiscvISA::IllegalFrmFault
 
class  gem5::RiscvISA::AddressFault
 
class  gem5::RiscvISA::BreakpointFault
 
class  gem5::RiscvISA::SyscallFault
 

Namespaces

 gem5
 Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
 
 gem5::RiscvISA
 

Enumerations

enum  gem5::RiscvISA::FloatException : uint64_t {
  gem5::RiscvISA::FloatInexact = 0x1, gem5::RiscvISA::FloatUnderflow = 0x2, gem5::RiscvISA::FloatOverflow = 0x4, gem5::RiscvISA::FloatDivZero = 0x8,
  gem5::RiscvISA::FloatInvalid = 0x10
}
 
enum  gem5::RiscvISA::ExceptionCode : uint64_t {
  gem5::RiscvISA::INST_ADDR_MISALIGNED = 0, gem5::RiscvISA::INST_ACCESS = 1, gem5::RiscvISA::INST_ILLEGAL = 2, gem5::RiscvISA::BREAKPOINT = 3,
  gem5::RiscvISA::LOAD_ADDR_MISALIGNED = 4, gem5::RiscvISA::LOAD_ACCESS = 5, gem5::RiscvISA::STORE_ADDR_MISALIGNED = 6, gem5::RiscvISA::AMO_ADDR_MISALIGNED = 6,
  gem5::RiscvISA::STORE_ACCESS = 7, gem5::RiscvISA::AMO_ACCESS = 7, gem5::RiscvISA::ECALL_USER = 8, gem5::RiscvISA::ECALL_SUPER = 9,
  gem5::RiscvISA::ECALL_MACHINE = 11, gem5::RiscvISA::INST_PAGE = 12, gem5::RiscvISA::LOAD_PAGE = 13, gem5::RiscvISA::STORE_PAGE = 15,
  gem5::RiscvISA::AMO_PAGE = 15, gem5::RiscvISA::INT_SOFTWARE_USER = 0, gem5::RiscvISA::INT_SOFTWARE_SUPER = 1, gem5::RiscvISA::INT_SOFTWARE_MACHINE = 3,
  gem5::RiscvISA::INT_TIMER_USER = 4, gem5::RiscvISA::INT_TIMER_SUPER = 5, gem5::RiscvISA::INT_TIMER_MACHINE = 7, gem5::RiscvISA::INT_EXT_USER = 8,
  gem5::RiscvISA::INT_EXT_SUPER = 9, gem5::RiscvISA::INT_EXT_MACHINE = 11, gem5::RiscvISA::NumInterruptTypes
}
 

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