gem5  v21.2.1.1
isa.hh
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3  * Copyright (c) 2009 The University of Edinburgh
4  * Copyright (c) 2014 Sven Karlsson
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33 
34 #ifndef __ARCH_RISCV_ISA_HH__
35 #define __ARCH_RISCV_ISA_HH__
36 
37 #include <vector>
38 
39 #include "arch/generic/isa.hh"
40 #include "arch/riscv/pcstate.hh"
41 #include "arch/riscv/types.hh"
42 #include "base/types.hh"
43 
44 namespace gem5
45 {
46 
47 struct RiscvISAParams;
48 class Checkpoint;
49 
50 namespace RiscvISA
51 {
52 
54 {
55  PRV_U = 0,
56  PRV_S = 1,
57  PRV_M = 3
58 };
59 
61 {
62  OFF = 0,
63  INITIAL = 1,
64  CLEAN = 2,
65  DIRTY = 3,
66 };
67 
68 class ISA : public BaseISA
69 {
70  protected:
72 
73  bool hpmCounterEnabled(int counter) const;
74 
75  public:
76  using Params = RiscvISAParams;
77 
78  void clear();
79 
80  PCStateBase *
81  newPCState(Addr new_inst_addr=0) const override
82  {
83  return new PCState(new_inst_addr);
84  }
85 
86  public:
87  RegVal readMiscRegNoEffect(int misc_reg) const;
88  RegVal readMiscReg(int misc_reg);
89  void setMiscRegNoEffect(int misc_reg, RegVal val);
90  void setMiscReg(int misc_reg, RegVal val);
91 
92  RegId flattenRegId(const RegId &regId) const { return regId; }
93  int flattenIntIndex(int reg) const { return reg; }
94  int flattenFloatIndex(int reg) const { return reg; }
95  int flattenVecIndex(int reg) const { return reg; }
96  int flattenVecElemIndex(int reg) const { return reg; }
97  int flattenVecPredIndex(int reg) const { return reg; }
98  int flattenCCIndex(int reg) const { return reg; }
99  int flattenMiscIndex(int reg) const { return reg; }
100 
101  bool inUserMode() const override;
102  void copyRegsFrom(ThreadContext *src) override;
103 
104  void serialize(CheckpointOut &cp) const override;
105  void unserialize(CheckpointIn &cp) override;
106 
107  ISA(const Params &p);
108 
109  void handleLockedRead(const RequestPtr &req) override;
110 
111  bool handleLockedWrite(const RequestPtr &req,
112  Addr cacheBlockMask) override;
113 
114  void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override;
115 
116  void globalClearExclusive() override;
117 };
118 
119 } // namespace RiscvISA
120 } // namespace gem5
121 
122 #endif // __ARCH_RISCV_ISA_HH__
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.cc:208
gem5::RiscvISA::FPUStatus
FPUStatus
Definition: isa.hh:60
gem5::RiscvISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:94
gem5::RiscvISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:214
gem5::RiscvISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:93
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:98
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
std::vector< RegVal >
gem5::RiscvISA::INITIAL
@ INITIAL
Definition: isa.hh:63
gem5::RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:76
gem5::RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:285
pcstate.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:499
gem5::RiscvISA::ISA::newPCState
PCStateBase * newPCState(Addr new_inst_addr=0) const override
Definition: isa.hh:81
gem5::RiscvISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:92
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
types.hh
gem5::RiscvISA::ISA::clear
void clear()
Definition: isa.cc:228
gem5::RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:272
gem5::RiscvISA::CLEAN
@ CLEAN
Definition: isa.hh:64
gem5::RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:71
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::ISA::handleLockedRead
void handleLockedRead(const RequestPtr &req) override
Definition: isa.cc:526
gem5::RiscvISA::ISA::handleLockedSnoop
void handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask) override
Definition: isa.cc:512
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:99
gem5::RiscvISA::ISA
Definition: isa.hh:68
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
isa.hh
types.hh
gem5::RiscvISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:96
gem5::RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:492
gem5::RiscvISA::ISA::globalClearExclusive
void globalClearExclusive() override
Definition: isa.cc:571
gem5::RiscvISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:97
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:372
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:55
gem5::RiscvISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:95
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RiscvISA::ISA::handleLockedWrite
bool handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask) override
Definition: isa.cc:536
gem5::BaseISA
Definition: isa.hh:57
gem5::RiscvISA::OFF
@ OFF
Definition: isa.hh:62
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RiscvISA::DIRTY
@ DIRTY
Definition: isa.hh:65
gem5::RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:249
gem5::RiscvISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:194
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:360

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