gem5  v21.1.0.2
isa.hh
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3  * Copyright (c) 2009 The University of Edinburgh
4  * Copyright (c) 2014 Sven Karlsson
5  * Copyright (c) 2016 RISC-V Foundation
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33 
34 #ifndef __ARCH_RISCV_ISA_HH__
35 #define __ARCH_RISCV_ISA_HH__
36 
37 #include <vector>
38 
39 #include "arch/generic/isa.hh"
40 #include "arch/riscv/types.hh"
41 #include "base/types.hh"
42 
43 namespace gem5
44 {
45 
46 struct RiscvISAParams;
47 class Checkpoint;
48 
49 namespace RiscvISA
50 {
51 
53 {
54  PRV_U = 0,
55  PRV_S = 1,
56  PRV_M = 3
57 };
58 
60 {
61  OFF = 0,
62  INITIAL = 1,
63  CLEAN = 2,
64  DIRTY = 3,
65 };
66 
67 class ISA : public BaseISA
68 {
69  protected:
71 
72  bool hpmCounterEnabled(int counter) const;
73 
74  public:
75  using Params = RiscvISAParams;
76 
77  void clear();
78 
79  public:
80  RegVal readMiscRegNoEffect(int misc_reg) const;
81  RegVal readMiscReg(int misc_reg);
82  void setMiscRegNoEffect(int misc_reg, RegVal val);
83  void setMiscReg(int misc_reg, RegVal val);
84 
85  RegId flattenRegId(const RegId &regId) const { return regId; }
86  int flattenIntIndex(int reg) const { return reg; }
87  int flattenFloatIndex(int reg) const { return reg; }
88  int flattenVecIndex(int reg) const { return reg; }
89  int flattenVecElemIndex(int reg) const { return reg; }
90  int flattenVecPredIndex(int reg) const { return reg; }
91  int flattenCCIndex(int reg) const { return reg; }
92  int flattenMiscIndex(int reg) const { return reg; }
93 
94  bool inUserMode() const override { return true; }
95  void copyRegsFrom(ThreadContext *src) override;
96 
97  void serialize(CheckpointOut &cp) const override;
98  void unserialize(CheckpointIn &cp) override;
99 
100  ISA(const Params &p);
101 };
102 
103 } // namespace RiscvISA
104 } // namespace gem5
105 
106 #endif // __ARCH_RISCV_ISA_HH__
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:55
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:56
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::ISA::inUserMode
bool inUserMode() const override
Definition: isa.hh:94
gem5::RiscvISA::FPUStatus
FPUStatus
Definition: isa.hh:59
gem5::RiscvISA::ISA::flattenFloatIndex
int flattenFloatIndex(int reg) const
Definition: isa.hh:87
gem5::RiscvISA::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:200
gem5::RiscvISA::ISA::flattenIntIndex
int flattenIntIndex(int reg) const
Definition: isa.hh:86
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::RiscvISA::ISA::flattenCCIndex
int flattenCCIndex(int reg) const
Definition: isa.hh:91
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:52
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
std::vector< RegVal >
gem5::RiscvISA::INITIAL
@ INITIAL
Definition: isa.hh:62
gem5::RiscvISA::ISA::Params
RiscvISAParams Params
Definition: isa.hh:75
gem5::RiscvISA::ISA::readMiscReg
RegVal readMiscReg(int misc_reg)
Definition: isa.cc:269
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::RiscvISA::ISA::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: isa.cc:481
gem5::RiscvISA::ISA::flattenRegId
RegId flattenRegId(const RegId &regId) const
Definition: isa.hh:85
types.hh
gem5::RiscvISA::ISA::clear
void clear()
Definition: isa.cc:214
gem5::RiscvISA::ISA::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg) const
Definition: isa.cc:256
gem5::RiscvISA::CLEAN
@ CLEAN
Definition: isa.hh:63
gem5::RiscvISA::ISA::miscRegFile
std::vector< RegVal > miscRegFile
Definition: isa.hh:70
gem5::RiscvISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::RiscvISA::ISA::flattenMiscIndex
int flattenMiscIndex(int reg) const
Definition: isa.hh:92
gem5::RiscvISA::ISA
Definition: isa.hh:67
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
isa.hh
types.hh
gem5::RiscvISA::ISA::flattenVecElemIndex
int flattenVecElemIndex(int reg) const
Definition: isa.hh:89
gem5::RiscvISA::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:474
gem5::RiscvISA::ISA::flattenVecPredIndex
int flattenVecPredIndex(int reg) const
Definition: isa.hh:90
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::RiscvISA::ISA::setMiscReg
void setMiscReg(int misc_reg, RegVal val)
Definition: isa.cc:356
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:54
gem5::RiscvISA::ISA::flattenVecIndex
int flattenVecIndex(int reg) const
Definition: isa.hh:88
gem5::BaseISA
Definition: isa.hh:54
gem5::RiscvISA::OFF
@ OFF
Definition: isa.hh:61
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::DIRTY
@ DIRTY
Definition: isa.hh:64
gem5::RiscvISA::ISA::hpmCounterEnabled
bool hpmCounterEnabled(int counter) const
Definition: isa.cc:233
gem5::RiscvISA::ISA::ISA
ISA(const Params &p)
Definition: isa.cc:185
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::RiscvISA::ISA::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val)
Definition: isa.cc:344

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