gem5  v22.0.0.2
faults.hh
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1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2018 TU Dresden
5  * All rights reserved.
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12  * notice, this list of conditions and the following disclaimer in the
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16  * this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 
31 #ifndef __ARCH_RISCV_FAULTS_HH__
32 #define __ARCH_RISCV_FAULTS_HH__
33 
34 #include <cstdint>
35 #include <string>
36 
37 #include "arch/riscv/isa.hh"
38 #include "cpu/null_static_inst.hh"
39 #include "sim/faults.hh"
40 
41 namespace gem5
42 {
43 
44 class ThreadContext;
45 
46 namespace RiscvISA
47 {
48 
49 enum FloatException : uint64_t
50 {
51  FloatInexact = 0x1,
54  FloatDivZero = 0x8,
55  FloatInvalid = 0x10
56 };
57 
58 /*
59  * In RISC-V, exception and interrupt codes share some values. They can be
60  * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
61  * but not exceptions. The full fault cause can be computed by placing the
62  * exception (or interrupt) code in the least significant bits of the CAUSE
63  * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
64  * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
65  * privileged specification v 1.10. Codes are enumerated in Table 3.6.
66  */
67 enum ExceptionCode : uint64_t
68 {
82  INST_PAGE = 12,
83  LOAD_PAGE = 13,
84  STORE_PAGE = 15,
85  AMO_PAGE = 15,
86 
97 };
98 
99 enum class FaultType
100 {
101  INTERRUPT,
103  OTHERS,
104 };
105 
106 class RiscvFault : public FaultBase
107 {
108  protected:
112 
114  : _name(n), _fault_type(ft), _code(c)
115  {}
116 
117  FaultName name() const override { return _name; }
118  bool isInterrupt() const { return _fault_type == FaultType::INTERRUPT; }
120  {
122  }
123  ExceptionCode exception() const { return _code; }
124  virtual RegVal trap_value() const { return 0; }
125 
126  virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
127  void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
128 };
129 
130 class Reset : public FaultBase
131 {
132  private:
134 
135  public:
136  Reset() : _name("reset") {}
137  FaultName name() const override { return _name; }
138 
139  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
140  nullStaticInstPtr) override;
141 };
142 
144 {
145  public:
147  : RiscvFault("interrupt", FaultType::INTERRUPT, c)
148  {}
149  InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {}
150 };
151 
153 {
154  public:
156  : RiscvFault("non_maskable_interrupt",
158  static_cast<ExceptionCode>(0))
159  {}
160 };
161 
162 class InstFault : public RiscvFault
163 {
164  protected:
166 
167  public:
170  {}
171 
172  RegVal trap_value() const override { return _inst; }
173 };
174 
176 {
177  public:
179  : InstFault("Unknown instruction", inst)
180  {}
181 
182  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
183 };
184 
186 {
187  private:
188  const std::string reason;
189 
190  public:
191  IllegalInstFault(std::string r, const ExtMachInst inst)
192  : InstFault("Illegal instruction", inst),
193  reason(r)
194  {}
195 
196  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
197 };
198 
200 {
201  private:
202  const std::string instName;
203 
204  public:
205  UnimplementedFault(std::string name, const ExtMachInst inst)
206  : InstFault("Unimplemented instruction", inst),
207  instName(name)
208  {}
209 
210  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
211 };
212 
214 {
215  private:
216  const uint8_t frm;
217 
218  public:
219  IllegalFrmFault(uint8_t r, const ExtMachInst inst)
220  : InstFault("Illegal floating-point rounding mode", inst),
221  frm(r)
222  {}
223 
224  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
225 };
226 
227 class AddressFault : public RiscvFault
228 {
229  private:
230  const Addr _addr;
231 
232  public:
234  : RiscvFault("Address", FaultType::OTHERS, code), _addr(addr)
235  {}
236 
237  RegVal trap_value() const override { return _addr; }
238 };
239 
241 {
242  private:
244 
245  public:
247  : RiscvFault("Breakpoint", FaultType::OTHERS, BREAKPOINT),
248  pcState(pc.as<PCState>())
249  {}
250 
251  RegVal trap_value() const override { return pcState.pc(); }
252  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
253 };
254 
255 class SyscallFault : public RiscvFault
256 {
257  public:
259  : RiscvFault("System call", FaultType::OTHERS, ECALL_USER)
260  {
261  switch (prv) {
262  case PRV_U:
263  _code = ECALL_USER;
264  break;
265  case PRV_S:
266  _code = ECALL_SUPER;
267  break;
268  case PRV_M:
270  break;
271  default:
272  panic("Unknown privilege mode %d.", prv);
273  break;
274  }
275  }
276 
277  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
278 };
279 
280 } // namespace RiscvISA
281 } // namespace gem5
282 
283 #endif // __ARCH_RISCV_FAULTS_HH__
gem5::GenericISA::PCStateWithNext::pc
Addr pc() const
Definition: pcstate.hh:263
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:56
gem5::RiscvISA::INT_EXT_MACHINE
@ INT_EXT_MACHINE
Definition: faults.hh:95
gem5::RiscvISA::FaultType::INTERRUPT
@ INTERRUPT
gem5::RiscvISA::UnimplementedFault::instName
const std::string instName
Definition: faults.hh:202
gem5::RiscvISA::INT_TIMER_USER
@ INT_TIMER_USER
Definition: faults.hh:90
gem5::RiscvISA::INT_TIMER_SUPER
@ INT_TIMER_SUPER
Definition: faults.hh:91
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:57
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::FloatDivZero
@ FloatDivZero
Definition: faults.hh:54
gem5::RiscvISA::LOAD_PAGE
@ LOAD_PAGE
Definition: faults.hh:83
gem5::RiscvISA::RiscvFault::_fault_type
const FaultType _fault_type
Definition: faults.hh:110
gem5::RiscvISA::INT_EXT_USER
@ INT_EXT_USER
Definition: faults.hh:93
gem5::RiscvISA::RiscvFault::_name
const FaultName _name
Definition: faults.hh:109
gem5::RiscvISA::RiscvFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:58
gem5::RiscvISA::BreakpointFault::BreakpointFault
BreakpointFault(const PCStateBase &pc)
Definition: faults.hh:246
gem5::RiscvISA::AddressFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:237
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:53
gem5::RiscvISA::BREAKPOINT
@ BREAKPOINT
Definition: faults.hh:72
gem5::RiscvISA::IllegalFrmFault::frm
const uint8_t frm
Definition: faults.hh:216
gem5::RiscvISA::INT_SOFTWARE_USER
@ INT_SOFTWARE_USER
Definition: faults.hh:87
gem5::RiscvISA::NonMaskableInterruptFault
Definition: faults.hh:152
gem5::RiscvISA::FloatInexact
@ FloatInexact
Definition: faults.hh:51
gem5::RiscvISA::BreakpointFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:251
gem5::RiscvISA::RiscvFault::isInterrupt
bool isInterrupt() const
Definition: faults.hh:118
gem5::RiscvISA::AddressFault::AddressFault
AddressFault(const Addr addr, ExceptionCode code)
Definition: faults.hh:233
faults.hh
gem5::RiscvISA::c
Bitfield< 5, 3 > c
Definition: pra_constants.hh:59
gem5::RiscvISA::AddressFault::_addr
const Addr _addr
Definition: faults.hh:230
isa.hh
gem5::ArmISA::as
Bitfield< 36 > as
Definition: misc_types.hh:508
gem5::RefCountingPtr< StaticInst >
gem5::RiscvISA::Reset
Definition: faults.hh:130
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::RiscvISA::INT_EXT_SUPER
@ INT_EXT_SUPER
Definition: faults.hh:94
gem5::RiscvISA::STORE_ADDR_MISALIGNED
@ STORE_ADDR_MISALIGNED
Definition: faults.hh:75
gem5::RiscvISA::NonMaskableInterruptFault::NonMaskableInterruptFault
NonMaskableInterruptFault()
Definition: faults.hh:155
gem5::RiscvISA::IllegalInstFault::IllegalInstFault
IllegalInstFault(std::string r, const ExtMachInst inst)
Definition: faults.hh:191
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::RiscvISA::LOAD_ACCESS
@ LOAD_ACCESS
Definition: faults.hh:74
gem5::RiscvISA::FloatUnderflow
@ FloatUnderflow
Definition: faults.hh:52
gem5::RiscvISA::LOAD_ADDR_MISALIGNED
@ LOAD_ADDR_MISALIGNED
Definition: faults.hh:73
gem5::RiscvISA::InstFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:172
gem5::RiscvISA::INT_TIMER_MACHINE
@ INT_TIMER_MACHINE
Definition: faults.hh:92
gem5::RiscvISA::UnimplementedFault::UnimplementedFault
UnimplementedFault(std::string name, const ExtMachInst inst)
Definition: faults.hh:205
gem5::RiscvISA::RiscvFault
Definition: faults.hh:106
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::Reset::Reset
Reset()
Definition: faults.hh:136
gem5::RiscvISA::ECALL_MACHINE
@ ECALL_MACHINE
Definition: faults.hh:81
gem5::RiscvISA::INST_ACCESS
@ INST_ACCESS
Definition: faults.hh:70
gem5::RiscvISA::RiscvFault::name
FaultName name() const override
Definition: faults.hh:117
gem5::RiscvISA::IllegalInstFault::reason
const std::string reason
Definition: faults.hh:188
gem5::RiscvISA::INT_SOFTWARE_SUPER
@ INT_SOFTWARE_SUPER
Definition: faults.hh:88
gem5::RiscvISA::INST_PAGE
@ INST_PAGE
Definition: faults.hh:82
gem5::RiscvISA::RiscvFault::RiscvFault
RiscvFault(FaultName n, FaultType ft, ExceptionCode c)
Definition: faults.hh:113
gem5::RiscvISA::FaultType
FaultType
Definition: faults.hh:99
gem5::RiscvISA::IllegalFrmFault
Definition: faults.hh:213
gem5::RiscvISA::STORE_ACCESS
@ STORE_ACCESS
Definition: faults.hh:77
gem5::RiscvISA::RiscvFault::_code
ExceptionCode _code
Definition: faults.hh:111
gem5::RiscvISA::NumInterruptTypes
@ NumInterruptTypes
Definition: faults.hh:96
gem5::RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:75
gem5::RiscvISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:169
gem5::RiscvISA::InstFault
Definition: faults.hh:162
gem5::RiscvISA::ExceptionCode
ExceptionCode
Definition: faults.hh:67
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::RiscvISA::BreakpointFault::pcState
const PCState pcState
Definition: faults.hh:243
gem5::RiscvISA::ECALL_SUPER
@ ECALL_SUPER
Definition: faults.hh:80
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::AMO_ADDR_MISALIGNED
@ AMO_ADDR_MISALIGNED
Definition: faults.hh:76
gem5::RiscvISA::INT_SOFTWARE_MACHINE
@ INT_SOFTWARE_MACHINE
Definition: faults.hh:89
gem5::RiscvISA::UnknownInstFault::UnknownInstFault
UnknownInstFault(const ExtMachInst inst)
Definition: faults.hh:178
gem5::RiscvISA::InstFault::InstFault
InstFault(FaultName n, const ExtMachInst inst)
Definition: faults.hh:168
gem5::RiscvISA::Reset::_name
const FaultName _name
Definition: faults.hh:133
gem5::RiscvISA::IllegalInstFault
Definition: faults.hh:185
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::RiscvISA::UnknownInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:185
gem5::RiscvISA::AMO_PAGE
@ AMO_PAGE
Definition: faults.hh:85
gem5::RiscvISA::InterruptFault::InterruptFault
InterruptFault(int c)
Definition: faults.hh:149
gem5::RiscvISA::ECALL_USER
@ ECALL_USER
Definition: faults.hh:79
gem5::RiscvISA::UnknownInstFault
Definition: faults.hh:175
gem5::RiscvISA::FloatInvalid
@ FloatInvalid
Definition: faults.hh:55
gem5::RiscvISA::BreakpointFault
Definition: faults.hh:240
gem5::RiscvISA::IllegalFrmFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:207
gem5::RiscvISA::STORE_PAGE
@ STORE_PAGE
Definition: faults.hh:84
gem5::RiscvISA::FaultType::NON_MASKABLE_INTERRUPT
@ NON_MASKABLE_INTERRUPT
gem5::RiscvISA::FloatOverflow
@ FloatOverflow
Definition: faults.hh:53
gem5::FaultBase
Definition: translation_gen.test.cc:49
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:456
gem5::RiscvISA::SyscallFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:220
gem5::RiscvISA::RiscvFault::exception
ExceptionCode exception() const
Definition: faults.hh:123
gem5::RiscvISA::AddressFault
Definition: faults.hh:227
gem5::RiscvISA::FloatException
FloatException
Definition: faults.hh:49
gem5::RiscvISA::BreakpointFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:214
gem5::RiscvISA::UnimplementedFault
Definition: faults.hh:199
gem5::RiscvISA::IllegalInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:193
gem5::RiscvISA::InterruptFault
Definition: faults.hh:143
gem5::RiscvISA::SyscallFault::SyscallFault
SyscallFault(PrivilegeMode prv)
Definition: faults.hh:258
gem5::RiscvISA::InterruptFault::InterruptFault
InterruptFault(ExceptionCode c)
Definition: faults.hh:146
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:55
gem5::RiscvISA::RiscvFault::trap_value
virtual RegVal trap_value() const
Definition: faults.hh:124
gem5::RiscvISA::INST_ILLEGAL
@ INST_ILLEGAL
Definition: faults.hh:71
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::RiscvISA::Reset::name
FaultName name() const override
Definition: faults.hh:137
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RiscvISA::SyscallFault
Definition: faults.hh:255
gem5::RiscvISA::UnimplementedFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:201
gem5::RiscvISA::IllegalFrmFault::IllegalFrmFault
IllegalFrmFault(uint8_t r, const ExtMachInst inst)
Definition: faults.hh:219
gem5::RiscvISA::FaultType::OTHERS
@ OTHERS
gem5::RiscvISA::RiscvFault::invokeSE
virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:52
gem5::RiscvISA::RiscvFault::isNonMaskableInterrupt
bool isNonMaskableInterrupt() const
Definition: faults.hh:119
gem5::RiscvISA::AMO_ACCESS
@ AMO_ACCESS
Definition: faults.hh:78
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::RiscvISA::InstFault::_inst
const ExtMachInst _inst
Definition: faults.hh:165
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RiscvISA::INST_ADDR_MISALIGNED
@ INST_ADDR_MISALIGNED
Definition: faults.hh:69

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