gem5  v21.1.0.2
faults.hh
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1 /*
2  * Copyright (c) 2016 RISC-V Foundation
3  * Copyright (c) 2016 The University of Virginia
4  * Copyright (c) 2018 TU Dresden
5  * All rights reserved.
6  *
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10  * notice, this list of conditions and the following disclaimer;
11  * redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
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14  * neither the name of the copyright holders nor the names of its
15  * contributors may be used to endorse or promote products derived from
16  * this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29  */
30 
31 #ifndef __ARCH_RISCV_FAULTS_HH__
32 #define __ARCH_RISCV_FAULTS_HH__
33 
34 #include <cstdint>
35 #include <string>
36 
37 #include "arch/riscv/isa.hh"
38 #include "cpu/null_static_inst.hh"
39 #include "sim/faults.hh"
40 
41 namespace gem5
42 {
43 
44 class ThreadContext;
45 
46 namespace RiscvISA
47 {
48 
49 enum FloatException : uint64_t
50 {
51  FloatInexact = 0x1,
54  FloatDivZero = 0x8,
55  FloatInvalid = 0x10
56 };
57 
58 /*
59  * In RISC-V, exception and interrupt codes share some values. They can be
60  * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
61  * but not exceptions. The full fault cause can be computed by placing the
62  * exception (or interrupt) code in the least significant bits of the CAUSE
63  * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
64  * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
65  * privileged specification v 1.10. Codes are enumerated in Table 3.6.
66  */
67 enum ExceptionCode : uint64_t
68 {
82  INST_PAGE = 12,
83  LOAD_PAGE = 13,
84  STORE_PAGE = 15,
85  AMO_PAGE = 15,
86 
97 };
98 
99 class RiscvFault : public FaultBase
100 {
101  protected:
103  const bool _interrupt;
105 
107  : _name(n), _interrupt(i), _code(c)
108  {}
109 
110  FaultName name() const override { return _name; }
111  bool isInterrupt() const { return _interrupt; }
112  ExceptionCode exception() const { return _code; }
113  virtual RegVal trap_value() const { return 0; }
114 
115  virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
116  void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
117 };
118 
119 class Reset : public FaultBase
120 {
121  private:
123 
124  public:
125  Reset() : _name("reset") {}
126  FaultName name() const override { return _name; }
127 
128  void invoke(ThreadContext *tc, const StaticInstPtr &inst =
129  nullStaticInstPtr) override;
130 };
131 
133 {
134  public:
135  InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {}
136  InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {}
137 };
138 
139 class InstFault : public RiscvFault
140 {
141  protected:
143 
144  public:
146  : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
147  {}
148 
149  RegVal trap_value() const override { return _inst; }
150 };
151 
153 {
154  public:
156  : InstFault("Unknown instruction", inst)
157  {}
158 
159  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
160 };
161 
163 {
164  private:
165  const std::string reason;
166 
167  public:
168  IllegalInstFault(std::string r, const ExtMachInst inst)
169  : InstFault("Illegal instruction", inst)
170  {}
171 
172  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
173 };
174 
176 {
177  private:
178  const std::string instName;
179 
180  public:
181  UnimplementedFault(std::string name, const ExtMachInst inst)
182  : InstFault("Unimplemented instruction", inst),
183  instName(name)
184  {}
185 
186  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
187 };
188 
190 {
191  private:
192  const uint8_t frm;
193 
194  public:
195  IllegalFrmFault(uint8_t r, const ExtMachInst inst)
196  : InstFault("Illegal floating-point rounding mode", inst),
197  frm(r)
198  {}
199 
200  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
201 };
202 
203 class AddressFault : public RiscvFault
204 {
205  private:
206  const Addr _addr;
207 
208  public:
210  : RiscvFault("Address", false, code), _addr(addr)
211  {}
212 
213  RegVal trap_value() const override { return _addr; }
214 };
215 
217 {
218  private:
220 
221  public:
223  : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
224  {}
225 
226  RegVal trap_value() const override { return pcState.pc(); }
227  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
228 };
229 
230 class SyscallFault : public RiscvFault
231 {
232  public:
234  : RiscvFault("System call", false, ECALL_USER)
235  {
236  switch (prv) {
237  case PRV_U:
238  _code = ECALL_USER;
239  break;
240  case PRV_S:
241  _code = ECALL_SUPER;
242  break;
243  case PRV_M:
245  break;
246  default:
247  panic("Unknown privilege mode %d.", prv);
248  break;
249  }
250  }
251 
252  void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
253 };
254 
255 } // namespace RiscvISA
256 } // namespace gem5
257 
258 #endif // __ARCH_RISCV_FAULTS_HH__
gem5::RiscvISA::PRV_S
@ PRV_S
Definition: isa.hh:55
gem5::RiscvISA::INT_EXT_MACHINE
@ INT_EXT_MACHINE
Definition: faults.hh:95
gem5::RiscvISA::UnimplementedFault::instName
const std::string instName
Definition: faults.hh:178
gem5::RiscvISA::INT_TIMER_USER
@ INT_TIMER_USER
Definition: faults.hh:90
gem5::RiscvISA::INT_TIMER_SUPER
@ INT_TIMER_SUPER
Definition: faults.hh:91
gem5::RiscvISA::PRV_M
@ PRV_M
Definition: isa.hh:56
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RiscvISA::FloatDivZero
@ FloatDivZero
Definition: faults.hh:54
gem5::RiscvISA::RiscvFault::RiscvFault
RiscvFault(FaultName n, bool i, ExceptionCode c)
Definition: faults.hh:106
gem5::RiscvISA::LOAD_PAGE
@ LOAD_PAGE
Definition: faults.hh:83
gem5::RiscvISA::INT_EXT_USER
@ INT_EXT_USER
Definition: faults.hh:93
gem5::RiscvISA::RiscvFault::_name
const FaultName _name
Definition: faults.hh:102
gem5::RiscvISA::RiscvFault::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:58
gem5::RiscvISA::RiscvFault::_interrupt
const bool _interrupt
Definition: faults.hh:103
gem5::RiscvISA::AddressFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:213
gem5::RiscvISA::PrivilegeMode
PrivilegeMode
Definition: isa.hh:52
gem5::RiscvISA::BREAKPOINT
@ BREAKPOINT
Definition: faults.hh:72
gem5::RiscvISA::IllegalFrmFault::frm
const uint8_t frm
Definition: faults.hh:192
gem5::RiscvISA::INT_SOFTWARE_USER
@ INT_SOFTWARE_USER
Definition: faults.hh:87
gem5::RiscvISA::FloatInexact
@ FloatInexact
Definition: faults.hh:51
gem5::RiscvISA::BreakpointFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:226
gem5::RiscvISA::RiscvFault::isInterrupt
bool isInterrupt() const
Definition: faults.hh:111
gem5::RiscvISA::AddressFault::AddressFault
AddressFault(const Addr addr, ExceptionCode code)
Definition: faults.hh:209
faults.hh
gem5::RiscvISA::c
Bitfield< 5, 3 > c
Definition: pra_constants.hh:59
gem5::RiscvISA::AddressFault::_addr
const Addr _addr
Definition: faults.hh:206
isa.hh
gem5::RefCountingPtr< StaticInst >
gem5::RiscvISA::Reset
Definition: faults.hh:119
gem5::RiscvISA::PCState
Definition: pcstate.hh:53
gem5::RiscvISA::INT_EXT_SUPER
@ INT_EXT_SUPER
Definition: faults.hh:94
gem5::RiscvISA::STORE_ADDR_MISALIGNED
@ STORE_ADDR_MISALIGNED
Definition: faults.hh:75
gem5::RiscvISA::IllegalInstFault::IllegalInstFault
IllegalInstFault(std::string r, const ExtMachInst inst)
Definition: faults.hh:168
gem5::nullStaticInstPtr
const StaticInstPtr nullStaticInstPtr
Statically allocated null StaticInstPtr.
Definition: null_static_inst.cc:36
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::RiscvISA::LOAD_ACCESS
@ LOAD_ACCESS
Definition: faults.hh:74
gem5::RiscvISA::FloatUnderflow
@ FloatUnderflow
Definition: faults.hh:52
gem5::RiscvISA::LOAD_ADDR_MISALIGNED
@ LOAD_ADDR_MISALIGNED
Definition: faults.hh:73
gem5::RiscvISA::InstFault::trap_value
RegVal trap_value() const override
Definition: faults.hh:149
gem5::RiscvISA::INT_TIMER_MACHINE
@ INT_TIMER_MACHINE
Definition: faults.hh:92
gem5::RiscvISA::UnimplementedFault::UnimplementedFault
UnimplementedFault(std::string name, const ExtMachInst inst)
Definition: faults.hh:181
gem5::RiscvISA::RiscvFault
Definition: faults.hh:99
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::RiscvISA::Reset::Reset
Reset()
Definition: faults.hh:125
gem5::RiscvISA::ECALL_MACHINE
@ ECALL_MACHINE
Definition: faults.hh:81
gem5::RiscvISA::INST_ACCESS
@ INST_ACCESS
Definition: faults.hh:70
gem5::RiscvISA::RiscvFault::name
FaultName name() const override
Definition: faults.hh:110
gem5::RiscvISA::IllegalInstFault::reason
const std::string reason
Definition: faults.hh:165
gem5::RiscvISA::INT_SOFTWARE_SUPER
@ INT_SOFTWARE_SUPER
Definition: faults.hh:88
gem5::RiscvISA::INST_PAGE
@ INST_PAGE
Definition: faults.hh:82
gem5::RiscvISA::IllegalFrmFault
Definition: faults.hh:189
gem5::RiscvISA::STORE_ACCESS
@ STORE_ACCESS
Definition: faults.hh:77
gem5::RiscvISA::RiscvFault::_code
ExceptionCode _code
Definition: faults.hh:104
gem5::RiscvISA::NumInterruptTypes
@ NumInterruptTypes
Definition: faults.hh:96
gem5::RiscvISA::r
Bitfield< 1 > r
Definition: pagetable.hh:75
gem5::RiscvISA::Reset::invoke
void invoke(ThreadContext *tc, const StaticInstPtr &inst=nullStaticInstPtr) override
Definition: faults.cc:152
gem5::RiscvISA::InstFault
Definition: faults.hh:139
gem5::RiscvISA::ExceptionCode
ExceptionCode
Definition: faults.hh:67
gem5::RiscvISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:54
gem5::RiscvISA::BreakpointFault::pcState
const PCState pcState
Definition: faults.hh:219
gem5::RiscvISA::ECALL_SUPER
@ ECALL_SUPER
Definition: faults.hh:80
null_static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::RiscvISA::AMO_ADDR_MISALIGNED
@ AMO_ADDR_MISALIGNED
Definition: faults.hh:76
gem5::RiscvISA::INT_SOFTWARE_MACHINE
@ INT_SOFTWARE_MACHINE
Definition: faults.hh:89
gem5::RiscvISA::UnknownInstFault::UnknownInstFault
UnknownInstFault(const ExtMachInst inst)
Definition: faults.hh:155
gem5::RiscvISA::InstFault::InstFault
InstFault(FaultName n, const ExtMachInst inst)
Definition: faults.hh:145
gem5::RiscvISA::Reset::_name
const FaultName _name
Definition: faults.hh:122
gem5::RiscvISA::IllegalInstFault
Definition: faults.hh:162
gem5::FaultName
const typedef char * FaultName
Definition: faults.hh:53
gem5::RiscvISA::UnknownInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:168
gem5::RiscvISA::AMO_PAGE
@ AMO_PAGE
Definition: faults.hh:85
gem5::RiscvISA::InterruptFault::InterruptFault
InterruptFault(int c)
Definition: faults.hh:136
gem5::RiscvISA::ECALL_USER
@ ECALL_USER
Definition: faults.hh:79
gem5::RiscvISA::UnknownInstFault
Definition: faults.hh:152
gem5::RiscvISA::FloatInvalid
@ FloatInvalid
Definition: faults.hh:55
gem5::RiscvISA::BreakpointFault
Definition: faults.hh:216
gem5::RiscvISA::IllegalFrmFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:192
gem5::RiscvISA::STORE_PAGE
@ STORE_PAGE
Definition: faults.hh:84
gem5::RiscvISA::FloatOverflow
@ FloatOverflow
Definition: faults.hh:53
gem5::FaultBase
Definition: faults.hh:58
gem5::ArmISA::n
Bitfield< 31 > n
Definition: misc_types.hh:455
gem5::RiscvISA::SyscallFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:205
gem5::RiscvISA::RiscvFault::exception
ExceptionCode exception() const
Definition: faults.hh:112
gem5::RiscvISA::AddressFault
Definition: faults.hh:203
gem5::RiscvISA::FloatException
FloatException
Definition: faults.hh:49
gem5::RiscvISA::BreakpointFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:199
gem5::RiscvISA::UnimplementedFault
Definition: faults.hh:175
gem5::RiscvISA::IllegalInstFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:176
gem5::RiscvISA::InterruptFault
Definition: faults.hh:132
gem5::RiscvISA::SyscallFault::SyscallFault
SyscallFault(PrivilegeMode prv)
Definition: faults.hh:233
gem5::RiscvISA::InterruptFault::InterruptFault
InterruptFault(ExceptionCode c)
Definition: faults.hh:135
gem5::RiscvISA::PRV_U
@ PRV_U
Definition: isa.hh:54
gem5::RiscvISA::RiscvFault::trap_value
virtual RegVal trap_value() const
Definition: faults.hh:113
gem5::RiscvISA::INST_ILLEGAL
@ INST_ILLEGAL
Definition: faults.hh:71
gem5::RiscvISA::BreakpointFault::BreakpointFault
BreakpointFault(const PCState &pc)
Definition: faults.hh:222
gem5::RiscvISA::Reset::name
FaultName name() const override
Definition: faults.hh:126
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RiscvISA::SyscallFault
Definition: faults.hh:230
gem5::RiscvISA::UnimplementedFault::invokeSE
void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override
Definition: faults.cc:184
gem5::RiscvISA::IllegalFrmFault::IllegalFrmFault
IllegalFrmFault(uint8_t r, const ExtMachInst inst)
Definition: faults.hh:195
gem5::RiscvISA::i
Bitfield< 2 > i
Definition: pra_constants.hh:279
gem5::GenericISA::SimplePCState::pc
Addr pc() const
Definition: types.hh:151
gem5::RiscvISA::RiscvFault::invokeSE
virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
Definition: faults.cc:52
gem5::RiscvISA::AMO_ACCESS
@ AMO_ACCESS
Definition: faults.hh:78
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::RiscvISA::InstFault::_inst
const ExtMachInst _inst
Definition: faults.hh:142
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::RiscvISA::INST_ADDR_MISALIGNED
@ INST_ADDR_MISALIGNED
Definition: faults.hh:69

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