#include "cpu/reg_class.hh"
#include "debug/CCRegs.hh"
Go to the source code of this file.
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enum | : RegIndex {
gem5::ArmISA::cc_reg::_NzIdx
, gem5::ArmISA::cc_reg::_CIdx
, gem5::ArmISA::cc_reg::_VIdx
, gem5::ArmISA::cc_reg::_GeIdx
,
gem5::ArmISA::cc_reg::_FpIdx
, gem5::ArmISA::cc_reg::_ZeroIdx
, gem5::ArmISA::cc_reg::NumRegs
} |
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enum | gem5::ArmISA::ConditionCode {
gem5::ArmISA::COND_EQ = 0
, gem5::ArmISA::COND_NE
, gem5::ArmISA::COND_CS
, gem5::ArmISA::COND_CC
,
gem5::ArmISA::COND_MI
, gem5::ArmISA::COND_PL
, gem5::ArmISA::COND_VS
, gem5::ArmISA::COND_VC
,
gem5::ArmISA::COND_HI
, gem5::ArmISA::COND_LS
, gem5::ArmISA::COND_GE
, gem5::ArmISA::COND_LT
,
gem5::ArmISA::COND_GT
, gem5::ArmISA::COND_LE
, gem5::ArmISA::COND_AL
, gem5::ArmISA::COND_UC
} |
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Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0