gem5::ArmISA::cc_reg Namespace Reference

Enumerations
enum	: RegIndex {   _NzIdx , _CIdx , _VIdx , _GeIdx ,   _FpIdx , _ZeroIdx , NumRegs }

Variables
const char *const	RegName [NumRegs]
constexpr RegId	Nz = ccRegClass[_NzIdx]
constexpr RegId	C = ccRegClass[_CIdx]
constexpr RegId	V = ccRegClass[_VIdx]
constexpr RegId	Ge = ccRegClass[_GeIdx]
constexpr RegId	Fp = ccRegClass[_FpIdx]
constexpr RegId	Zero = ccRegClass[_ZeroIdx]

Enumeration Type Documentation

anonymous enum

anonymous enum : RegIndex

Enumerator
_NzIdx
_CIdx
_VIdx
_GeIdx
_FpIdx
_ZeroIdx
NumRegs

Definition at line 53 of file cc.hh.

Variable Documentation

C

RegId gem5::ArmISA::cc_reg::C = ccRegClass[_CIdx]

Definition at line 95 of file cc.hh.

Referenced by gem5::ArmISA::ArmFault::invoke64(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().

Fp

RegId gem5::ArmISA::cc_reg::Fp = ccRegClass[_FpIdx]

Definition at line 98 of file cc.hh.

Referenced by gem5::fastmodel::CortexA76TC::readCCRegFlat(), gem5::fastmodel::CortexR52TC::readCCRegFlat(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), and gem5::trace::ArmNativeTrace::ThreadState::update().

Ge

RegId gem5::ArmISA::cc_reg::Ge = ccRegClass[_GeIdx]

Definition at line 97 of file cc.hh.

Referenced by gem5::ArmISA::ArmFault::invoke64(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().

Nz

RegId gem5::ArmISA::cc_reg::Nz = ccRegClass[_NzIdx]

inlineconstexpr

Definition at line 94 of file cc.hh.

Referenced by gem5::ArmISA::ArmFault::invoke64(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), gem5::fastmodel::CortexR52TC::readCCRegFlat(), gem5::ArmISA::ISA::readMiscReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), gem5::ArmISA::ISA::setMiscReg(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().

RegName

const char* const gem5::ArmISA::cc_reg::RegName[NumRegs]

Initial value:

= {
    "nz",
    "c",
    "v",
    "ge",
    "fp",
    "zero"
}

Definition at line 64 of file cc.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printCCReg(), gem5::ArmISA::CCRegClassOps::regName(), and gem5::trace::TarmacTracerRecord::TraceRegEntry::updateCC().

V

RegId gem5::ArmISA::cc_reg::V = ccRegClass[_VIdx]

Definition at line 96 of file cc.hh.

Referenced by gem5::ArmISA::ArmFault::invoke64(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), and gem5::ArmV8KvmCPU::updateThreadContext().

Zero

RegId gem5::ArmISA::cc_reg::Zero = ccRegClass[_ZeroIdx]

Definition at line 99 of file cc.hh.