gem5  v22.0.0.2
reg_class.hh
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40 
41 #ifndef __CPU__REG_CLASS_HH__
42 #define __CPU__REG_CLASS_HH__
43 
44 #include <cstddef>
45 #include <string>
46 
47 #include "base/cprintf.hh"
48 #include "base/debug.hh"
49 #include "base/intmath.hh"
50 #include "base/types.hh"
51 
52 namespace gem5
53 {
54 
57 {
60 
68 };
69 
70 class RegId;
71 
73 {
74  public:
76  virtual std::string regName(const RegId &id) const;
78  virtual std::string valString(const void *val, size_t size) const;
79 };
80 
81 class RegClass
82 {
83  private:
84  size_t _numRegs;
85  size_t _regBytes;
86  // This is how much to shift an index by to get an offset of a register in
87  // a register file from the register index, which would otherwise need to
88  // be calculated with a multiply.
89  size_t _regShift;
90 
91  static inline RegClassOps defaultOps;
94 
95  public:
96  constexpr RegClass(size_t num_regs, const debug::Flag &debug_flag,
97  size_t reg_bytes=sizeof(RegVal)) :
98  _numRegs(num_regs), _regBytes(reg_bytes),
99  _regShift(ceilLog2(reg_bytes)), debugFlag(debug_flag)
100  {}
101  constexpr RegClass(size_t num_regs, RegClassOps &new_ops,
102  const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal)) :
103  RegClass(num_regs, debug_flag, reg_bytes)
104  {
105  _ops = &new_ops;
106  }
107 
108  constexpr size_t numRegs() const { return _numRegs; }
109  constexpr size_t regBytes() const { return _regBytes; }
110  constexpr size_t regShift() const { return _regShift; }
111  constexpr const debug::Flag &debug() const { return debugFlag; }
112 
113  std::string regName(const RegId &id) const { return _ops->regName(id); }
114  std::string
115  valString(const void *val) const
116  {
117  return _ops->valString(val, regBytes());
118  }
119 };
120 
126 class RegId
127 {
128  protected:
129  static const char* regClassStrings[];
133 
134  friend struct std::hash<RegId>;
135 
136  public:
137  constexpr RegId() : RegId(InvalidRegClass, 0) {}
138 
139  constexpr RegId(RegClassType reg_class, RegIndex reg_idx)
140  : regClass(reg_class), regIdx(reg_idx), numPinnedWrites(0)
141  {}
142 
143  constexpr operator RegIndex() const
144  {
145  return index();
146  }
147 
148  constexpr bool
149  operator==(const RegId& that) const
150  {
151  return regClass == that.classValue() && regIdx == that.index();
152  }
153 
154  constexpr bool
155  operator!=(const RegId& that) const
156  {
157  return !(*this==that);
158  }
159 
163  constexpr bool
164  operator<(const RegId& that) const
165  {
166  return regClass < that.classValue() ||
167  (regClass == that.classValue() && (regIdx < that.index()));
168  }
169 
173  constexpr bool
174  isRenameable() const
175  {
177  }
178 
180  constexpr bool
181  is(RegClassType reg_class) const
182  {
183  return regClass == reg_class;
184  }
185 
188  constexpr RegIndex index() const { return regIdx; }
189 
191  constexpr RegClassType classValue() const { return regClass; }
193  constexpr const char*
194  className() const
195  {
196  return regClassStrings[regClass];
197  }
198 
199  int getNumPinnedWrites() const { return numPinnedWrites; }
200  void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
201 
202  friend std::ostream&
203  operator<<(std::ostream& os, const RegId& rid)
204  {
205  return os << rid.className() << "{" << rid.index() << "}";
206  }
207 };
208 
209 template <typename ValueType>
211 {
212  public:
213  std::string
214  valString(const void *val, size_t size) const override
215  {
216  assert(size == sizeof(ValueType));
217  return csprintf("%s", *(const ValueType *)val);
218  }
219 };
220 
221 template <typename ValueType>
222 class VecElemRegClassOps : public TypedRegClassOps<ValueType>
223 {
224  protected:
225  size_t elemsPerVec;
226 
227  public:
228  explicit VecElemRegClassOps(size_t elems_per_vec) :
229  elemsPerVec(elems_per_vec)
230  {}
231 
232  std::string
233  regName(const RegId &id) const override
234  {
235  RegIndex reg_idx = id.index() / elemsPerVec;
236  RegIndex elem_idx = id.index() % elemsPerVec;
237  return csprintf("v%d[%d]", reg_idx, elem_idx);
238  }
239 };
240 
245 class PhysRegId : private RegId
246 {
247  private:
250  bool pinned;
251 
252  public:
253  explicit PhysRegId() : RegId(InvalidRegClass, -1), flatIdx(-1),
255  {}
256 
258  explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
259  RegIndex _flatIdx)
260  : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
262  {}
263 
266  using RegId::index;
267  using RegId::classValue;
268  using RegId::className;
269  using RegId::is;
276  bool
277  operator<(const PhysRegId& that) const
278  {
279  return RegId::operator<(that);
280  }
281 
282  bool
283  operator==(const PhysRegId& that) const
284  {
285  return RegId::operator==(that);
286  }
287 
288  bool
289  operator!=(const PhysRegId& that) const
290  {
291  return RegId::operator!=(that);
292  }
299  bool isFixedMapping() const { return !isRenameable(); }
300 
302  const RegIndex& flatIndex() const { return flatIdx; }
303 
304  int getNumPinnedWrites() const { return numPinnedWrites; }
305 
306  void
307  setNumPinnedWrites(int numWrites)
308  {
309  // An instruction with a pinned destination reg can get
310  // squashed. The numPinnedWrites counter may be zero when
311  // the squash happens but we need to know if the dest reg
312  // was pinned originally in order to reset counters properly
313  // for a possible re-rename using the same physical reg (which
314  // may be required in case of a mem access order violation).
315  pinned = (numWrites != 0);
316  numPinnedWrites = numWrites;
317  }
318 
321 
322  bool isPinned() const { return pinned; }
323 
324  int
326  {
328  }
329 
330  void
332  {
333  numPinnedWritesToComplete = numWrites;
334  }
335 
338 };
339 
341 
342 } // namespace gem5
343 
344 namespace std
345 {
346 template<>
347 struct hash<gem5::RegId>
348 {
349  size_t
350  operator()(const gem5::RegId& reg_id) const
351  {
352  // Extract unique integral values for the effective fields of a RegId.
353  const size_t index = static_cast<size_t>(reg_id.index());
354  const size_t class_num = static_cast<size_t>(reg_id.regClass);
355 
356  const size_t shifted_class_num =
357  class_num << (sizeof(gem5::RegIndex) << 3);
358 
359  // Concatenate the class_num to the end of the flat_index, in order to
360  // maximize information retained.
361  const size_t concatenated_hash = index | shifted_class_num;
362 
363  // If RegIndex is larger than size_t, then class_num will not be
364  // considered by this hash function, so we may wish to perform a
365  // different operation to include that information in the hash.
366  static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
367  "sizeof(RegIndex) should be less than sizeof(size_t)");
368 
369  return concatenated_hash;
370  }
371 };
372 } // namespace std
373 
374 #endif // __CPU__REG_CLASS_HH__
gem5::debug::Flag
Definition: debug.hh:62
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:322
gem5::PhysRegId::PhysRegId
PhysRegId()
Definition: reg_class.hh:253
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RegId::operator!=
constexpr bool operator!=(const RegId &that) const
Definition: reg_class.hh:155
gem5::RegId::isRenameable
constexpr bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:174
gem5::RegClass::_regShift
size_t _regShift
Definition: reg_class.hh:89
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:199
gem5::VecElemRegClassOps::elemsPerVec
size_t elemsPerVec
Definition: reg_class.hh:225
std::hash< gem5::RegId >::operator()
size_t operator()(const gem5::RegId &reg_id) const
Definition: reg_class.hh:350
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:67
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:304
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::RegId::operator<<
friend std::ostream & operator<<(std::ostream &os, const RegId &rid)
Definition: reg_class.hh:203
gem5::RegClass::valString
std::string valString(const void *val) const
Definition: reg_class.hh:115
gem5::RegClass::regBytes
constexpr size_t regBytes() const
Definition: reg_class.hh:109
gem5::RegClassOps::valString
virtual std::string valString(const void *val, size_t size) const
Print the value of a register pointed to by val of size size.
Definition: reg_class.cc:59
gem5::RegClass::debugFlag
const debug::Flag & debugFlag
Definition: reg_class.hh:93
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RegClass::_ops
RegClassOps * _ops
Definition: reg_class.hh:92
gem5::RegClassOps::regName
virtual std::string regName(const RegId &id) const
Print the name of the register specified in id.
Definition: reg_class.cc:53
gem5::TypedRegClassOps
Definition: reg_class.hh:210
gem5::RegId::className
constexpr const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:194
gem5::PhysRegId::decrNumPinnedWritesToComplete
void decrNumPinnedWritesToComplete()
Definition: reg_class.hh:336
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::RegClass::regName
std::string regName(const RegId &id) const
Definition: reg_class.hh:113
gem5::RegId::regClass
RegClassType regClass
Definition: reg_class.hh:130
gem5::TypedRegClassOps::valString
std::string valString(const void *val, size_t size) const override
Print the value of a register pointed to by val of size size.
Definition: reg_class.hh:214
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::VecElemRegClassOps::VecElemRegClassOps
VecElemRegClassOps(size_t elems_per_vec)
Definition: reg_class.hh:228
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:319
gem5::RegId::setNumPinnedWrites
void setNumPinnedWrites(int num_writes)
Definition: reg_class.hh:200
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:302
gem5::PhysRegId::pinned
bool pinned
Definition: reg_class.hh:250
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:337
gem5::RegId::operator==
constexpr bool operator==(const RegId &that) const
Definition: reg_class.hh:149
gem5::PhysRegId::operator!=
bool operator!=(const PhysRegId &that) const
Definition: reg_class.hh:289
gem5::RegId::regClassStrings
static const char * regClassStrings[]
Definition: reg_class.hh:129
gem5::RegId::operator<
constexpr bool operator<(const RegId &that) const
Order operator.
Definition: reg_class.hh:164
gem5::RegId::RegId
constexpr RegId(RegClassType reg_class, RegIndex reg_idx)
Definition: reg_class.hh:139
debug.hh
gem5::RegId::regIdx
RegIndex regIdx
Definition: reg_class.hh:131
cprintf.hh
gem5::PhysRegId::getNumPinnedWritesToComplete
int getNumPinnedWritesToComplete() const
Definition: reg_class.hh:325
gem5::PhysRegId::numPinnedWritesToComplete
int numPinnedWritesToComplete
Definition: reg_class.hh:249
gem5::RegClass
Definition: reg_class.hh:81
gem5::RegClass::RegClass
constexpr RegClass(size_t num_regs, RegClassOps &new_ops, const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal))
Definition: reg_class.hh:101
gem5::PhysRegId::operator<
bool operator<(const PhysRegId &that) const
Explicit forward methods, to prevent comparisons of PhysRegId with RegIds.
Definition: reg_class.hh:277
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::RegClass::RegClass
constexpr RegClass(size_t num_regs, const debug::Flag &debug_flag, size_t reg_bytes=sizeof(RegVal))
Definition: reg_class.hh:96
gem5::RegClass::regShift
constexpr size_t regShift() const
Definition: reg_class.hh:110
gem5::VecElemRegClassOps::regName
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition: reg_class.hh:233
gem5::ceilLog2
static constexpr int ceilLog2(const T &n)
Definition: intmath.hh:84
gem5::RegId::numPinnedWrites
int numPinnedWrites
Definition: reg_class.hh:132
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::RegClass::defaultOps
static RegClassOps defaultOps
Definition: reg_class.hh:91
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
std
Overload hash function for BasicBlockRange type.
Definition: misc.hh:2388
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:320
gem5::PhysRegId::flatIdx
RegIndex flatIdx
Definition: reg_class.hh:248
gem5::VecElemRegClassOps
Definition: reg_class.hh:222
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:307
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:331
gem5::PhysRegId::PhysRegId
PhysRegId(RegClassType _regClass, RegIndex _regIdx, RegIndex _flatIdx)
Scalar PhysRegId constructor.
Definition: reg_class.hh:258
gem5::PhysRegId::isFixedMapping
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
Definition: reg_class.hh:299
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:188
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId::classValue
constexpr RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:191
gem5::RegId::is
constexpr bool is(RegClassType reg_class) const
Definition: reg_class.hh:181
gem5::RegClass::_numRegs
size_t _numRegs
Definition: reg_class.hh:84
gem5::RegClassOps
Definition: reg_class.hh:72
gem5::RegClass::_regBytes
size_t _regBytes
Definition: reg_class.hh:85
gem5::RegClass::debug
constexpr const debug::Flag & debug() const
Definition: reg_class.hh:111
gem5::PhysRegId::operator==
bool operator==(const PhysRegId &that) const
Definition: reg_class.hh:283
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::RegClass::numRegs
constexpr size_t numRegs() const
Definition: reg_class.hh:108
gem5::RegId::RegId
constexpr RegId()
Definition: reg_class.hh:137

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