gem5  v21.2.1.1
reg_class.hh
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40 
41 #ifndef __CPU__REG_CLASS_HH__
42 #define __CPU__REG_CLASS_HH__
43 
44 #include <cassert>
45 #include <cstddef>
46 #include <string>
47 
48 #include "arch/vecregs.hh"
49 #include "base/types.hh"
50 #include "config/the_isa.hh"
51 
52 namespace gem5
53 {
54 
57 {
60 
67 };
68 
69 class RegId;
70 
72 {
73  public:
74  virtual std::string regName(const RegId &id) const = 0;
75 };
76 
78 {
79  public:
80  std::string regName(const RegId &id) const override;
81 };
82 
83 class RegClass
84 {
85  private:
86  size_t _size;
88 
91 
92  public:
93  RegClass(size_t new_size, RegIndex new_zero=-1) :
94  _size(new_size), _zeroReg(new_zero)
95  {}
96  RegClass(size_t new_size, RegClassOps &new_ops, RegIndex new_zero=-1) :
97  RegClass(new_size, new_zero)
98  {
99  _ops = &new_ops;
100  }
101 
102  size_t size() const { return _size; }
103  RegIndex zeroReg() const { return _zeroReg; }
104 
105  std::string regName(const RegId &id) const { return _ops->regName(id); }
106 };
107 
113 class RegId
114 {
115  protected:
116  static const char* regClassStrings[];
120  static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
122 
123  friend struct std::hash<RegId>;
124 
125  public:
127 
128  RegId(RegClassType reg_class, RegIndex reg_idx)
129  : RegId(reg_class, reg_idx, IllegalElemIndex) {}
130 
131  explicit RegId(RegClassType reg_class, RegIndex reg_idx,
132  ElemIndex elem_idx)
133  : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
134  numPinnedWrites(0)
135  {
136  if (elemIdx == IllegalElemIndex) {
138  "Creating vector physical index w/o element index");
139  } else {
141  "Creating non-vector physical index w/ element index");
142  }
143  }
144 
145  bool
146  operator==(const RegId& that) const
147  {
148  return regClass == that.classValue() && regIdx == that.index() &&
149  elemIdx == that.elemIndex();
150  }
151 
152  bool operator!=(const RegId& that) const { return !(*this==that); }
153 
157  bool
158  operator<(const RegId& that) const
159  {
160  return regClass < that.classValue() ||
161  (regClass == that.classValue() && (
162  regIdx < that.index() ||
163  (regIdx == that.index() && elemIdx < that.elemIndex())));
164  }
165 
169  bool
170  isRenameable() const
171  {
172  return regClass != MiscRegClass;
173  }
174 
176  bool is(RegClassType reg_class) const { return regClass == reg_class; }
177 
180  RegIndex index() const { return regIdx; }
181 
185  RegIndex
186  flatIndex() const
187  {
188  switch (regClass) {
189  case IntRegClass:
190  case FloatRegClass:
191  case VecRegClass:
192  case VecPredRegClass:
193  case CCRegClass:
194  case MiscRegClass:
195  return regIdx;
196  case VecElemClass:
197  return Scale * regIdx + elemIdx;
198  }
199  panic("Trying to flatten a register without class!");
200  }
204  RegIndex elemIndex() const { return elemIdx; }
206  RegClassType classValue() const { return regClass; }
208  const char* className() const { return regClassStrings[regClass]; }
209 
210  int getNumPinnedWrites() const { return numPinnedWrites; }
211  void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
212 
213  friend std::ostream&
214  operator<<(std::ostream& os, const RegId& rid)
215  {
216  return os << rid.className() << "{" << rid.index() << "}";
217  }
218 };
219 
224 class PhysRegId : private RegId
225 {
226  private:
229  bool pinned;
230 
231  public:
232  explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1),
234  {}
235 
237  explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
238  RegIndex _flatIdx)
239  : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
241  {}
242 
244  explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
245  ElemIndex elem_idx, RegIndex flat_idx)
246  : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx),
248  {}
249 
252  using RegId::index;
253  using RegId::classValue;
254  using RegId::className;
255  using RegId::elemIndex;
256  using RegId::is;
263  bool
264  operator<(const PhysRegId& that) const
265  {
266  return RegId::operator<(that);
267  }
268 
269  bool
270  operator==(const PhysRegId& that) const
271  {
272  return RegId::operator==(that);
273  }
274 
275  bool
276  operator!=(const PhysRegId& that) const
277  {
278  return RegId::operator!=(that);
279  }
286  bool isFixedMapping() const { return !isRenameable(); }
287 
289  const RegIndex& flatIndex() const { return flatIdx; }
290 
291  static PhysRegId
293  {
294  assert(vid->is(VecRegClass));
295  return PhysRegId(VecElemClass, vid->index(), elem);
296  }
297 
298  int getNumPinnedWrites() const { return numPinnedWrites; }
299 
300  void
301  setNumPinnedWrites(int numWrites)
302  {
303  // An instruction with a pinned destination reg can get
304  // squashed. The numPinnedWrites counter may be zero when
305  // the squash happens but we need to know if the dest reg
306  // was pinned originally in order to reset counters properly
307  // for a possible re-rename using the same physical reg (which
308  // may be required in case of a mem access order violation).
309  pinned = (numWrites != 0);
310  numPinnedWrites = numWrites;
311  }
312 
315 
316  bool isPinned() const { return pinned; }
317 
318  int
320  {
322  }
323 
324  void
326  {
327  numPinnedWritesToComplete = numWrites;
328  }
329 
332 };
333 
335 
336 } // namespace gem5
337 
338 namespace std
339 {
340 template<>
341 struct hash<gem5::RegId>
342 {
343  size_t
344  operator()(const gem5::RegId& reg_id) const
345  {
346  // Extract unique integral values for the effective fields of a RegId.
347  const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
348  const size_t class_num = static_cast<size_t>(reg_id.regClass);
349 
350  const size_t shifted_class_num =
351  class_num << (sizeof(gem5::RegIndex) << 3);
352 
353  // Concatenate the class_num to the end of the flat_index, in order to
354  // maximize information retained.
355  const size_t concatenated_hash = flat_index | shifted_class_num;
356 
357  // If RegIndex is larger than size_t, then class_num will not be
358  // considered by this hash function, so we may wish to perform a
359  // different operation to include that information in the hash.
360  static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
361  "sizeof(RegIndex) should be less than sizeof(size_t)");
362 
363  return concatenated_hash;
364  }
365 };
366 } // namespace std
367 
368 #endif // __CPU__REG_CLASS_HH__
gem5::RegClass::_zeroReg
const RegIndex _zeroReg
Definition: reg_class.hh:87
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:316
gem5::PhysRegId::PhysRegId
PhysRegId()
Definition: reg_class.hh:232
gem5::PhysRegId::elemId
static PhysRegId elemId(PhysRegId *vid, ElemIndex elem)
Definition: reg_class.hh:292
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:210
std::hash< gem5::RegId >::operator()
size_t operator()(const gem5::RegId &reg_id) const
Definition: reg_class.hh:344
gem5::RegClass::zeroReg
RegIndex zeroReg() const
Definition: reg_class.hh:103
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::RegId::flatIndex
RegIndex flatIndex() const
Index flattening.
Definition: reg_class.hh:186
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:298
gem5::RegClass::_size
size_t _size
Definition: reg_class.hh:86
gem5::PhysRegId::PhysRegId
PhysRegId(RegClassType _regClass, RegIndex _regIdx, ElemIndex elem_idx, RegIndex flat_idx)
Vector PhysRegId constructor (w/ elemIndex).
Definition: reg_class.hh:244
gem5::RegId::operator<<
friend std::ostream & operator<<(std::ostream &os, const RegId &rid)
Definition: reg_class.hh:214
gem5::RegClass::_ops
RegClassOps * _ops
Definition: reg_class.hh:90
gem5::RegId::operator!=
bool operator!=(const RegId &that) const
Definition: reg_class.hh:152
gem5::RegId::is
bool is(RegClassType reg_class) const
Definition: reg_class.hh:176
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:180
gem5::PhysRegId::decrNumPinnedWritesToComplete
void decrNumPinnedWritesToComplete()
Definition: reg_class.hh:330
gem5::RegClass::RegClass
RegClass(size_t new_size, RegClassOps &new_ops, RegIndex new_zero=-1)
Definition: reg_class.hh:96
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::RegClass::regName
std::string regName(const RegId &id) const
Definition: reg_class.hh:105
gem5::RegId::regClass
RegClassType regClass
Definition: reg_class.hh:117
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::RegClass::size
size_t size() const
Definition: reg_class.hh:102
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:313
gem5::RegId::setNumPinnedWrites
void setNumPinnedWrites(int num_writes)
Definition: reg_class.hh:211
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:289
gem5::RegId::operator==
bool operator==(const RegId &that) const
Definition: reg_class.hh:146
gem5::RegId::isRenameable
bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:170
gem5::PhysRegId::pinned
bool pinned
Definition: reg_class.hh:229
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:331
gem5::DefaultRegClassOps
Definition: reg_class.hh:77
gem5::PhysRegId::operator!=
bool operator!=(const PhysRegId &that) const
Definition: reg_class.hh:276
gem5::RegId::regClassStrings
static const char * regClassStrings[]
Definition: reg_class.hh:116
gem5::RegId::regIdx
RegIndex regIdx
Definition: reg_class.hh:118
gem5::RegClassOps::regName
virtual std::string regName(const RegId &id) const =0
gem5::PhysRegId::getNumPinnedWritesToComplete
int getNumPinnedWritesToComplete() const
Definition: reg_class.hh:319
gem5::RegId::className
const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:208
gem5::RegId::classValue
RegClassType classValue() const
Class accessor.
Definition: reg_class.hh:206
gem5::PhysRegId::numPinnedWritesToComplete
int numPinnedWritesToComplete
Definition: reg_class.hh:228
gem5::RegClass
Definition: reg_class.hh:83
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::RegId::operator<
bool operator<(const RegId &that) const
Order operator.
Definition: reg_class.hh:158
gem5::RegClass::defaultOps
static DefaultRegClassOps defaultOps
Definition: reg_class.hh:89
gem5::PhysRegId::operator<
bool operator<(const PhysRegId &that) const
Explicit forward methods, to prevent comparisons of PhysRegId with RegIds.
Definition: reg_class.hh:264
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::RegId::elemIndex
RegIndex elemIndex() const
Elem accessor.
Definition: reg_class.hh:204
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::RegId::elemIdx
ElemIndex elemIdx
Definition: reg_class.hh:119
gem5::RegId::numPinnedWrites
int numPinnedWrites
Definition: reg_class.hh:121
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::PhysRegId::is
bool is(RegClassType reg_class) const
Definition: reg_class.hh:176
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:314
gem5::RegClass::RegClass
RegClass(size_t new_size, RegIndex new_zero=-1)
Definition: reg_class.hh:93
gem5::RegId::RegId
RegId(RegClassType reg_class, RegIndex reg_idx)
Definition: reg_class.hh:128
gem5::PhysRegId::flatIdx
RegIndex flatIdx
Definition: reg_class.hh:227
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:301
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:224
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:325
gem5::PhysRegId::PhysRegId
PhysRegId(RegClassType _regClass, RegIndex _regIdx, RegIndex _flatIdx)
Scalar PhysRegId constructor.
Definition: reg_class.hh:237
gem5::RegId::RegId
RegId()
Definition: reg_class.hh:126
gem5::PhysRegId::isFixedMapping
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
Definition: reg_class.hh:286
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::RegId::RegId
RegId(RegClassType reg_class, RegIndex reg_idx, ElemIndex elem_idx)
Definition: reg_class.hh:131
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::RegId::Scale
static constexpr size_t Scale
Definition: reg_class.hh:120
gem5::DefaultRegClassOps::regName
std::string regName(const RegId &id) const override
Definition: reg_class.cc:48
gem5::PhysRegId::index
RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:180
gem5::RegClassOps
Definition: reg_class.hh:71
gem5::IllegalElemIndex
static const ElemIndex IllegalElemIndex
ElemIndex value that indicates that the register is not a vector.
Definition: types.hh:182
gem5::PhysRegId::operator==
bool operator==(const PhysRegId &that) const
Definition: reg_class.hh:270
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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