gem5  v21.1.0.2
reg_class.hh
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40 
41 #ifndef __CPU__REG_CLASS_HH__
42 #define __CPU__REG_CLASS_HH__
43 
44 #include <cassert>
45 #include <cstddef>
46 
47 #include "arch/vecregs.hh"
48 #include "base/types.hh"
49 #include "config/the_isa.hh"
50 
51 namespace gem5
52 {
53 
56 {
59 
66 };
67 
69 {
70  private:
71  size_t _size;
73 
74  public:
75  RegClassInfo(size_t new_size, RegIndex new_zero = -1) :
76  _size(new_size), _zeroReg(new_zero)
77  {}
78 
79  size_t size() const { return _size; }
80  RegIndex zeroReg() const { return _zeroReg; }
81 };
82 
88 class RegId
89 {
90  protected:
91  static const char* regClassStrings[];
95  static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
97 
98  friend struct std::hash<RegId>;
99 
100  public:
102 
103  RegId(RegClass reg_class, RegIndex reg_idx)
104  : RegId(reg_class, reg_idx, IllegalElemIndex) {}
105 
106  explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
107  : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
108  numPinnedWrites(0)
109  {
110  if (elemIdx == IllegalElemIndex) {
112  "Creating vector physical index w/o element index");
113  } else {
115  "Creating non-vector physical index w/ element index");
116  }
117  }
118 
119  bool
120  operator==(const RegId& that) const
121  {
122  return regClass == that.classValue() && regIdx == that.index() &&
123  elemIdx == that.elemIndex();
124  }
125 
126  bool operator!=(const RegId& that) const { return !(*this==that); }
127 
131  bool
132  operator<(const RegId& that) const
133  {
134  return regClass < that.classValue() ||
135  (regClass == that.classValue() && (
136  regIdx < that.index() ||
137  (regIdx == that.index() && elemIdx < that.elemIndex())));
138  }
139 
143  bool
144  isRenameable() const
145  {
146  return regClass != MiscRegClass;
147  }
148 
150  bool is(RegClass reg_class) const { return regClass == reg_class; }
151 
154  RegIndex index() const { return regIdx; }
155 
159  RegIndex
160  flatIndex() const
161  {
162  switch (regClass) {
163  case IntRegClass:
164  case FloatRegClass:
165  case VecRegClass:
166  case VecPredRegClass:
167  case CCRegClass:
168  case MiscRegClass:
169  return regIdx;
170  case VecElemClass:
171  return Scale * regIdx + elemIdx;
172  }
173  panic("Trying to flatten a register without class!");
174  }
178  RegIndex elemIndex() const { return elemIdx; }
180  RegClass classValue() const { return regClass; }
182  const char* className() const { return regClassStrings[regClass]; }
183 
184  int getNumPinnedWrites() const { return numPinnedWrites; }
185  void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
186 
187  friend std::ostream&
188  operator<<(std::ostream& os, const RegId& rid)
189  {
190  return os << rid.className() << "{" << rid.index() << "}";
191  }
192 };
193 
198 class PhysRegId : private RegId
199 {
200  private:
203  bool pinned;
204 
205  public:
206  explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1),
208  {}
209 
211  explicit PhysRegId(RegClass _regClass, RegIndex _regIdx,
212  RegIndex _flatIdx)
213  : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
215  {}
216 
218  explicit PhysRegId(RegClass _regClass, RegIndex _regIdx,
219  ElemIndex elem_idx, RegIndex flat_idx)
220  : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx),
222  {}
223 
226  using RegId::index;
227  using RegId::classValue;
228  using RegId::className;
229  using RegId::elemIndex;
230  using RegId::is;
237  bool
238  operator<(const PhysRegId& that) const
239  {
240  return RegId::operator<(that);
241  }
242 
243  bool
244  operator==(const PhysRegId& that) const
245  {
246  return RegId::operator==(that);
247  }
248 
249  bool
250  operator!=(const PhysRegId& that) const
251  {
252  return RegId::operator!=(that);
253  }
260  bool isFixedMapping() const { return !isRenameable(); }
261 
263  const RegIndex& flatIndex() const { return flatIdx; }
264 
265  static PhysRegId
267  {
268  assert(vid->is(VecRegClass));
269  return PhysRegId(VecElemClass, vid->index(), elem);
270  }
271 
272  int getNumPinnedWrites() const { return numPinnedWrites; }
273 
274  void
275  setNumPinnedWrites(int numWrites)
276  {
277  // An instruction with a pinned destination reg can get
278  // squashed. The numPinnedWrites counter may be zero when
279  // the squash happens but we need to know if the dest reg
280  // was pinned originally in order to reset counters properly
281  // for a possible re-rename using the same physical reg (which
282  // may be required in case of a mem access order violation).
283  pinned = (numWrites != 0);
284  numPinnedWrites = numWrites;
285  }
286 
289 
290  bool isPinned() const { return pinned; }
291 
292  int
294  {
296  }
297 
298  void
300  {
301  numPinnedWritesToComplete = numWrites;
302  }
303 
306 };
307 
309 
310 } // namespace gem5
311 
312 namespace std
313 {
314 template<>
315 struct hash<gem5::RegId>
316 {
317  size_t
318  operator()(const gem5::RegId& reg_id) const
319  {
320  // Extract unique integral values for the effective fields of a RegId.
321  const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
322  const size_t class_num = static_cast<size_t>(reg_id.regClass);
323 
324  const size_t shifted_class_num =
325  class_num << (sizeof(gem5::RegIndex) << 3);
326 
327  // Concatenate the class_num to the end of the flat_index, in order to
328  // maximize information retained.
329  const size_t concatenated_hash = flat_index | shifted_class_num;
330 
331  // If RegIndex is larger than size_t, then class_num will not be
332  // considered by this hash function, so we may wish to perform a
333  // different operation to include that information in the hash.
334  static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
335  "sizeof(RegIndex) should be less than sizeof(size_t)");
336 
337  return concatenated_hash;
338  }
339 };
340 } // namespace std
341 
342 #endif // __CPU__REG_CLASS_HH__
gem5::ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: vec.hh:58
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:62
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:290
gem5::PhysRegId::PhysRegId
PhysRegId()
Definition: reg_class.hh:206
gem5::PhysRegId::elemId
static PhysRegId elemId(PhysRegId *vid, ElemIndex elem)
Definition: reg_class.hh:266
gem5::RegClass
RegClass
Enumerate the classes of registers.
Definition: reg_class.hh:55
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:184
std::hash< gem5::RegId >::operator()
size_t operator()(const gem5::RegId &reg_id) const
Definition: reg_class.hh:318
gem5::RegId::regClass
RegClass regClass
Definition: reg_class.hh:92
gem5::RegId::flatIndex
RegIndex flatIndex() const
Index flattening.
Definition: reg_class.hh:160
gem5::RegClassInfo::zeroReg
RegIndex zeroReg() const
Definition: reg_class.hh:80
gem5::RegClassInfo::RegClassInfo
RegClassInfo(size_t new_size, RegIndex new_zero=-1)
Definition: reg_class.hh:75
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:272
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::RegClassInfo::_zeroReg
const RegIndex _zeroReg
Definition: reg_class.hh:72
gem5::RegId::operator<<
friend std::ostream & operator<<(std::ostream &os, const RegId &rid)
Definition: reg_class.hh:188
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::RegId::operator!=
bool operator!=(const RegId &that) const
Definition: reg_class.hh:126
gem5::RegId::classValue
RegClass classValue() const
Class accessor.
Definition: reg_class.hh:180
gem5::PhysRegId::PhysRegId
PhysRegId(RegClass _regClass, RegIndex _regIdx, ElemIndex elem_idx, RegIndex flat_idx)
Vector PhysRegId constructor (w/ elemIndex).
Definition: reg_class.hh:218
gem5::RegId::index
RegIndex index() const
Index accessors.
Definition: reg_class.hh:154
gem5::RegClassInfo::size
size_t size() const
Definition: reg_class.hh:79
gem5::PhysRegId::decrNumPinnedWritesToComplete
void decrNumPinnedWritesToComplete()
Definition: reg_class.hh:304
gem5::RegId::is
bool is(RegClass reg_class) const
Definition: reg_class.hh:150
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:287
gem5::RegId::setNumPinnedWrites
void setNumPinnedWrites(int num_writes)
Definition: reg_class.hh:185
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:263
gem5::RegId::operator==
bool operator==(const RegId &that) const
Definition: reg_class.hh:120
gem5::RegId::isRenameable
bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:144
gem5::PhysRegId::pinned
bool pinned
Definition: reg_class.hh:203
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:305
gem5::PhysRegId::operator!=
bool operator!=(const PhysRegId &that) const
Definition: reg_class.hh:250
gem5::RegId::regClassStrings
static const char * regClassStrings[]
Definition: reg_class.hh:91
gem5::PhysRegId::PhysRegId
PhysRegId(RegClass _regClass, RegIndex _regIdx, RegIndex _flatIdx)
Scalar PhysRegId constructor.
Definition: reg_class.hh:211
gem5::RegId::regIdx
RegIndex regIdx
Definition: reg_class.hh:93
gem5::RegClassInfo::_size
size_t _size
Definition: reg_class.hh:71
gem5::PhysRegId::getNumPinnedWritesToComplete
int getNumPinnedWritesToComplete() const
Definition: reg_class.hh:293
gem5::RegId::className
const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:182
gem5::PhysRegId::numPinnedWritesToComplete
int numPinnedWritesToComplete
Definition: reg_class.hh:202
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::RegId::operator<
bool operator<(const RegId &that) const
Order operator.
Definition: reg_class.hh:132
gem5::RegId::RegId
RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
Definition: reg_class.hh:106
gem5::PhysRegId::operator<
bool operator<(const PhysRegId &that) const
Explicit forward methods, to prevent comparisons of PhysRegId with RegIds.
Definition: reg_class.hh:238
gem5::RegId::elemIndex
RegIndex elemIndex() const
Elem accessor.
Definition: reg_class.hh:178
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::RegId::elemIdx
ElemIndex elemIdx
Definition: reg_class.hh:94
gem5::RegId::numPinnedWrites
int numPinnedWrites
Definition: reg_class.hh:96
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::RegId::RegId
RegId(RegClass reg_class, RegIndex reg_idx)
Definition: reg_class.hh:103
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:288
gem5::PhysRegId::flatIdx
RegIndex flatIdx
Definition: reg_class.hh:201
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:275
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:299
gem5::RegClassInfo
Definition: reg_class.hh:68
gem5::RegId::RegId
RegId()
Definition: reg_class.hh:101
gem5::PhysRegId::isFixedMapping
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
Definition: reg_class.hh:260
gem5::PhysRegId::is
bool is(RegClass reg_class) const
Definition: reg_class.hh:150
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::RegId::Scale
static constexpr size_t Scale
Definition: reg_class.hh:95
gem5::PhysRegId::index
RegIndex index() const
Visible RegId methods.
Definition: reg_class.hh:154
gem5::IllegalElemIndex
static const ElemIndex IllegalElemIndex
ElemIndex value that indicates that the register is not a vector.
Definition: types.hh:182
gem5::PhysRegId::operator==
bool operator==(const PhysRegId &that) const
Definition: reg_class.hh:244
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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