gem5  v22.0.0.1
cc.hh
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37 
38 #ifndef __ARCH_ARM_REGS_CC_HH__
39 #define __ARCH_ARM_REGS_CC_HH__
40 
41 #include "cpu/reg_class.hh"
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA
47 {
48 
49 namespace cc_reg
50 {
51 
52 enum : RegIndex
53 {
61 };
62 
63 inline constexpr RegId
65  C(CCRegClass, _CIdx),
66  V(CCRegClass, _VIdx),
70 
71 const char * const RegName[NumRegs] = {
72  "nz",
73  "c",
74  "v",
75  "ge",
76  "fp",
77  "zero"
78 };
79 
80 } // namespace cc_reg
81 
83 {
84  COND_EQ = 0,
85  COND_NE, // 1
86  COND_CS, // 2
87  COND_CC, // 3
88  COND_MI, // 4
89  COND_PL, // 5
90  COND_VS, // 6
91  COND_VC, // 7
92  COND_HI, // 8
93  COND_LS, // 9
94  COND_GE, // 10
95  COND_LT, // 11
96  COND_GT, // 12
97  COND_LE, // 13
98  COND_AL, // 14
99  COND_UC // 15
100 };
101 
102 } // namespace ArmISA
103 } // namespace gem5
104 
105 #endif // __ARCH_ARM_REGS_CC_HH__
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:92
gem5::ArmISA::cc_reg::_FpIdx
@ _FpIdx
Definition: cc.hh:58
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:85
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::ArmISA::cc_reg::_VIdx
@ _VIdx
Definition: cc.hh:56
gem5::ArmISA::cc_reg::Fp
constexpr RegId Fp(CCRegClass, _FpIdx)
gem5::ArmISA::cc_reg::RegName
const char *const RegName[NumRegs]
Definition: cc.hh:71
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:89
gem5::ArmISA::cc_reg::Nz
constexpr RegId Nz(CCRegClass, _NzIdx)
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:86
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:95
gem5::ArmISA::cc_reg::NumRegs
@ NumRegs
Definition: cc.hh:60
gem5::ArmISA::cc_reg::V
constexpr RegId V(CCRegClass, _VIdx)
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:91
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:99
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:84
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:90
gem5::ArmISA::cc_reg::_ZeroIdx
@ _ZeroIdx
Definition: cc.hh:59
gem5::ArmISA::cc_reg::_NzIdx
@ _NzIdx
Definition: cc.hh:54
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:98
gem5::ArmISA::cc_reg::_GeIdx
@ _GeIdx
Definition: cc.hh:57
gem5::ArmISA::cc_reg::C
constexpr RegId C(CCRegClass, _CIdx)
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:88
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:93
gem5::ArmISA::cc_reg::Ge
constexpr RegId Ge(CCRegClass, _GeIdx)
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:97
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:82
reg_class.hh
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:94
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::cc_reg::Zero
constexpr RegId Zero(CCRegClass, _ZeroIdx)
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:96
gem5::ArmISA::cc_reg::_CIdx
@ _CIdx
Definition: cc.hh:55
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:87

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