gem5  v22.1.0.0
gem5::Gicv3 Member List

This is the complete list of members for gem5::Gicv3, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
addrRangesgem5::Gicv3protected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BaseGic(const Params &p)gem5::BaseGic
blockIntUpdate() constgem5::BaseGicinlineprotectedvirtual
clearDistRange(Gicv3Registers *to, Addr daddr, size_t size)gem5::Gicv3Registersprotectedstatic
clearInt(uint32_t int_id) overridegem5::Gicv3protectedvirtual
clearPPInt(uint32_t int_id, uint32_t cpu) overridegem5::Gicv3protectedvirtual
clearRedistRegister(Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)gem5::Gicv3Registersprotectedstatic
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
copyCpuRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg)gem5::Gicv3Registersprotectedstatic
copyDistRange(Gicv3Registers *from, Gicv3Registers *to, Addr daddr, size_t size)gem5::Gicv3Registersprotectedstatic
copyDistRegister(Gicv3Registers *from, Gicv3Registers *to, Addr daddr)gem5::Gicv3Registersprotectedstatic
copyGicState(Gicv3Registers *from, Gicv3Registers *to)gem5::Gicv3protected
copyRedistRange(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr, size_t size)gem5::Gicv3Registersprotectedstatic
copyRedistRegister(Gicv3Registers *from, Gicv3Registers *to, const ArmISA::Affinity &aff, Addr daddr)gem5::Gicv3Registersprotectedstatic
cpuInterfacesgem5::Gicv3protected
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deassertAll(uint32_t cpu)gem5::Gicv3
deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type)gem5::Gicv3
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
distRangegem5::Gicv3protected
distributorgem5::Gicv3protected
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
G0S enum valuegem5::Gicv3
G1NS enum valuegem5::Gicv3
G1S enum valuegem5::Gicv3
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRanges() const overridegem5::Gicv3inlineprotectedvirtual
getCPUInterface(int cpu_id) constgem5::Gicv3inline
getCPUInterfaceByAffinity(const ArmISA::Affinity &aff) constgem5::Gicv3
getDistributor() constgem5::Gicv3inline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::PioDevicevirtual
getProbeManager()gem5::SimObject
getRedistributor(ContextID context_id) constgem5::Gicv3inline
getRedistributorByAddr(Addr address) constgem5::Gicv3
getRedistributorByAffinity(const ArmISA::Affinity &aff) constgem5::Gicv3
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getSystem() constgem5::BaseGicinline
Gicv3(const Params &p)gem5::Gicv3
Gicv3CPUInterface classgem5::Gicv3friend
Gicv3Distributor classgem5::Gicv3friend
Gicv3Redistributor classgem5::Gicv3friend
GicVersion enum namegem5::BaseGic
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
GroupId enum namegem5::Gicv3
haveAsserted(uint32_t cpu) constgem5::Gicv3
init() overridegem5::Gicv3protectedvirtual
initState()gem5::SimObjectvirtual
INT_ACTIVE enum valuegem5::Gicv3
INT_ACTIVE_PENDING enum valuegem5::Gicv3
INT_EDGE_TRIGGERED enum valuegem5::Gicv3
INT_INACTIVE enum valuegem5::Gicv3
INT_LEVEL_SENSITIVE enum valuegem5::Gicv3
INT_PENDING enum valuegem5::Gicv3
INTID_NONSECUREgem5::Gicv3static
INTID_SECUREgem5::Gicv3static
INTID_SPURIOUSgem5::Gicv3static
IntStatus enum namegem5::Gicv3
IntTriggerType enum namegem5::Gicv3
itsgem5::Gicv3protected
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
Params typedefgem5::BaseGic
PARAMS(Gicv3)gem5::Gicv3protected
params() constgem5::BaseGic
pathgem5::Serializableprivatestatic
PioDevice(const Params &p)gem5::PioDevice
pioPortgem5::PioDeviceprotected
platformgem5::BaseGicprotected
postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)gem5::Gicv3
powerStategem5::ClockedObject
PPI_MAXgem5::Gicv3static
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
read(PacketPtr pkt) overridegem5::Gicv3protectedvirtual
readCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg) overridegem5::Gicv3virtual
readDistributor(Addr daddr) overridegem5::Gicv3virtual
readRedistributor(const ArmISA::Affinity &aff, Addr daddr) overridegem5::Gicv3virtual
redistRangegem5::Gicv3protected
redistributorsgem5::Gicv3protected
redistSizegem5::Gicv3protected
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
reset()gem5::Gicv3protected
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
sendInt(uint32_t int_id) overridegem5::Gicv3protectedvirtual
sendPPInt(uint32_t int_id, uint32_t cpu) overridegem5::Gicv3protectedvirtual
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::Gicv3protectedvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
SGI_MAXgem5::Gicv3static
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
simObjectListgem5::SimObjectprivatestatic
SimObjectList typedefgem5::SimObjectprivate
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
supportsVersion(GicVersion version) overridegem5::Gicv3protectedvirtual
sysgem5::PioDeviceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
unserialize(CheckpointIn &cp) overridegem5::Gicv3protectedvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
write(PacketPtr pkt) overridegem5::Gicv3protectedvirtual
writeCpu(const ArmISA::Affinity &aff, ArmISA::MiscRegIndex misc_reg, RegVal data) overridegem5::Gicv3virtual
writeDistributor(Addr daddr, uint32_t data) overridegem5::Gicv3virtual
writeRedistributor(const ArmISA::Affinity &aff, Addr daddr, uint32_t data) overridegem5::Gicv3virtual
~BaseGic()gem5::BaseGicvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~PioDevice()gem5::PioDevicevirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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