gem5 v24.0.0.0
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This device is the base class which all devices senstive to an address range inherit from. More...
#include <io_device.hh>
Public Types | |
using | Params = PioDeviceParams |
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using | Params = ClockedObjectParams |
Parameters of ClockedObject. | |
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typedef SimObjectParams | Params |
Public Member Functions | |
PioDevice (const Params &p) | |
virtual | ~PioDevice () |
void | init () override |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
Get a port with a given name and index. | |
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ClockedObject (const ClockedObjectParams &p) | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
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void | updateClockPeriod () |
Update the tick to the current tick. | |
Tick | clockEdge (Cycles cycles=Cycles(0)) const |
Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. | |
Cycles | curCycle () const |
Determine the current cycle, corresponding to a tick aligned to a clock edge. | |
Tick | nextCycle () const |
Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. | |
uint64_t | frequency () const |
Tick | clockPeriod () const |
double | voltage () const |
Cycles | ticksToCycles (Tick t) const |
Tick | cyclesToTicks (Cycles c) const |
Protected Member Functions | |
virtual AddrRangeList | getAddrRanges () const =0 |
Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to. | |
virtual Tick | read (PacketPtr pkt)=0 |
Pure virtual function that the device must implement. | |
virtual Tick | write (PacketPtr pkt)=0 |
Pure virtual function that the device must implement. | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
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Clocked (ClockDomain &clk_domain) | |
Create a clocked object and set the clock domain based on the parameters. | |
Clocked (Clocked &)=delete | |
Clocked & | operator= (Clocked &)=delete |
virtual | ~Clocked () |
Virtual destructor due to inheritance. | |
void | resetClock () const |
Reset the object's clock using the current global tick value. | |
virtual void | clockPeriodUpdated () |
A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. | |
Protected Attributes | |
System * | sys |
PioPort< PioDevice > | pioPort |
The pioPort that handles the requests for us and provides us requests that it sees. | |
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const SimObjectParams & | _params |
Cached copy of the object parameters. | |
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EventQueue * | eventq |
A pointer to this object's event queue. | |
Friends | |
class | PioPort< PioDevice > |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
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PowerState * | powerState |
This device is the base class which all devices senstive to an address range inherit from.
There are three pure virtual functions which all devices must implement getAddrRanges(), read(), and write(). The magic do choose which mode we are in, etc is handled by the PioPort so the device doesn't have to bother.
Definition at line 102 of file io_device.hh.
using gem5::PioDevice::Params = PioDeviceParams |
Definition at line 134 of file io_device.hh.
gem5::PioDevice::PioDevice | ( | const Params & | p | ) |
Definition at line 50 of file io_device.cc.
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virtual |
Definition at line 54 of file io_device.cc.
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protectedpure virtual |
Every PIO device is obliged to provide an implementation that returns the address ranges the device responds to.
Implemented in gem5::AMDGPUDevice, gem5::AMDGPUInterruptHandler, gem5::AMDGPUSystemHub, gem5::BasicPioDevice, gem5::fastmodel::GIC, gem5::GenericPciHost, gem5::GenericTimerFrame, gem5::GenericTimerMem, gem5::GenericWatchdog, gem5::GicV2, gem5::Gicv2m, gem5::Gicv3, gem5::Gicv3Its, gem5::GPUCommandProcessor, gem5::HDLcd, gem5::HSAPacketProcessor, gem5::Iob, gem5::LupioBLK, gem5::MHU, gem5::NoMaliGpu, gem5::PciDevice, gem5::Pl111, gem5::PM4PacketProcessor, gem5::qemu::FwCfg, gem5::SDMAEngine, gem5::TesterDma, gem5::Uart8250, gem5::UFSHostDevice, gem5::VGic, gem5::X86ISA::I8042, and gem5::X86ISA::I8259.
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overridevirtual |
Get a port with a given name and index.
This is used at binding time and returns a reference to a protocol-agnostic port.
gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.
if_name | Port name |
idx | Index in the case of a VectorPort |
Reimplemented from gem5::SimObject.
Reimplemented in gem5::fastmodel::ResetControllerExample, and gem5::X86IdeController.
Definition at line 67 of file io_device.cc.
References gem5::SimObject::getPort(), and pioPort.
Referenced by gem5::Clint::getPort(), gem5::DmaDevice::getPort(), gem5::fastmodel::GIC::getPort(), gem5::fastmodel::ResetControllerExample::getPort(), gem5::Gicv3Its::getPort(), gem5::X86ISA::Cmos::getPort(), gem5::X86ISA::I8042::getPort(), gem5::X86ISA::I82094AA::getPort(), gem5::X86ISA::I8254::getPort(), and gem5::X86ISA::I8259::getPort().
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overridevirtual |
init() is called after all C++ SimObjects have been created and all ports are connected.
Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.
Reimplemented from gem5::SimObject.
Reimplemented in gem5::Plic.
Definition at line 59 of file io_device.cc.
References gem5::Named::name(), panic, and pioPort.
Referenced by gem5::BaseGic::init(), gem5::Clint::init(), gem5::CpuLocalTimer::init(), gem5::DmaDevice::init(), gem5::EnergyCtrl::init(), gem5::Plic::init(), gem5::X86ISA::I82094AA::init(), and gem5::X86ISA::I8259::init().
Pure virtual function that the device must implement.
Called when a read command is recieved by the port.
pkt | Packet describing this request |
Implemented in gem5::A9SCU, gem5::AmbaFake, gem5::AMDGPUDevice, gem5::AMDGPUInterruptHandler, gem5::AMDGPUSystemHub, gem5::BadDevice, gem5::Clint, gem5::CopyEngine, gem5::CpuLocalTimer, gem5::DumbTOD, gem5::EnergyCtrl, gem5::fastmodel::GIC, gem5::fastmodel::ResetControllerExample, gem5::FVPBasePwrCtrl, gem5::GenericPciHost, gem5::GenericTimerFrame, gem5::GenericTimerMem, gem5::GenericWatchdog, gem5::GicV2, gem5::Gicv2m, gem5::Gicv3, gem5::Gicv3Its, gem5::GPUCommandProcessor, gem5::HDLcd, gem5::I2CBus, gem5::IdeController, gem5::IGbE, gem5::Iob, gem5::IsaFake, gem5::LupioBLK, gem5::LupioIPI, gem5::LupioPIC, gem5::LupioRNG, gem5::LupioRTC, gem5::LupioSYS, gem5::LupioTMR, gem5::LupioTTY, gem5::MaltaCChip, gem5::MaltaIO, gem5::MHU, gem5::MmDisk, gem5::MmioVirtIO, gem5::NoMaliGpu, gem5::NSGigE, gem5::PciVirtIO, gem5::Pl011, gem5::PL031, gem5::Pl050, gem5::Pl111, gem5::Plic, gem5::PM4PacketProcessor, gem5::qemu::FwCfgIo, gem5::qemu::FwCfgMmio, gem5::RealViewCtrl, gem5::RiscvISA::MmioVirtIO, gem5::SDMAEngine, gem5::SimpleUart, gem5::sinic::Device, gem5::Sp804, gem5::Sp805, gem5::SysSecCtrl, gem5::TesterDma, gem5::Uart8250, gem5::UFSHostDevice, gem5::VGic, gem5::X86ISA::Cmos, gem5::X86ISA::I8042, gem5::X86ISA::I82094AA, gem5::X86ISA::I8237, gem5::X86ISA::I8254, gem5::X86ISA::I8259, and gem5::X86ISA::Speaker.
Referenced by gem5::AMDGPUDevice::AMDGPUDevice().
Pure virtual function that the device must implement.
Called when a write command is recieved by the port.
pkt | Packet describing this request |
Implemented in gem5::A9SCU, gem5::AmbaFake, gem5::AMDGPUDevice, gem5::AMDGPUInterruptHandler, gem5::AMDGPUSystemHub, gem5::BadDevice, gem5::Clint, gem5::CopyEngine, gem5::CpuLocalTimer, gem5::DumbTOD, gem5::EnergyCtrl, gem5::fastmodel::GIC, gem5::fastmodel::ResetControllerExample, gem5::FVPBasePwrCtrl, gem5::GenericPciHost, gem5::GenericTimerFrame, gem5::GenericTimerMem, gem5::GenericWatchdog, gem5::GicV2, gem5::Gicv2m, gem5::Gicv3, gem5::Gicv3Its, gem5::GPUCommandProcessor, gem5::HDLcd, gem5::I2CBus, gem5::IdeController, gem5::IGbE, gem5::Iob, gem5::IsaFake, gem5::LupioBLK, gem5::LupioIPI, gem5::LupioPIC, gem5::LupioRNG, gem5::LupioRTC, gem5::LupioSYS, gem5::LupioTMR, gem5::LupioTTY, gem5::MaltaCChip, gem5::MaltaIO, gem5::MHU, gem5::MmDisk, gem5::MmioVirtIO, gem5::NoMaliGpu, gem5::NSGigE, gem5::PciVirtIO, gem5::Pl011, gem5::PL031, gem5::Pl050, gem5::Pl111, gem5::Plic, gem5::PM4PacketProcessor, gem5::qemu::FwCfgIo, gem5::qemu::FwCfgMmio, gem5::RealViewCtrl, gem5::RiscvISA::MmioVirtIO, gem5::SDMAEngine, gem5::SimpleUart, gem5::sinic::Device, gem5::Sp804, gem5::Sp805, gem5::SysSecCtrl, gem5::TesterDma, gem5::Uart8250, gem5::UFSHostDevice, gem5::VGic, gem5::X86ISA::Cmos, gem5::X86ISA::I8042, gem5::X86ISA::I82094AA, gem5::X86ISA::I8237, gem5::X86ISA::I8254, gem5::X86ISA::I8259, and gem5::X86ISA::Speaker.
Referenced by gem5::PciDevice::unserialize().
Definition at line 140 of file io_device.hh.
The pioPort that handles the requests for us and provides us requests that it sees.
Definition at line 109 of file io_device.hh.
Referenced by getPort(), init(), gem5::PciDevice::unserialize(), gem5::sinic::Device::unserialize(), and gem5::PciDevice::writeConfig().
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protected |
Definition at line 105 of file io_device.hh.
Referenced by gem5::DmaDevice::cacheBlockSize(), gem5::GicV2::clearInt(), gem5::MaltaCChip::clearIntr(), gem5::HDLcd::cmdDisable(), gem5::HDLcd::cmdEnable(), gem5::GicV2::copyGicState(), gem5::Gicv3::deassertAll(), gem5::Gicv3::deassertInt(), gem5::Pl111::dmaDone(), gem5::HDLcd::drainResume(), gem5::FVPBasePwrCtrl::FVPBasePwrCtrl(), gem5::Iob::generateIpi(), gem5::GicV2::genSwiMask(), gem5::BaseGic::getSystem(), gem5::FVPBasePwrCtrl::getThreadContextByMPID(), gem5::Gicv3::haveAsserted(), gem5::CpuLocalTimer::init(), gem5::Gicv3::init(), gem5::GicV2::postDelayedFiq(), gem5::GicV2::postDelayedInt(), gem5::Gicv3::postInt(), gem5::MaltaCChip::postIntr(), gem5::FVPBasePwrCtrl::powerCoreOn(), gem5::HDLcd::pxlFrameDone(), gem5::HDLcd::pxlVSyncEnd(), gem5::A9SCU::read(), gem5::GicV2::readCpu(), gem5::GicV2::readDistributor(), gem5::Iob::receiveDeviceInterrupt(), gem5::Iob::receiveJBusInterrupt(), gem5::Gicv3Its::runProcess(), gem5::HSAPacketProcessor::sendAgentDispatchCompletionSignal(), gem5::HSAPacketProcessor::sendCompletionSignal(), gem5::CpuLocalTimer::serialize(), gem5::GicV2::softInt(), gem5::FVPBasePwrCtrl::startup(), gem5::GPUCommandProcessor::submitDispatchPkt(), gem5::GPUCommandProcessor::system(), gem5::GPUCommandProcessor::translate(), gem5::HSAPacketProcessor::translate(), gem5::CpuLocalTimer::unserialize(), gem5::GicV2::updateIntState(), gem5::VGic::updateIntState(), gem5::GicV2::updateRunPri(), gem5::GenericTimerMem::validateAccessPerm(), gem5::VGic::VGic(), and gem5::FVPBasePwrCtrl::write().