| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| BaseXBar(const BaseXBarParams &p) | gem5::BaseXBar | protected |
| calcPacketTiming(PacketPtr pkt, Tick header_delay) | gem5::BaseXBar | protected |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| cpuSidePorts | gem5::BaseXBar | protected |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| defaultPortID | gem5::BaseXBar | protected |
| defaultRange | gem5::BaseXBar | protected |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| findPort(AddrRange addr_range, PacketPtr pkt=nullptr) | gem5::BaseXBar | protected |
| findPort(PacketPtr pkt) | gem5::BaseXBar | inlineprotected |
| forwardLatency | gem5::BaseXBar | protected |
| frequency() const | gem5::Clocked | inline |
| frontendLatency | gem5::BaseXBar | protected |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const | gem5::BaseXBar | protected |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::BaseXBar | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| gotAddrRanges | gem5::BaseXBar | protected |
| gotAllAddrRanges | gem5::BaseXBar | protected |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| headerLatency | gem5::BaseXBar | protected |
| init() | gem5::SimObject | virtual |
| initState() | gem5::SimObject | virtual |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memSidePorts | gem5::BaseXBar | protected |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| NoncoherentXBar(const NoncoherentXBarParams &p) | gem5::NoncoherentXBar | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::ClockedObject | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pktCount | gem5::BaseXBar | protected |
| pktSize | gem5::BaseXBar | protected |
| portMap | gem5::BaseXBar | protected |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| recvAtomicBackdoor(PacketPtr pkt, PortID cpu_side_port_id, MemBackdoorPtr *backdoor=nullptr) | gem5::NoncoherentXBar | protected |
| recvFunctional(PacketPtr pkt, PortID cpu_side_port_id) | gem5::NoncoherentXBar | protected |
| recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor) | gem5::NoncoherentXBar | protected |
| recvRangeChange(PortID mem_side_port_id) | gem5::BaseXBar | protectedvirtual |
| recvReqRetry(PortID mem_side_port_id) | gem5::NoncoherentXBar | protected |
| recvTimingReq(PacketPtr pkt, PortID cpu_side_port_id) | gem5::NoncoherentXBar | protectedvirtual |
| recvTimingResp(PacketPtr pkt, PortID mem_side_port_id) | gem5::NoncoherentXBar | protectedvirtual |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() override | gem5::BaseXBar | virtual |
| reqLayers | gem5::NoncoherentXBar | protected |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| respLayers | gem5::NoncoherentXBar | protected |
| responseLatency | gem5::BaseXBar | protected |
| routeTo | gem5::BaseXBar | protected |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| transDist | gem5::BaseXBar | protected |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| useDefaultRange | gem5::BaseXBar | protected |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| width | gem5::BaseXBar | protected |
| xbarRanges | gem5::BaseXBar | protected |
| ~BaseXBar() | gem5::BaseXBar | virtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~NoncoherentXBar() | gem5::NoncoherentXBar | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |