| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| cacheBlockSize() const | gem5::DmaDevice | inline |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| decodeHeader(PM4Queue *q, PM4Header header) | gem5::PM4PacketProcessor | |
| decodeNext(PM4Queue *q) | gem5::PM4PacketProcessor | |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| DmaDevice(const Params &p) | gem5::DmaDevice | |
| DmaFnPtr typedef | gem5::DmaVirtDevice | |
| dmaPending() const | gem5::DmaDevice | inline |
| dmaPort | gem5::DmaDevice | protected |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaReadVirt(Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmaVirt(DmaFnPtr dmaFn, Addr host_addr, unsigned size, DmaCallback *cb, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| DmaVirtDevice(const Params &p) | gem5::DmaVirtDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) | gem5::DmaDevice | inline |
| dmaWriteVirt(Addr host_addr, unsigned size, DmaCallback *b, void *data, Tick delay=0) | gem5::DmaVirtDevice | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doneMQDWrite(Addr mqdAddr, Addr addr) | gem5::PM4PacketProcessor | |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::PM4PacketProcessor | virtual |
| getGARTAddr(Addr addr) const | gem5::PM4PacketProcessor | |
| getKiqDoorbellOffset() | gem5::PM4PacketProcessor | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::DmaDevice | virtual |
| getPqDoorbellOffset() | gem5::PM4PacketProcessor | inline |
| getProbeManager() | gem5::SimObject | |
| getQueue(Addr offset, bool gfx=false) | gem5::PM4PacketProcessor | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| gpuDevice | gem5::PM4PacketProcessor | private |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| indirectBuffer(PM4Queue *q, PM4IndirectBuf *pkt) | gem5::PM4PacketProcessor | |
| init() override | gem5::DmaDevice | virtual |
| initState() | gem5::SimObject | virtual |
| kiq | gem5::PM4PacketProcessor | private |
| kiq_pkt | gem5::PM4PacketProcessor | private |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| mapKiq(Addr offset) | gem5::PM4PacketProcessor | |
| mapPq(Addr offset) | gem5::PM4PacketProcessor | |
| mapProcess(PM4Queue *q, PM4MapProcess *pkt) | gem5::PM4PacketProcessor | |
| mapQueues(PM4Queue *q, PM4MapQueues *pkt) | gem5::PM4PacketProcessor | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| newQueue(QueueDesc *q, Addr offset, PM4MapQueues *pkt=nullptr, int id=-1) | gem5::PM4PacketProcessor | |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::DmaDevice | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| PM4PacketProcessor(const PM4PacketProcessorParams &p) | gem5::PM4PacketProcessor | |
| powerState | gem5::ClockedObject | |
| pq | gem5::PM4PacketProcessor | private |
| pq_pkt | gem5::PM4PacketProcessor | private |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| process(PM4Queue *q, Addr wptrOffset) | gem5::PM4PacketProcessor | |
| processMQD(PM4MapQueues *pkt, PM4Queue *q, Addr addr, QueueDesc *mqd, uint16_t vmid) | gem5::PM4PacketProcessor | |
| processSDMAMQD(PM4MapQueues *pkt, PM4Queue *q, Addr addr, SDMAQueueDesc *mqd, uint16_t vmid) | gem5::PM4PacketProcessor | |
| queryStatus(PM4Queue *q, PM4QueryStatus *pkt) | gem5::PM4PacketProcessor | |
| queryStatusDone(PM4Queue *q, PM4QueryStatus *pkt) | gem5::PM4PacketProcessor | |
| queues | gem5::PM4PacketProcessor | private |
| queuesMap | gem5::PM4PacketProcessor | private |
| read(PacketPtr pkt) override | gem5::PM4PacketProcessor | inlinevirtual |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| releaseMem(PM4Queue *q, PM4ReleaseMem *pkt) | gem5::PM4PacketProcessor | |
| releaseMemDone(PM4Queue *q, PM4ReleaseMem *pkt, Addr addr) | gem5::PM4PacketProcessor | |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| runList(PM4Queue *q, PM4RunList *pkt) | gem5::PM4PacketProcessor | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::PM4PacketProcessor | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setGPUDevice(AMDGPUDevice *gpu_device) | gem5::PM4PacketProcessor | |
| setHqdActive(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdIbCtrl(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqBase(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqBaseHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqControl(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqDoorbellCtrl(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqPtr(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqRptrReportAddr(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqRptrReportAddrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqWptrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqWptrLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqWptrPollAddr(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdPqWptrPollAddrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setHqdVmid(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbBaseHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbBaseLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbCntl(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbDoorbellCntrl(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbDoorbellRangeHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbDoorbellRangeLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbRptrAddrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbRptrAddrLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbVmid(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbWptrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbWptrLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbWptrPollAddrHi(uint32_t data) | gem5::PM4PacketProcessor | |
| setRbWptrPollAddrLo(uint32_t data) | gem5::PM4PacketProcessor | |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setUconfigReg(PM4Queue *q, PM4SetUconfigReg *pkt) | gem5::PM4PacketProcessor | |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| simObjectList | gem5::SimObject | privatestatic |
| SimObjectList typedef | gem5::SimObject | private |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| switchBuffer(PM4Queue *q, PM4SwitchBuf *pkt) | gem5::PM4PacketProcessor | |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| translate(Addr vaddr, Addr size) override | gem5::PM4PacketProcessor | virtual |
| unmapQueues(PM4Queue *q, PM4UnmapQueues *pkt) | gem5::PM4PacketProcessor | |
| unserialize(CheckpointIn &cp) override | gem5::PM4PacketProcessor | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateReadIndex(Addr offset, uint64_t rd_idx) | gem5::PM4PacketProcessor | |
| voltage() const | gem5::Clocked | inline |
| waitRegMem(PM4Queue *q, PM4WaitRegMem *pkt) | gem5::PM4PacketProcessor | |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| write(PacketPtr pkt) override | gem5::PM4PacketProcessor | inlinevirtual |
| writeData(PM4Queue *q, PM4WriteData *pkt) | gem5::PM4PacketProcessor | |
| writeDataDone(PM4Queue *q, PM4WriteData *pkt, Addr addr) | gem5::PM4PacketProcessor | |
| writeMMIO(PacketPtr pkt, Addr mmio_offset) | gem5::PM4PacketProcessor | |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~DmaDevice()=default | gem5::DmaDevice | virtual |
| ~DmaVirtDevice() | gem5::DmaVirtDevice | inlinevirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |