| _activeCus | gem5::Shader | private |
| _dispatcher | gem5::Shader | |
| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _gpuVmApe | gem5::Shader | private |
| _lastInactiveTick | gem5::Shader | private |
| _ldsApe | gem5::Shader | private |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _scratchApe | gem5::Shader | private |
| AccessMem(uint64_t address, void *ptr, uint32_t size, int cu_id, MemCmd cmd, bool suppress_func_errors) | gem5::Shader | |
| addDeferredDispatch(void *raw_pkt, uint32_t queue_id, Addr host_pkt_addr) | gem5::Shader | |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| blitKernel | gem5::Shader | private |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| coissue_return | gem5::Shader | |
| cpuPointer | gem5::Shader | |
| cpuThread | gem5::Shader | |
| cuList | gem5::Shader | |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| decNumOutstandingInvL2s() | gem5::Shader | |
| deferred_dispatches | gem5::Shader | private |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dispatcher() | gem5::Shader | |
| dispatchWorkgroups(HSAQueueEntry *task) | gem5::Shader | |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doFunctionalAccess(const RequestPtr &req, MemCmd cmd, void *data, bool suppress_func_errors, int cu_id) | gem5::Shader | |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| execScheduledAdds() | gem5::Shader | |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| functionalTLBAccess(PacketPtr pkt, int cu_id, BaseMMU::Mode mode) | gem5::Shader | |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getHiddenPrivateBase() | gem5::Shader | inline |
| getHwReg(int regIdx) | gem5::Shader | inline |
| getNumOutstandingInvL2s() const | gem5::Shader | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getScratchBase() | gem5::Shader | inline |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| globalMemSize | gem5::Shader | |
| gpuCmdProc | gem5::Shader | |
| gpuTc | gem5::Shader | |
| gpuVmApe() const | gem5::Shader | inline |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| hsail_mode | gem5::Shader | |
| hsail_mode_e enum name | gem5::Shader | |
| hwRegs | gem5::Shader | private |
| impl_kern_end_rel | gem5::Shader | |
| impl_kern_launch_acq | gem5::Shader | |
| incNumOutstandingInvL2s() | gem5::Shader | inline |
| incVectorInstDstOperand(int num_operands) | gem5::Shader | inline |
| incVectorInstSrcOperand(int num_operands) | gem5::Shader | inline |
| init() | gem5::Shader | virtual |
| initShHiddenPrivateBase(Addr queueBase, uint32_t offset) | gem5::Shader | inline |
| initState() | gem5::SimObject | virtual |
| isGpuVmApe(Addr addr) const | gem5::Shader | inline |
| isLdsApe(Addr addr) const | gem5::Shader | inline |
| isScratchApe(Addr addr) const | gem5::Shader | inline |
| kernelExitRequested | gem5::Shader | private |
| ldsApe() const | gem5::Shader | inline |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| max_valu_insts | gem5::Shader | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| mmap(int length) | gem5::Shader | |
| n_cu | gem5::Shader | |
| n_cu_per_sqc | gem5::Shader | |
| n_wf | gem5::Shader | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| nextSchedCu | gem5::Shader | |
| notifyCuSleep() | gem5::Shader | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| num_outstanding_invl2s | gem5::Shader | private |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| Params typedef | gem5::Shader | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| prepareFlush(GPUDynInstPtr gpuDynInst) | gem5::Shader | |
| prepareInvalidate(HSAQueueEntry *task) | gem5::Shader | |
| probeManager | gem5::SimObject | private |
| processTimingPacket(PacketPtr pkt) | gem5::Shader | |
| ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id) | gem5::Shader | |
| ReadMem(uint64_t address, void *ptr, uint32_t sz, int cu_id, bool suppress_func_errors) | gem5::Shader | |
| registerCU(int cu_id, ComputeUnit *compute_unit) | gem5::Shader | inline |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| requestKernelExitEvent(bool is_blit_kernel) | gem5::Shader | inline |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| sa_n | gem5::Shader | |
| sa_val | gem5::Shader | |
| sa_when | gem5::Shader | |
| sa_x | gem5::Shader | |
| sampleInstRoundTrip(std::vector< Tick > roundTripTime) | gem5::Shader | |
| sampleLineRoundTrip(const std::map< Addr, std::vector< Tick > > &roundTripTime) | gem5::Shader | |
| sampleLoad(const Tick accessTime) | gem5::Shader | |
| sampleStore(const Tick accessTime) | gem5::Shader | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| ScheduleAdd(int *val, Tick when, int x) | gem5::Shader | |
| scratchApe() const | gem5::Shader | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setHwReg(int regIdx, uint32_t val) | gem5::Shader | inline |
| setLdsApe(Addr base, Addr limit) | gem5::Shader | inline |
| setScratchApe(Addr base, Addr limit) | gem5::Shader | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| Shader(const Params &p) | gem5::Shader | |
| shHiddenPrivateBaseVmid | gem5::Shader | private |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| SIMT enum value | gem5::Shader | |
| startup() | gem5::SimObject | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::Shader | protected |
| systemHub | gem5::Shader | |
| tick | gem5::Clocked | mutableprivate |
| tickEvent | gem5::Shader | |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| timingSim | gem5::Shader | |
| total_valu_insts | gem5::Shader | |
| trace_vgpr_all | gem5::Shader | |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateContext(int cid) | gem5::Shader | |
| VECTOR_SCALAR enum value | gem5::Shader | |
| voltage() const | gem5::Clocked | inline |
| vramRequestorId() | gem5::Shader | |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id) | gem5::Shader | |
| WriteMem(uint64_t address, void *ptr, uint32_t sz, int cu_id, bool suppress_func_errors) | gem5::Shader | |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~Shader() | gem5::Shader | |
| ~SimObject() | gem5::SimObject | virtual |