| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| AckCtl | gem5::VGic | private |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| BitUnion32(ListReg) Bitfield< 31 > HW | gem5::VGic | private |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| CPBR | gem5::VGic | private |
| CpuID | gem5::VGic | private |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| En | gem5::VGic | private |
| EndBitUnion(ListReg) BitUnion32(HCR) Bitfield< 31 | gem5::VGic | private |
| EndBitUnion(HCR) BitUnion32(VCTLR) Bitfield< 9 > EOImode | gem5::VGic | private |
| EnGrp1 | gem5::VGic | private |
| EOI | gem5::VGic | private |
| EOICount | gem5::VGic | private |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| findHighestPendingLR(struct vcpuIntData *vid) | gem5::VGic | inlineprivate |
| findLRForVIRQ(struct vcpuIntData *vid, int virq, int vcpu) | gem5::VGic | inlineprivate |
| FIQEn | gem5::VGic | private |
| frequency() const | gem5::Clocked | inline |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRanges() const override | gem5::VGic | virtual |
| getMISR(struct vcpuIntData *vid) | gem5::VGic | private |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) override | gem5::PioDevice | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| gic | gem5::VGic | private |
| GICH_APR0 | gem5::VGic | privatestatic |
| GICH_EISR0 | gem5::VGic | privatestatic |
| GICH_EISR1 | gem5::VGic | privatestatic |
| GICH_ELSR0 | gem5::VGic | privatestatic |
| GICH_ELSR1 | gem5::VGic | privatestatic |
| GICH_HCR | gem5::VGic | privatestatic |
| GICH_LR0 | gem5::VGic | privatestatic |
| GICH_LR1 | gem5::VGic | privatestatic |
| GICH_LR2 | gem5::VGic | privatestatic |
| GICH_LR3 | gem5::VGic | privatestatic |
| GICH_MISR | gem5::VGic | privatestatic |
| GICH_REG_SIZE | gem5::VGic | privatestatic |
| GICH_SIZE | gem5::VGic | privatestatic |
| GICH_VMCR | gem5::VGic | privatestatic |
| GICH_VTR | gem5::VGic | privatestatic |
| GICV_ABPR | gem5::VGic | privatestatic |
| GICV_AEOIR | gem5::VGic | privatestatic |
| GICV_AHPPIR | gem5::VGic | privatestatic |
| GICV_AIAR | gem5::VGic | privatestatic |
| GICV_APR0 | gem5::VGic | privatestatic |
| GICV_BPR | gem5::VGic | privatestatic |
| GICV_CTLR | gem5::VGic | privatestatic |
| GICV_DIR | gem5::VGic | privatestatic |
| GICV_EOIR | gem5::VGic | privatestatic |
| GICV_HPPIR | gem5::VGic | privatestatic |
| GICV_IAR | gem5::VGic | privatestatic |
| GICV_IIDR | gem5::VGic | privatestatic |
| GICV_PMR | gem5::VGic | privatestatic |
| GICV_RPR | gem5::VGic | privatestatic |
| GICV_SIZE | gem5::VGic | privatestatic |
| gicvIIDR | gem5::VGic | private |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| Grp1 | gem5::VGic | private |
| hvAddr | gem5::VGic | private |
| init() override | gem5::PioDevice | virtual |
| initState() | gem5::SimObject | virtual |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| LR_ACTIVE | gem5::VGic | privatestatic |
| LR_PENDING | gem5::VGic | privatestatic |
| LRENPIE | gem5::VGic | private |
| lrPending(struct vcpuIntData *vid) | gem5::VGic | inlineprivate |
| lrValid(struct vcpuIntData *vid) | gem5::VGic | inlineprivate |
| maintInt | gem5::VGic | private |
| maintIntPosted | gem5::VGic | private |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextCycle() const | gem5::Clocked | inline |
| notifyFork() | gem5::Drainable | inlinevirtual |
| NPIE | gem5::VGic | private |
| NUM_LR | gem5::VGic | privatestatic |
| gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
| params() const | gem5::SimObject | inline |
| Params typedef | gem5::VGic | |
| path | gem5::Serializable | privatestatic |
| pioDelay | gem5::VGic | private |
| PioDevice(const Params &p) | gem5::PioDevice | |
| pioPort | gem5::PioDevice | protected |
| platform | gem5::VGic | private |
| postMaintInt(uint32_t cpu) | gem5::VGic | private |
| postVInt(uint32_t cpu, Tick when) | gem5::VGic | private |
| postVIntEvent | gem5::VGic | private |
| powerState | gem5::ClockedObject | |
| preDumpStats() | gem5::statistics::Group | virtual |
| Priority | gem5::VGic | private |
| probeManager | gem5::SimObject | private |
| processPostVIntEvent(uint32_t cpu) | gem5::VGic | private |
| read(PacketPtr pkt) override | gem5::VGic | virtual |
| readCtrl(PacketPtr pkt) | gem5::VGic | private |
| readVCpu(PacketPtr pkt) | gem5::VGic | private |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::VGic | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| startup() | gem5::SimObject | virtual |
| State | gem5::VGic | private |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::statistics::Group | private |
| sys | gem5::PioDevice | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| UIE | gem5::VGic | private |
| unPostMaintInt(uint32_t cpu) | gem5::VGic | private |
| unPostVInt(uint32_t cpu) | gem5::VGic | private |
| unserialize(CheckpointIn &cp) override | gem5::VGic | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| updateIntState(ContextID ctx_id) | gem5::VGic | private |
| vcpuAddr | gem5::VGic | private |
| vcpuData | gem5::VGic | private |
| VGic(const Params &p) | gem5::VGic | |
| VGIC_CPU_MAX | gem5::VGic | privatestatic |
| VGrp0DIE | gem5::VGic | private |
| VGrp0EIE | gem5::VGic | private |
| VGrp1DIE | gem5::VGic | private |
| VGrp1EIE | gem5::VGic | private |
| vIntPosted | gem5::VGic | private |
| VirtualID | gem5::VGic | private |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| write(PacketPtr pkt) override | gem5::VGic | virtual |
| writeCtrl(PacketPtr pkt) | gem5::VGic | private |
| writeVCpu(PacketPtr pkt) | gem5::VGic | private |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~PioDevice() | gem5::PioDevice | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |
| ~VGic() | gem5::VGic | |