_drainManager | gem5::Drainable | private |
_drainState | gem5::Drainable | mutableprivate |
_name | gem5::Named | private |
_objNameResolver | gem5::SimObject | privatestatic |
_params | gem5::SimObject | protected |
addEventProbe(SimObject *obj, const char *name) | gem5::prefetch::Base | |
addMMU(BaseMMU *mmu) | gem5::prefetch::Base | |
AddrPriority typedef | gem5::prefetch::Queued | |
addStat(statistics::Info *info) | gem5::statistics::Group | |
addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
addToQueue(std::list< DeferredPacket > &queue, DeferredPacket &dpp) | gem5::prefetch::Queued | private |
alreadyInQueue(std::list< DeferredPacket > &queue, const PrefetchInfo &pfi, int32_t priority) | gem5::prefetch::Queued | private |
Base(const BasePrefetcherParams &p) | gem5::prefetch::Base | |
blkSize | gem5::prefetch::Base | protected |
blockAddress(Addr a) const | gem5::prefetch::Base | protected |
blockIndex(Addr a) const | gem5::prefetch::Base | protected |
cacheSnoop | gem5::prefetch::Queued | protected |
calculatePrefetch(const PrefetchInfo &pfi, std::vector< AddrPriority > &addresses, const CacheAccessor &cache) override | gem5::prefetch::DCPT | virtual |
clockDomain | gem5::Clocked | private |
Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
Clocked(Clocked &)=delete | gem5::Clocked | protected |
clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
clockPeriod() const | gem5::Clocked | inline |
clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
const_iterator typedef | gem5::prefetch::Queued | protected |
createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt) | gem5::prefetch::Queued | private |
curCycle() const | gem5::Clocked | inline |
currentSection() | gem5::Serializable | static |
cycle | gem5::Clocked | mutableprivate |
cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
DCPT(const DCPTPrefetcherParams &p) | gem5::prefetch::DCPT | |
dcpt | gem5::prefetch::DCPT | private |
deschedule(Event &event) | gem5::EventManager | inline |
deschedule(Event *event) | gem5::EventManager | inline |
dmDrain() | gem5::Drainable | private |
dmDrainResume() | gem5::Drainable | private |
drain() override | gem5::SimObject | inlinevirtual |
Drainable() | gem5::Drainable | protected |
drainResume() | gem5::Drainable | inlineprotectedvirtual |
drainState() const | gem5::Drainable | inline |
EventManager(EventManager &em) | gem5::EventManager | inline |
EventManager(EventManager *em) | gem5::EventManager | inline |
EventManager(EventQueue *eq) | gem5::EventManager | inline |
eventq | gem5::EventManager | protected |
eventQueue() const | gem5::EventManager | inline |
EvictionInfo typedef | gem5::prefetch::Base | private |
find(const char *name) | gem5::SimObject | static |
frequency() const | gem5::Clocked | inline |
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
getMaxPermittedPrefetches(size_t total) const | gem5::prefetch::Queued | private |
getPacket() override | gem5::prefetch::Queued | virtual |
getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
getProbeManager() | gem5::SimObject | |
getSimObjectResolver() | gem5::SimObject | static |
getStatGroups() const | gem5::statistics::Group | |
getStats() const | gem5::statistics::Group | |
Group()=delete | gem5::statistics::Group | |
Group(const Group &)=delete | gem5::statistics::Group | |
Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
incrDemandMhsrMisses() | gem5::prefetch::Base | inline |
init() | gem5::SimObject | virtual |
initState() | gem5::SimObject | virtual |
insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority, const CacheAccessor &cache) | gem5::prefetch::Queued | |
issuedPrefetches | gem5::prefetch::Base | protected |
iterator typedef | gem5::prefetch::Queued | protected |
latency | gem5::prefetch::Queued | protected |
lBlkSize | gem5::prefetch::Base | protected |
listeners | gem5::prefetch::Base | private |
loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
memInvalidate() | gem5::SimObject | inlinevirtual |
memWriteback() | gem5::SimObject | inlinevirtual |
mergedParent | gem5::statistics::Group | private |
mergedStatGroups | gem5::statistics::Group | private |
mergeStatGroup(Group *block) | gem5::statistics::Group | |
missingTranslationQueueSize | gem5::prefetch::Queued | protected |
mmu | gem5::prefetch::Base | protected |
name() const | gem5::Named | inlinevirtual |
Named(const std::string &name_) | gem5::Named | inline |
nextCycle() const | gem5::Clocked | inline |
nextPrefetchReadyTime() const override | gem5::prefetch::Queued | inlinevirtual |
notify(const CacheAccessProbeArg &acc, const PrefetchInfo &pfi) override | gem5::prefetch::Queued | virtual |
notifyEvict(const EvictionInfo &info) | gem5::prefetch::Base | inlinevirtual |
notifyFill(const CacheAccessProbeArg &acc) | gem5::prefetch::Base | inlinevirtual |
notifyFork() | gem5::Drainable | inlinevirtual |
observeAccess(const PacketPtr &pkt, bool miss, bool prefetched) const | gem5::prefetch::Base | protected |
onData | gem5::prefetch::Base | protected |
onInst | gem5::prefetch::Base | protected |
onMiss | gem5::prefetch::Base | protected |
onRead | gem5::prefetch::Base | protected |
onWrite | gem5::prefetch::Base | protected |
gem5::operator=(const Group &)=delete | gem5::statistics::Group | |
gem5::Clocked::operator=(Clocked &)=delete | gem5::Clocked | protected |
pageAddress(Addr a) const | gem5::prefetch::Base | protected |
pageBytes | gem5::prefetch::Base | protected |
pageIthBlockAddress(Addr page, uint32_t i) const | gem5::prefetch::Base | protected |
pageOffset(Addr a) const | gem5::prefetch::Base | protected |
Params typedef | gem5::ClockedObject | |
params() const | gem5::SimObject | inline |
path | gem5::Serializable | privatestatic |
pfHitInCache() | gem5::prefetch::Base | inline |
pfHitInMSHR() | gem5::prefetch::Base | inline |
pfHitInWB() | gem5::prefetch::Base | inline |
pfq | gem5::prefetch::Queued | protected |
pfqMissingTranslation | gem5::prefetch::Queued | protected |
powerState | gem5::ClockedObject | |
preDumpStats() | gem5::statistics::Group | virtual |
prefetchOnAccess | gem5::prefetch::Base | protected |
prefetchOnPfHit | gem5::prefetch::Base | protected |
prefetchStats | gem5::prefetch::Base | protected |
prefetchUnused() | gem5::prefetch::Base | inline |
printQueue(const std::list< DeferredPacket > &queue) const | gem5::prefetch::Queued | |
probeManager | gem5::prefetch::Base | protected |
probeNotify(const CacheAccessProbeArg &acc, bool miss) | gem5::prefetch::Base | |
processMissingTranslations(unsigned max) | gem5::prefetch::Queued | private |
Queued(const QueuedPrefetcherParams &p) | gem5::prefetch::Queued | |
queueFilter | gem5::prefetch::Queued | protected |
queueSize | gem5::prefetch::Queued | protected |
queueSquash | gem5::prefetch::Queued | protected |
regProbeListeners() override | gem5::prefetch::Base | virtual |
regProbePoints() | gem5::SimObject | virtual |
regStats() | gem5::statistics::Group | virtual |
requestorId | gem5::prefetch::Base | protected |
reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
resetClock() const | gem5::Clocked | inlineprotected |
resetStats() | gem5::statistics::Group | virtual |
resolveStat(std::string name) const | gem5::statistics::Group | |
samePage(Addr a, Addr b) const | gem5::prefetch::Base | protected |
schedule(Event &event, Tick when) | gem5::EventManager | inline |
schedule(Event *event, Tick when) | gem5::EventManager | inline |
Serializable() | gem5::Serializable | |
serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
setCurTick(Tick newVal) | gem5::EventManager | inline |
setParentInfo(System *sys, ProbeManager *pm, unsigned blk_size) | gem5::prefetch::Base | virtual |
setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
signalDrainDone() const | gem5::Drainable | inlineprotected |
SimObject(const Params &p) | gem5::SimObject | |
SimObjectList typedef | gem5::SimObject | private |
simObjectList | gem5::SimObject | privatestatic |
startup() | gem5::SimObject | virtual |
statGroups | gem5::statistics::Group | private |
stats | gem5::statistics::Group | private |
statsQueued | gem5::prefetch::Queued | protected |
system | gem5::prefetch::Base | protected |
tagPrefetch | gem5::prefetch::Queued | protected |
throttleControlPct | gem5::prefetch::Queued | protected |
tick | gem5::Clocked | mutableprivate |
ticksToCycles(Tick t) const | gem5::Clocked | inline |
translationComplete(DeferredPacket *dp, bool failed, const CacheAccessor &cache) | gem5::prefetch::Queued | private |
unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
update() const | gem5::Clocked | inlineprivate |
updateClockPeriod() | gem5::Clocked | inline |
usefulPrefetches | gem5::prefetch::Base | protected |
useVirtualAddresses | gem5::prefetch::Base | protected |
voltage() const | gem5::Clocked | inline |
wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
~Base()=default | gem5::prefetch::Base | virtual |
~Clocked() | gem5::Clocked | inlineprotectedvirtual |
~DCPT()=default | gem5::prefetch::DCPT | |
~Drainable() | gem5::Drainable | protectedvirtual |
~Group() | gem5::statistics::Group | virtual |
~Named()=default | gem5::Named | virtual |
~Queued() | gem5::prefetch::Queued | virtual |
~Serializable() | gem5::Serializable | virtual |
~SimObject() | gem5::SimObject | virtual |