gem5 v24.0.0.0
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copy_engine_defs.hh File Reference
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Classes

struct  gem5::copy_engine_reg::DmaDesc
 
struct  gem5::copy_engine_reg::Reg< T >
 
struct  gem5::copy_engine_reg::Regs
 
struct  gem5::copy_engine_reg::Regs::INTRCTRL
 
struct  gem5::copy_engine_reg::ChanRegs
 
struct  gem5::copy_engine_reg::ChanRegs::CHANCTRL
 
struct  gem5::copy_engine_reg::ChanRegs::CHANSTS
 
struct  gem5::copy_engine_reg::ChanRegs::CHANCMD
 
struct  gem5::copy_engine_reg::ChanRegs::CHANERR
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::copy_engine_reg
 

Macros

#define ADD_FIELD8(NAME, OFFSET, BITS)
 
#define ADD_FIELD16(NAME, OFFSET, BITS)
 
#define ADD_FIELD32(NAME, OFFSET, BITS)
 
#define ADD_FIELD64(NAME, OFFSET, BITS)
 

Variables

const uint32_t gem5::copy_engine_reg::GEN_CHANCOUNT = 0x00
 
const uint32_t gem5::copy_engine_reg::GEN_XFERCAP = 0x01
 
const uint32_t gem5::copy_engine_reg::GEN_INTRCTRL = 0x03
 
const uint32_t gem5::copy_engine_reg::GEN_ATTNSTATUS = 0x04
 
const uint32_t gem5::copy_engine_reg::CHAN_CONTROL = 0x00
 
const uint32_t gem5::copy_engine_reg::CHAN_STATUS = 0x04
 
const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR = 0x0C
 
const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR_LOW = 0x0C
 
const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR_HIGH = 0x10
 
const uint32_t gem5::copy_engine_reg::CHAN_COMMAND = 0x14
 
const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR = 0x18
 
const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR_LOW = 0x18
 
const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR_HIGH = 0x1C
 
const uint32_t gem5::copy_engine_reg::CHAN_ERROR = 0x28
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_INT_GEN = 0x00000001
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_SRC_SN = 0x00000002
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_DST_SN = 0x00000004
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_CP_STS = 0x00000008
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_FRAME = 0x00000010
 
const uint32_t gem5::copy_engine_reg::DESC_CTRL_NULL = 0x00000020
 

Macro Definition Documentation

◆ ADD_FIELD16

#define ADD_FIELD16 ( NAME,
OFFSET,
BITS )
Value:
inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint16_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 86 of file copy_engine_defs.hh.

◆ ADD_FIELD32

#define ADD_FIELD32 ( NAME,
OFFSET,
BITS )
Value:
inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 90 of file copy_engine_defs.hh.

◆ ADD_FIELD64

#define ADD_FIELD64 ( NAME,
OFFSET,
BITS )
Value:
inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 94 of file copy_engine_defs.hh.

◆ ADD_FIELD8

#define ADD_FIELD8 ( NAME,
OFFSET,
BITS )
Value:
inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
inline void NAME(uint8_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }

Definition at line 82 of file copy_engine_defs.hh.


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