gem5  v22.0.0.2
comm.hh
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41 
42 #ifndef __CPU_O3_COMM_HH__
43 #define __CPU_O3_COMM_HH__
44 
45 #include <vector>
46 
47 #include "arch/generic/pcstate.hh"
48 #include "base/types.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/inst_seq.hh"
51 #include "cpu/o3/dyn_inst_ptr.hh"
52 #include "cpu/o3/limits.hh"
53 #include "sim/faults.hh"
54 
55 namespace gem5
56 {
57 
58 namespace o3
59 {
60 
63 {
64  int size;
65 
70 };
71 
74 {
75  int size;
76 
78 };
79 
82 {
83  int size;
84 
86 };
87 
89 struct IEWStruct
90 {
91  int size;
92 
97  std::unique_ptr<PCStateBase> pc[MaxThreads];
98 
103 };
104 
106 {
107  int size;
108 
110 };
111 
114 {
115  struct DecodeComm
116  {
117  std::unique_ptr<PCStateBase> nextPC;
122  uint64_t branchAddr;
123  unsigned branchCount;
124  bool squash;
128  };
129 
131 
132  struct RenameComm {};
133 
135 
136  struct IewComm
137  {
138  // Also eventually include skid buffer space.
139  unsigned freeIQEntries;
140  unsigned freeLQEntries;
141  unsigned freeSQEntries;
142  unsigned dispatchedToLQ;
143  unsigned dispatchedToSQ;
144 
145  unsigned iqCount;
146  unsigned ldstqCount;
147 
148  unsigned dispatched;
149  bool usedIQ;
150  bool usedLSQ;
151  };
152 
154 
155  struct CommitComm
156  {
158  // This code has been re-structured for better packing of variables
159  // instead of by stage which is the more logical way to arrange the
160  // data.
161  // F = Fetch
162  // D = Decode
163  // I = IEW
164  // R = Rename
165  // As such each member is annotated with who consumes it
166  // e.g. bool variable name // *F,R for Fetch and Rename
168 
172  std::unique_ptr<PCStateBase> pc; // *F
173 
177 
180 
184 
188 
193 
195  unsigned freeROBEntries; // *R
196 
197  bool squash; // *F, D, R, I
198  bool robSquashing; // *F, D, R, I
199 
201  bool usedROB; // *R
202 
204  bool emptyROB; // *R
205 
207  bool branchTaken; // *F
209  bool interruptPending; // *F
211  bool clearInterrupt; // *F
212 
215  bool strictlyOrdered; // *I
216 
217  };
218 
220 
227 };
228 
229 } // namespace o3
230 } // namespace gem5
231 
232 #endif //__CPU_O3_COMM_HH__
gem5::o3::TimeStruct::CommitComm::nonSpecSeqNum
InstSeqNum nonSpecSeqNum
Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instructio...
Definition: comm.hh:187
gem5::o3::TimeStruct::CommitComm::clearInterrupt
bool clearInterrupt
If the interrupt ended up being cleared before being handled.
Definition: comm.hh:211
gem5::o3::TimeStruct::renameUnblock
bool renameUnblock[MaxThreads]
Definition: comm.hh:224
gem5::o3::TimeStruct::CommitComm::strictlyOrdered
bool strictlyOrdered
Hack for now to send back an strictly ordered access to the IEW stage.
Definition: comm.hh:215
gem5::o3::TimeStruct::CommitComm::strictlyOrderedLoad
DynInstPtr strictlyOrderedLoad
Hack for now to send back a strictly ordered access to the IEW stage.
Definition: comm.hh:183
gem5::o3::RenameStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:85
gem5::o3::TimeStruct::DecodeComm::squashInst
DynInstPtr squashInst
Definition: comm.hh:119
gem5::o3::FetchStruct::fetchFault
Fault fetchFault
Definition: comm.hh:67
gem5::o3::IEWStruct::includeSquashInst
bool includeSquashInst[MaxThreads]
Definition: comm.hh:102
gem5::o3::IEWStruct::size
int size
Definition: comm.hh:91
gem5::o3::TimeStruct::DecodeComm::branchTaken
bool branchTaken
Definition: comm.hh:127
gem5::o3::FetchStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:66
gem5::o3::TimeStruct::DecodeComm::mispredictInst
DynInstPtr mispredictInst
Definition: comm.hh:118
gem5::o3::IEWStruct
Struct that defines the information passed from IEW to commit.
Definition: comm.hh:89
gem5::o3::IEWStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:93
gem5::o3::TimeStruct::renameInfo
RenameComm renameInfo[MaxThreads]
Definition: comm.hh:134
gem5::o3::TimeStruct::IewComm::dispatched
unsigned dispatched
Definition: comm.hh:148
gem5::o3::TimeStruct::DecodeComm::branchMispredict
bool branchMispredict
Definition: comm.hh:126
gem5::o3::TimeStruct::IewComm::freeLQEntries
unsigned freeLQEntries
Definition: comm.hh:140
gem5::o3::TimeStruct::CommitComm::squash
bool squash
Definition: comm.hh:197
gem5::o3::TimeStruct::DecodeComm::mispredPC
Addr mispredPC
Definition: comm.hh:121
faults.hh
gem5::o3::TimeStruct::CommitComm::mispredictInst
DynInstPtr mispredictInst
Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.
Definition: comm.hh:176
gem5::o3::TimeStruct::DecodeComm::branchCount
unsigned branchCount
Definition: comm.hh:123
gem5::o3::TimeStruct::IewComm::freeSQEntries
unsigned freeSQEntries
Definition: comm.hh:141
gem5::RefCountingPtr< DynInst >
gem5::o3::TimeStruct::decodeUnblock
bool decodeUnblock[MaxThreads]
Definition: comm.hh:222
gem5::o3::TimeStruct::IewComm::usedIQ
bool usedIQ
Definition: comm.hh:149
gem5::o3::TimeStruct::IewComm::dispatchedToSQ
unsigned dispatchedToSQ
Definition: comm.hh:143
gem5::o3::TimeStruct::iewUnblock
bool iewUnblock[MaxThreads]
Definition: comm.hh:226
gem5::o3::TimeStruct::IewComm::usedLSQ
bool usedLSQ
Definition: comm.hh:150
gem5::o3::TimeStruct::DecodeComm::predIncorrect
bool predIncorrect
Definition: comm.hh:125
gem5::o3::TimeStruct::IewComm::ldstqCount
unsigned ldstqCount
Definition: comm.hh:146
gem5::o3::TimeStruct::IewComm
Definition: comm.hh:136
gem5::o3::IEWStruct::branchTaken
bool branchTaken[MaxThreads]
Definition: comm.hh:101
gem5::o3::TimeStruct::CommitComm::pc
std::unique_ptr< PCStateBase > pc
The pc of the next instruction to execute.
Definition: comm.hh:172
gem5::o3::TimeStruct::IewComm::freeIQEntries
unsigned freeIQEntries
Definition: comm.hh:139
inst_seq.hh
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::o3::IssueStruct::size
int size
Definition: comm.hh:107
gem5::o3::TimeStruct::CommitComm::freeROBEntries
unsigned freeROBEntries
Tell Rename how many free entries it has in the ROB.
Definition: comm.hh:195
gem5::o3::IssueStruct
Definition: comm.hh:105
gem5::o3::FetchStruct
Struct that defines the information passed from fetch to decode.
Definition: comm.hh:62
gem5::o3::TimeStruct::RenameComm
Definition: comm.hh:132
gem5::o3::FetchStruct::clearFetchFault
bool clearFetchFault
Definition: comm.hh:69
gem5::o3::IEWStruct::squashedSeqNum
InstSeqNum squashedSeqNum[MaxThreads]
Definition: comm.hh:96
gem5::o3::TimeStruct
Struct that defines all backwards communication.
Definition: comm.hh:113
gem5::o3::TimeStruct::DecodeComm::doneSeqNum
InstSeqNum doneSeqNum
Definition: comm.hh:120
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
gem5::o3::TimeStruct::DecodeComm::squash
bool squash
Definition: comm.hh:124
gem5::o3::TimeStruct::decodeInfo
DecodeComm decodeInfo[MaxThreads]
Definition: comm.hh:130
gem5::o3::TimeStruct::CommitComm::emptyROB
bool emptyROB
Notify Rename that the ROB is empty.
Definition: comm.hh:204
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::IEWStruct::squash
bool squash[MaxThreads]
Definition: comm.hh:99
dyn_inst_ptr.hh
gem5::o3::TimeStruct::renameBlock
bool renameBlock[MaxThreads]
Definition: comm.hh:223
gem5::o3::TimeStruct::CommitComm::squashInst
DynInstPtr squashInst
Instruction that caused the a non-mispredict squash.
Definition: comm.hh:179
gem5::o3::TimeStruct::DecodeComm::branchAddr
uint64_t branchAddr
Definition: comm.hh:122
gem5::o3::FetchStruct::size
int size
Definition: comm.hh:64
gem5::o3::TimeStruct::IewComm::iqCount
unsigned iqCount
Definition: comm.hh:145
pcstate.hh
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::FetchStruct::fetchFaultSN
InstSeqNum fetchFaultSN
Definition: comm.hh:68
gem5::o3::TimeStruct::CommitComm::branchTaken
bool branchTaken
Was the branch taken or not.
Definition: comm.hh:207
gem5::o3::TimeStruct::CommitComm::interruptPending
bool interruptPending
If an interrupt is pending and fetch should stall.
Definition: comm.hh:209
gem5::o3::IEWStruct::mispredictInst
DynInstPtr mispredictInst[MaxThreads]
Definition: comm.hh:94
types.hh
gem5::o3::DecodeStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:77
gem5::o3::TimeStruct::decodeBlock
bool decodeBlock[MaxThreads]
Definition: comm.hh:221
gem5::o3::TimeStruct::CommitComm
Definition: comm.hh:155
gem5::o3::DecodeStruct::size
int size
Definition: comm.hh:75
gem5::o3::TimeStruct::DecodeComm
Definition: comm.hh:115
gem5::o3::TimeStruct::IewComm::dispatchedToLQ
unsigned dispatchedToLQ
Definition: comm.hh:142
gem5::o3::IEWStruct::pc
std::unique_ptr< PCStateBase > pc[MaxThreads]
Definition: comm.hh:97
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::TimeStruct::CommitComm::usedROB
bool usedROB
Rename should re-read number of free rob entries.
Definition: comm.hh:201
gem5::o3::TimeStruct::iewBlock
bool iewBlock[MaxThreads]
Definition: comm.hh:225
gem5::o3::IEWStruct::branchMispredict
bool branchMispredict[MaxThreads]
Definition: comm.hh:100
gem5::o3::TimeStruct::commitInfo
CommitComm commitInfo[MaxThreads]
Definition: comm.hh:219
gem5::o3::IssueStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:109
gem5::o3::DecodeStruct
Struct that defines the information passed from decode to rename.
Definition: comm.hh:73
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::TimeStruct::CommitComm::robSquashing
bool robSquashing
Definition: comm.hh:198
gem5::o3::TimeStruct::DecodeComm::nextPC
std::unique_ptr< PCStateBase > nextPC
Definition: comm.hh:117
limits.hh
gem5::o3::TimeStruct::CommitComm::doneSeqNum
InstSeqNum doneSeqNum
Represents the instruction that has either been retired or squashed.
Definition: comm.hh:192
gem5::o3::TimeStruct::iewInfo
IewComm iewInfo[MaxThreads]
Definition: comm.hh:153
gem5::o3::RenameStruct::size
int size
Definition: comm.hh:83
gem5::o3::IEWStruct::mispredPC
Addr mispredPC[MaxThreads]
Definition: comm.hh:95
gem5::o3::RenameStruct
Struct that defines the information passed from rename to IEW.
Definition: comm.hh:81

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