gem5  v21.1.0.2
comm.hh
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41 
42 #ifndef __CPU_O3_COMM_HH__
43 #define __CPU_O3_COMM_HH__
44 
45 #include <vector>
46 
47 #include "arch/pcstate.hh"
48 #include "base/types.hh"
49 #include "cpu/inst_seq.hh"
50 #include "cpu/o3/dyn_inst_ptr.hh"
51 #include "cpu/o3/limits.hh"
52 #include "sim/faults.hh"
53 
54 namespace gem5
55 {
56 
57 namespace o3
58 {
59 
62 {
63  int size;
64 
69 };
70 
73 {
74  int size;
75 
77 };
78 
81 {
82  int size;
83 
85 };
86 
88 struct IEWStruct
89 {
90  int size;
91 
97 
102 };
103 
105 {
106  int size;
107 
109 };
110 
113 {
114  struct DecodeComm
115  {
121  uint64_t branchAddr;
122  unsigned branchCount;
123  bool squash;
127  };
128 
130 
131  struct RenameComm {};
132 
134 
135  struct IewComm
136  {
137  // Also eventually include skid buffer space.
138  unsigned freeIQEntries;
139  unsigned freeLQEntries;
140  unsigned freeSQEntries;
141  unsigned dispatchedToLQ;
142  unsigned dispatchedToSQ;
143 
144  unsigned iqCount;
145  unsigned ldstqCount;
146 
147  unsigned dispatched;
148  bool usedIQ;
149  bool usedLSQ;
150  };
151 
153 
154  struct CommitComm
155  {
157  // This code has been re-structured for better packing of variables
158  // instead of by stage which is the more logical way to arrange the
159  // data.
160  // F = Fetch
161  // D = Decode
162  // I = IEW
163  // R = Rename
164  // As such each member is annotated with who consumes it
165  // e.g. bool variable name // *F,R for Fetch and Rename
167 
172 
176 
179 
183 
187 
192 
194  unsigned freeROBEntries; // *R
195 
196  bool squash; // *F, D, R, I
197  bool robSquashing; // *F, D, R, I
198 
200  bool usedROB; // *R
201 
203  bool emptyROB; // *R
204 
206  bool branchTaken; // *F
208  bool interruptPending; // *F
210  bool clearInterrupt; // *F
211 
214  bool strictlyOrdered; // *I
215 
216  };
217 
219 
226 };
227 
228 } // namespace o3
229 } // namespace gem5
230 
231 #endif //__CPU_O3_COMM_HH__
gem5::o3::TimeStruct::CommitComm::nonSpecSeqNum
InstSeqNum nonSpecSeqNum
Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instructio...
Definition: comm.hh:186
gem5::o3::TimeStruct::CommitComm::clearInterrupt
bool clearInterrupt
If the interrupt ended up being cleared before being handled.
Definition: comm.hh:210
gem5::o3::TimeStruct::renameUnblock
bool renameUnblock[MaxThreads]
Definition: comm.hh:223
gem5::o3::TimeStruct::CommitComm::strictlyOrdered
bool strictlyOrdered
Hack for now to send back an strictly ordered access to the IEW stage.
Definition: comm.hh:214
gem5::o3::TimeStruct::CommitComm::strictlyOrderedLoad
DynInstPtr strictlyOrderedLoad
Hack for now to send back a strictly ordered access to the IEW stage.
Definition: comm.hh:182
gem5::o3::RenameStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:84
gem5::o3::TimeStruct::DecodeComm::squashInst
DynInstPtr squashInst
Definition: comm.hh:118
gem5::o3::FetchStruct::fetchFault
Fault fetchFault
Definition: comm.hh:66
gem5::o3::IEWStruct::includeSquashInst
bool includeSquashInst[MaxThreads]
Definition: comm.hh:101
gem5::o3::IEWStruct::size
int size
Definition: comm.hh:90
gem5::o3::TimeStruct::DecodeComm::branchTaken
bool branchTaken
Definition: comm.hh:126
gem5::o3::FetchStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:65
gem5::o3::TimeStruct::DecodeComm::mispredictInst
DynInstPtr mispredictInst
Definition: comm.hh:117
gem5::o3::IEWStruct
Struct that defines the information passed from IEW to commit.
Definition: comm.hh:88
gem5::o3::IEWStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:92
gem5::o3::TimeStruct::renameInfo
RenameComm renameInfo[MaxThreads]
Definition: comm.hh:133
gem5::o3::TimeStruct::IewComm::dispatched
unsigned dispatched
Definition: comm.hh:147
gem5::o3::TimeStruct::DecodeComm::branchMispredict
bool branchMispredict
Definition: comm.hh:125
gem5::o3::TimeStruct::IewComm::freeLQEntries
unsigned freeLQEntries
Definition: comm.hh:139
gem5::o3::TimeStruct::CommitComm::squash
bool squash
Definition: comm.hh:196
gem5::o3::TimeStruct::DecodeComm::mispredPC
Addr mispredPC
Definition: comm.hh:120
faults.hh
gem5::o3::TimeStruct::CommitComm::mispredictInst
DynInstPtr mispredictInst
Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.
Definition: comm.hh:175
gem5::o3::TimeStruct::DecodeComm::branchCount
unsigned branchCount
Definition: comm.hh:122
gem5::o3::TimeStruct::IewComm::freeSQEntries
unsigned freeSQEntries
Definition: comm.hh:140
gem5::RefCountingPtr< DynInst >
gem5::o3::TimeStruct::decodeUnblock
bool decodeUnblock[MaxThreads]
Definition: comm.hh:221
gem5::o3::TimeStruct::IewComm::usedIQ
bool usedIQ
Definition: comm.hh:148
gem5::o3::TimeStruct::IewComm::dispatchedToSQ
unsigned dispatchedToSQ
Definition: comm.hh:142
gem5::o3::TimeStruct::iewUnblock
bool iewUnblock[MaxThreads]
Definition: comm.hh:225
gem5::o3::TimeStruct::IewComm::usedLSQ
bool usedLSQ
Definition: comm.hh:149
gem5::o3::TimeStruct::DecodeComm::predIncorrect
bool predIncorrect
Definition: comm.hh:124
gem5::o3::TimeStruct::IewComm::ldstqCount
unsigned ldstqCount
Definition: comm.hh:145
gem5::o3::TimeStruct::IewComm
Definition: comm.hh:135
gem5::o3::IEWStruct::branchTaken
bool branchTaken[MaxThreads]
Definition: comm.hh:100
gem5::o3::TimeStruct::IewComm::freeIQEntries
unsigned freeIQEntries
Definition: comm.hh:138
inst_seq.hh
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::IssueStruct::size
int size
Definition: comm.hh:106
gem5::o3::TimeStruct::CommitComm::freeROBEntries
unsigned freeROBEntries
Tell Rename how many free entries it has in the ROB.
Definition: comm.hh:194
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::o3::IssueStruct
Definition: comm.hh:104
gem5::o3::FetchStruct
Struct that defines the information passed from fetch to decode.
Definition: comm.hh:61
gem5::o3::TimeStruct::RenameComm
Definition: comm.hh:131
gem5::o3::FetchStruct::clearFetchFault
bool clearFetchFault
Definition: comm.hh:68
gem5::o3::IEWStruct::squashedSeqNum
InstSeqNum squashedSeqNum[MaxThreads]
Definition: comm.hh:95
gem5::o3::TimeStruct
Struct that defines all backwards communication.
Definition: comm.hh:112
gem5::o3::TimeStruct::DecodeComm::doneSeqNum
InstSeqNum doneSeqNum
Definition: comm.hh:119
gem5::o3::MaxWidth
static constexpr int MaxWidth
Definition: limits.hh:37
gem5::o3::TimeStruct::DecodeComm::squash
bool squash
Definition: comm.hh:123
gem5::o3::TimeStruct::decodeInfo
DecodeComm decodeInfo[MaxThreads]
Definition: comm.hh:129
gem5::o3::TimeStruct::CommitComm::emptyROB
bool emptyROB
Notify Rename that the ROB is empty.
Definition: comm.hh:203
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::IEWStruct::squash
bool squash[MaxThreads]
Definition: comm.hh:98
dyn_inst_ptr.hh
gem5::o3::TimeStruct::renameBlock
bool renameBlock[MaxThreads]
Definition: comm.hh:222
gem5::o3::TimeStruct::CommitComm::squashInst
DynInstPtr squashInst
Instruction that caused the a non-mispredict squash.
Definition: comm.hh:178
gem5::o3::TimeStruct::DecodeComm::branchAddr
uint64_t branchAddr
Definition: comm.hh:121
gem5::o3::IEWStruct::pc
TheISA::PCState pc[MaxThreads]
Definition: comm.hh:96
gem5::o3::FetchStruct::size
int size
Definition: comm.hh:63
gem5::o3::TimeStruct::DecodeComm::nextPC
TheISA::PCState nextPC
Definition: comm.hh:116
gem5::o3::TimeStruct::IewComm::iqCount
unsigned iqCount
Definition: comm.hh:144
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::FetchStruct::fetchFaultSN
InstSeqNum fetchFaultSN
Definition: comm.hh:67
gem5::o3::TimeStruct::CommitComm::branchTaken
bool branchTaken
Was the branch taken or not.
Definition: comm.hh:206
gem5::o3::TimeStruct::CommitComm::interruptPending
bool interruptPending
If an interrupt is pending and fetch should stall.
Definition: comm.hh:208
gem5::o3::IEWStruct::mispredictInst
DynInstPtr mispredictInst[MaxThreads]
Definition: comm.hh:93
types.hh
gem5::o3::DecodeStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:76
gem5::o3::TimeStruct::decodeBlock
bool decodeBlock[MaxThreads]
Definition: comm.hh:220
gem5::o3::TimeStruct::CommitComm
Definition: comm.hh:154
gem5::o3::DecodeStruct::size
int size
Definition: comm.hh:74
gem5::o3::TimeStruct::DecodeComm
Definition: comm.hh:114
gem5::o3::TimeStruct::IewComm::dispatchedToLQ
unsigned dispatchedToLQ
Definition: comm.hh:141
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::TimeStruct::CommitComm::usedROB
bool usedROB
Rename should re-read number of free rob entries.
Definition: comm.hh:200
gem5::o3::TimeStruct::iewBlock
bool iewBlock[MaxThreads]
Definition: comm.hh:224
gem5::o3::IEWStruct::branchMispredict
bool branchMispredict[MaxThreads]
Definition: comm.hh:99
gem5::o3::TimeStruct::commitInfo
CommitComm commitInfo[MaxThreads]
Definition: comm.hh:218
gem5::o3::IssueStruct::insts
DynInstPtr insts[MaxWidth]
Definition: comm.hh:108
gem5::o3::DecodeStruct
Struct that defines the information passed from decode to rename.
Definition: comm.hh:72
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::TimeStruct::CommitComm::robSquashing
bool robSquashing
Definition: comm.hh:197
limits.hh
gem5::o3::TimeStruct::CommitComm::doneSeqNum
InstSeqNum doneSeqNum
Represents the instruction that has either been retired or squashed.
Definition: comm.hh:191
gem5::o3::TimeStruct::iewInfo
IewComm iewInfo[MaxThreads]
Definition: comm.hh:152
gem5::o3::RenameStruct::size
int size
Definition: comm.hh:82
gem5::o3::IEWStruct::mispredPC
Addr mispredPC[MaxThreads]
Definition: comm.hh:94
gem5::o3::TimeStruct::CommitComm::pc
TheISA::PCState pc
The pc of the next instruction to execute.
Definition: comm.hh:171
gem5::o3::RenameStruct
Struct that defines the information passed from rename to IEW.
Definition: comm.hh:80

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