#include <comm.hh>

Public Attributes
std::unique_ptr< PCStateBase >	pc
	The pc of the next instruction to execute.

DynInstPtr	mispredictInst
	Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.

DynInstPtr	squashInst
	Instruction that caused the a non-mispredict squash.

DynInstPtr	strictlyOrderedLoad
	Hack for now to send back a strictly ordered access to the IEW stage.

InstSeqNum	nonSpecSeqNum
	Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.

InstSeqNum	doneSeqNum
	Represents the instruction that has either been retired or squashed.

unsigned	freeROBEntries
	Tell Rename how many free entries it has in the ROB.

bool	squash

bool	robSquashing

bool	usedROB
	Rename should re-read number of free rob entries.

bool	emptyROB
	Notify Rename that the ROB is empty.

bool	branchTaken
	Was the branch taken or not.

bool	interruptPending
	If an interrupt is pending and fetch should stall.

bool	clearInterrupt
	If the interrupt ended up being cleared before being handled.

bool	strictlyOrdered
	Hack for now to send back an strictly ordered access to the IEW stage.

Detailed Description

Definition at line 154 of file comm.hh.

Member Data Documentation

◆ branchTaken

bool gem5::o3::TimeStruct::CommitComm::branchTaken

Was the branch taken or not.

Definition at line 206 of file comm.hh.

◆ clearInterrupt

bool gem5::o3::TimeStruct::CommitComm::clearInterrupt

If the interrupt ended up being cleared before being handled.

Definition at line 210 of file comm.hh.

◆ doneSeqNum

InstSeqNum gem5::o3::TimeStruct::CommitComm::doneSeqNum

Represents the instruction that has either been retired or squashed.

Similar to having a single bus that broadcasts the retired or squashed sequence number.

Definition at line 191 of file comm.hh.

◆ emptyROB

bool gem5::o3::TimeStruct::CommitComm::emptyROB

Notify Rename that the ROB is empty.

Definition at line 203 of file comm.hh.

◆ freeROBEntries

unsigned gem5::o3::TimeStruct::CommitComm::freeROBEntries

Tell Rename how many free entries it has in the ROB.

Definition at line 194 of file comm.hh.

◆ interruptPending

bool gem5::o3::TimeStruct::CommitComm::interruptPending

If an interrupt is pending and fetch should stall.

Definition at line 208 of file comm.hh.

◆ mispredictInst

DynInstPtr gem5::o3::TimeStruct::CommitComm::mispredictInst

Provide fetch the instruction that mispredicted, if this pointer is not-null a misprediction occured.

Definition at line 175 of file comm.hh.

◆ nonSpecSeqNum

InstSeqNum gem5::o3::TimeStruct::CommitComm::nonSpecSeqNum

Communication specifically to the IQ to tell the IQ that it can schedule a non-speculative instruction.

Definition at line 186 of file comm.hh.

◆ pc

std::unique_ptr<PCStateBase> gem5::o3::TimeStruct::CommitComm::pc

The pc of the next instruction to execute.

This is the next instruction for a branch mispredict, but the same instruction for order violation and the like

Definition at line 171 of file comm.hh.

◆ robSquashing

bool gem5::o3::TimeStruct::CommitComm::robSquashing

Definition at line 197 of file comm.hh.

◆ squash

bool gem5::o3::TimeStruct::CommitComm::squash

Definition at line 196 of file comm.hh.

◆ squashInst

DynInstPtr gem5::o3::TimeStruct::CommitComm::squashInst

Instruction that caused the a non-mispredict squash.

Definition at line 178 of file comm.hh.

◆ strictlyOrdered

bool gem5::o3::TimeStruct::CommitComm::strictlyOrdered

Hack for now to send back an strictly ordered access to the IEW stage.

Definition at line 214 of file comm.hh.

◆ strictlyOrderedLoad

DynInstPtr gem5::o3::TimeStruct::CommitComm::strictlyOrderedLoad

Hack for now to send back a strictly ordered access to the IEW stage.

Definition at line 182 of file comm.hh.

◆ usedROB

bool gem5::o3::TimeStruct::CommitComm::usedROB

Rename should re-read number of free rob entries.

Definition at line 200 of file comm.hh.

The documentation for this struct was generated from the following file:

cpu/o3/comm.hh

Public Attributes