gem5  v21.1.0.2
Classes | Typedefs | Variables
gem5::o3 Namespace Reference

Classes

class  Checker
 Specific non-templated derived class used for SimObject configuration. More...
 
class  Commit
 Commit handles single threaded and SMT commit. More...
 
class  CPU
 O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...
 
class  Decode
 Decode class handles both single threaded and SMT decode. More...
 
struct  DecodeStruct
 Struct that defines the information passed from decode to rename. More...
 
class  DependencyEntry
 Node in a linked list. More...
 
class  DependencyGraph
 Array of linked list that maintains the dependencies between producing instructions and consuming instructions. More...
 
class  DynInst
 
class  ElasticTrace
 The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU. More...
 
class  Fetch
 Fetch class handles both single threaded and SMT fetch. More...
 
struct  FetchStruct
 Struct that defines the information passed from fetch to decode. More...
 
class  FUPool
 Pool of FU's, specific to the new CPU model. More...
 
class  IEW
 IEW handles both single threaded and SMT IEW (issue/execute/writeback). More...
 
struct  IEWStruct
 Struct that defines the information passed from IEW to commit. More...
 
class  InstructionQueue
 A standard instruction queue class. More...
 
struct  IssueStruct
 
class  LSQ
 
class  LSQUnit
 Class that implements the actual LQ and SQ for each specific thread. More...
 
struct  ltseqnum
 
class  MemDepUnit
 Memory dependency unit class. More...
 
class  PhysRegFile
 Simple physical register file class. More...
 
class  Rename
 Rename handles both single threaded and SMT rename. More...
 
struct  RenameStruct
 Struct that defines the information passed from rename to IEW. More...
 
class  ROB
 ROB class. More...
 
class  Scoreboard
 Implements a simple scoreboard to track which registers are ready. More...
 
class  SimpleFreeList
 Free list for a single class of registers (e.g., integer or floating point). More...
 
class  SimpleRenameMap
 Register rename map for a single class of registers (e.g., integer or floating point). More...
 
class  SimpleTrace
 
class  StoreSet
 Implements a store set predictor for determining if memory instructions are dependent upon each other. More...
 
class  ThreadContext
 Derived ThreadContext class for use with the O3CPU. More...
 
class  ThreadState
 Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc. More...
 
struct  TimeStruct
 Struct that defines all backwards communication. More...
 
class  UnifiedFreeList
 FreeList class that simply holds the list of free integer and floating point registers. More...
 
class  UnifiedRenameMap
 Unified register rename map for all classes of registers. More...
 

Typedefs

using DynInstPtr = RefCountingPtr< DynInst >
 
using DynInstConstPtr = RefCountingPtr< const DynInst >
 

Variables

static constexpr int MaxWidth = 12
 
static constexpr int MaxThreads = 4
 

Typedef Documentation

◆ DynInstConstPtr

Definition at line 56 of file dyn_inst_ptr.hh.

◆ DynInstPtr

Definition at line 55 of file dyn_inst_ptr.hh.

Variable Documentation

◆ MaxThreads

constexpr int gem5::o3::MaxThreads = 4
staticconstexpr

◆ MaxWidth

constexpr int gem5::o3::MaxWidth = 12
staticconstexpr

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