gem5  v21.1.0.2
dramsim3_wrapper.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2013 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  *
37  */
38 
39 #include <cassert>
40 
46 #ifdef DEBUG
47 #undef DEBUG
48 #endif
49 
50 #include "mem/dramsim3_wrapper.hh"
51 
52 #include <fstream>
53 
54 #include "DRAMsim3/src/dramsim3.h"
55 #include "base/compiler.hh"
56 #include "base/logging.hh"
57 
58 namespace gem5
59 {
60 
61 namespace memory
62 {
63 
64 DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
65  const std::string& working_dir,
66  std::function<void(uint64_t)> read_cb,
67  std::function<void(uint64_t)> write_cb) :
68  dramsim(dramsim3::GetMemorySystem(config_file, working_dir,
69  read_cb, write_cb)),
70  _clockPeriod(0.0), _queueSize(0), _burstSize(0)
71 {
72  // there is no way of getting DRAMsim3 to tell us what frequency
73  // it is assuming, so we have to extract it ourselves
74  _clockPeriod = dramsim->GetTCK();
75 
76  if (!_clockPeriod)
77  fatal("DRAMsim3 wrapper failed to get clock\n");
78 
79  // we also need to know what transaction queue size DRAMsim3 is
80  // using so we can stall when responses are blocked
81  _queueSize = dramsim->GetQueueSize();
82 
83  if (!_queueSize)
84  fatal("DRAMsim3 wrapper failed to get queue size\n");
85 
86 
87  // finally, get the data bus bits and burst length so we can add a
88  // sanity check for the burst size
89  unsigned int dataBusBits = dramsim->GetBusBits();
90  unsigned int burstLength = dramsim->GetBurstLength();
91 
92  if (!dataBusBits || !burstLength)
93  fatal("DRAMsim3 wrapper failed to get burst size\n");
94 
95  _burstSize = dataBusBits * burstLength / 8;
96 }
97 
99 {
100  delete dramsim;
101 }
102 
103 
104 void
106 {
107  dramsim->PrintStats();
108 }
109 
110 void
112 {
113  dramsim->ResetStats();
114 }
115 
116 void
117 DRAMsim3Wrapper::setCallbacks(std::function<void(uint64_t)> read_complete,
118  std::function<void(uint64_t)> write_complete)
119 {
120  dramsim->RegisterCallbacks(read_complete, write_complete);
121 }
122 
123 bool
124 DRAMsim3Wrapper::canAccept(uint64_t addr, bool is_write) const
125 {
126  return dramsim->WillAcceptTransaction(addr, is_write);
127 }
128 
129 void
130 DRAMsim3Wrapper::enqueue(uint64_t addr, bool is_write)
131 {
132  GEM5_VAR_USED bool success = dramsim->AddTransaction(addr, is_write);
133  assert(success);
134 }
135 
136 double
138 {
139  return _clockPeriod;
140 }
141 
142 unsigned int
144 {
145  return _queueSize;
146 }
147 
148 unsigned int
150 {
151  return _burstSize;
152 }
153 
154 void
156 {
157  dramsim->ClockTick();
158 }
159 
160 } // namespace memory
161 } // namespace gem5
gem5::memory::DRAMsim3Wrapper::dramsim
dramsim3::MemorySystem * dramsim
Definition: dramsim3_wrapper.hh:78
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::memory::DRAMsim3Wrapper::canAccept
bool canAccept(uint64_t addr, bool is_write) const
Determine if the controller can accept a new packet or not.
Definition: dramsim3_wrapper.cc:124
gem5::memory::DRAMsim3Wrapper::clockPeriod
double clockPeriod() const
Get the internal clock period used by DRAMsim3, specified in ns.
Definition: dramsim3_wrapper.cc:137
gem5::memory::DRAMsim3Wrapper::setCallbacks
void setCallbacks(std::function< void(uint64_t)> read_complete, std::function< void(uint64_t)> write_complete)
Set the callbacks to use for read and write completion.
Definition: dramsim3_wrapper.cc:117
gem5::memory::DRAMsim3Wrapper::burstSize
unsigned int burstSize() const
Get the burst size in bytes used by DRAMsim3.
Definition: dramsim3_wrapper.cc:149
gem5::memory::DRAMsim3Wrapper::printStats
void printStats()
Print the stats gathered in DRAMsim3.
Definition: dramsim3_wrapper.cc:105
memory
Definition: mem.h:38
gem5::memory::DRAMsim3Wrapper::queueSize
unsigned int queueSize() const
Get the transaction queue size used by DRAMsim3.
Definition: dramsim3_wrapper.cc:143
gem5::memory::DRAMsim3Wrapper::DRAMsim3Wrapper
DRAMsim3Wrapper(const std::string &config_file, const std::string &working_dir, std::function< void(uint64_t)> read_cb, std::function< void(uint64_t)> write_cb)
Create an instance of the DRAMsim3 multi-channel memory controller using a specific config and system...
Definition: dramsim3_wrapper.cc:64
gem5::memory::DRAMsim3Wrapper::_clockPeriod
double _clockPeriod
Definition: dramsim3_wrapper.hh:80
dramsim3_wrapper.hh
compiler.hh
dramsim3
Forward declaration to avoid includes.
Definition: dramsim3_wrapper.hh:53
gem5::memory::DRAMsim3Wrapper::enqueue
void enqueue(uint64_t addr, bool is_write)
Enqueue a packet.
Definition: dramsim3_wrapper.cc:130
gem5::memory::DRAMsim3Wrapper::~DRAMsim3Wrapper
~DRAMsim3Wrapper()
Definition: dramsim3_wrapper.cc:98
gem5::memory::DRAMsim3Wrapper::tick
void tick()
Progress the memory controller one cycle.
Definition: dramsim3_wrapper.cc:155
logging.hh
gem5::memory::DRAMsim3Wrapper::_queueSize
unsigned int _queueSize
Definition: dramsim3_wrapper.hh:82
gem5::memory::DRAMsim3Wrapper::_burstSize
unsigned int _burstSize
Definition: dramsim3_wrapper.hh:84
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::memory::DRAMsim3Wrapper::resetStats
void resetStats()
Reset stats (useful for fastforwarding switch)
Definition: dramsim3_wrapper.cc:111
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Tue Sep 21 2021 12:25:32 for gem5 by doxygen 1.8.17