gem5::memory Namespace Reference

Namespaces
	qos

Classes
class	LockedAddr
	Locked address class that represents a physical address and a context id. More...
class	AbstractMemory
	An abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information. More...
class	CfiMemory
	CfiMemory: This is modelling a flash memory adhering to the Common Flash Interface (CFI): More...
class	DRAMInterface
	Interface to DRAM devices with media specific parameters, statistics, and functions. More...
class	DRAMSim2
class	DRAMSim2Wrapper
	Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world. More...
class	DRAMsim3
class	DRAMsim3Wrapper
	Wrapper class to avoid having DRAMsim3 names like ClockDomain etc clashing with the normal gem5 world. More...
class	HBMCtrl
	HBM2 is divided into two pseudo channels which have independent data buses but share a command bus (separate row and column command bus). More...
class	HeteroMemCtrl
class	BurstHelper
	A burst helper helps organize and manage a packet that is larger than the memory burst size. More...
class	MemPacket
	A memory packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address. More...
class	MemCtrl
	The memory controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary controller. More...
class	MemInterface
	General interface to memory device Includes functions and parameters shared across media types. More...
class	NVMInterface
	Interface to NVM devices with media specific parameters, statistics, and functions. More...
class	BackingStoreEntry
	A single entry for the backing store. More...
class	PhysicalMemory
	The physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect. More...
class	SharedMemoryServer
class	SimpleMemory
	The simple memory is a basic single-ported memory controller with a configurable throughput and latency. More...

Typedefs
typedef std::deque< MemPacket * >	MemPacketQueue

Functions
	GEM5_DEPRECATED_NAMESPACE (QoS, qos)

Variables
int	SHOW_SIM_OUTPUT = 0
	DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in the DRAMSim2 print macros), otherwise we get linking errors due to undefined references. More...

Typedef Documentation

MemPacketQueue

typedef std::deque<MemPacket*> gem5::memory::MemPacketQueue

Definition at line 220 of file mem_ctrl.hh.

Function Documentation

GEM5_DEPRECATED_NAMESPACE()

gem5::memory::GEM5_DEPRECATED_NAMESPACE	(	QoS	,
		qos
	)

Variable Documentation

SHOW_SIM_OUTPUT

int gem5::memory::SHOW_SIM_OUTPUT = 0

DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in the DRAMSim2 print macros), otherwise we get linking errors due to undefined references.

Definition at line 68 of file dramsim2_wrapper.cc.

Referenced by gem5::memory::DRAMSim2Wrapper::DRAMSim2Wrapper().