inst_queue.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2011-2012, 2014 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_O3_INST_QUEUE_HH__
#define __CPU_O3_INST_QUEUE_HH__
 
#include <list>
#include <map>
#include <queue>
#include <vector>
 
#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/dep_graph.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/mem_dep_unit.hh"
#include "cpu/o3/store_set.hh"
#include "cpu/op_class.hh"
#include "cpu/timebuf.hh"
#include "enums/SMTQueuePolicy.hh"
#include "sim/eventq.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace memory
{
class MemInterface;
} // namespace memory
 
namespace o3
{
 
class FUPool;
class CPU;
class IEW;
 
class InstructionQueue
{
  public:
    // Typedef of iterator through the list of instructions.
    typedef typename std::list<DynInstPtr>::iterator ListIt;
 
    class FUCompletion : public Event
    {
      private:
        DynInstPtr inst;
 
        int fuIdx;
 
        InstructionQueue *iqPtr;
 
        bool freeFU;
 
      public:
        FUCompletion(const DynInstPtr &_inst, int fu_idx,
                     InstructionQueue *iq_ptr);
 
        virtual void process();
        virtual const char *description() const;
        void setFreeFU() { freeFU = true; }
    };
 
    InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
            const BaseO3CPUParams &params);
 
    ~InstructionQueue();
 
    std::string name() const;
 
    void resetState();
 
    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
    void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
 
    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
    bool isDrained() const;
 
    void drainSanityCheck() const;
 
    void takeOverFrom();
 
    int entryAmount(ThreadID num_threads);
 
    void resetEntries();
 
    unsigned numFreeEntries();
 
    unsigned numFreeEntries(ThreadID tid);
 
    bool isFull();
 
    bool isFull(ThreadID tid);
 
    bool hasReadyInsts();
 
    void insert(const DynInstPtr &new_inst);
 
    void insertNonSpec(const DynInstPtr &new_inst);
 
    void insertBarrier(const DynInstPtr &barr_inst);
 
    DynInstPtr getInstToExecute();
 
    DynInstPtr getDeferredMemInstToExecute();
 
    DynInstPtr getBlockedMemInstToExecute();
 
    void
    recordProducer(const DynInstPtr &inst)
    {
        addToProducers(inst);
    }
 
    void processFUCompletion(const DynInstPtr &inst, int fu_idx);
 
    void scheduleReadyInsts();
 
    void scheduleNonSpec(const InstSeqNum &inst);
 
    void commit(const InstSeqNum &inst, ThreadID tid = 0);
 
    int wakeDependents(const DynInstPtr &completed_inst);
 
    void addReadyMemInst(const DynInstPtr &ready_inst);
 
    void rescheduleMemInst(const DynInstPtr &resched_inst);
 
    void replayMemInst(const DynInstPtr &replay_inst);
 
    void deferMemInst(const DynInstPtr &deferred_inst);
 
    void blockMemInst(const DynInstPtr &blocked_inst);
 
    void cacheUnblocked();
 
    void violation(const DynInstPtr &store, const DynInstPtr &faulting_load);
 
    void squash(ThreadID tid);
 
    unsigned getCount(ThreadID tid) { return count[tid]; };
 
    void printInsts();
 
  private:
    void doSquash(ThreadID tid);
 
    // Various pointers
 
    CPU *cpu;
 
    memory::MemInterface *dcacheInterface;
 
    IEW *iewStage;
 
    MemDepUnit memDepUnit[MaxThreads];
 
    TimeBuffer<IssueStruct> *issueToExecuteQueue;
 
    TimeBuffer<TimeStruct> *timeBuffer;
 
    typename TimeBuffer<TimeStruct>::wire fromCommit;
 
    FUPool *fuPool;
 
    // Instruction lists, ready queues, and ordering
 
    std::list<DynInstPtr> instList[MaxThreads];
 
    std::list<DynInstPtr> instsToExecute;
 
    std::list<DynInstPtr> deferredMemInsts;
 
    std::list<DynInstPtr> blockedMemInsts;
 
    std::list<DynInstPtr> retryMemInsts;
 
    struct PqCompare
    {
        bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const;
    };
 
    typedef std::priority_queue<
        DynInstPtr, std::vector<DynInstPtr>, PqCompare> ReadyInstQueue;
 
    ReadyInstQueue readyInsts[Num_OpClasses];
 
    std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
 
    typedef std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
 
    struct ListOrderEntry
    {
        OpClass queueType;
        InstSeqNum oldestInst;
    };
 
    std::list<ListOrderEntry> listOrder;
 
    typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
 
    bool queueOnList[Num_OpClasses];
 
    ListOrderIt readyIt[Num_OpClasses];
 
    void addToOrderList(OpClass op_class);
 
    void moveToYoungerInst(ListOrderIt age_order_it);
 
    DependencyGraph<DynInstPtr> dependGraph;
 
    // Various parameters
 
    SMTQueuePolicy iqPolicy;
 
    ThreadID numThreads;
 
    std::list<ThreadID> *activeThreads;
 
    unsigned count[MaxThreads];
 
    unsigned maxEntries[MaxThreads];
 
    unsigned freeEntries;
 
    unsigned numEntries;
 
    unsigned totalWidth;
 
    unsigned numPhysRegs;
 
    int wbOutstanding;
 
    Cycles commitToIEWDelay;
 
    InstSeqNum squashedSeqNum[MaxThreads];
 
    std::vector<bool> regScoreboard;
 
    bool addToDependents(const DynInstPtr &new_inst);
 
    void addToProducers(const DynInstPtr &new_inst);
 
    void addIfReady(const DynInstPtr &inst);
 
    int countInsts();
 
    void dumpLists();
 
    void dumpInsts();
 
    struct IQStats : public statistics::Group
    {
        IQStats(CPU *cpu, const unsigned &total_width);
        statistics::Scalar instsAdded;
        statistics::Scalar nonSpecInstsAdded;
 
        statistics::Scalar instsIssued;
        statistics::Scalar intInstsIssued;
        statistics::Scalar floatInstsIssued;
        statistics::Scalar branchInstsIssued;
        statistics::Scalar memInstsIssued;
        statistics::Scalar miscInstsIssued;
        statistics::Scalar squashedInstsIssued;
        statistics::Scalar squashedInstsExamined;
        statistics::Scalar squashedOperandsExamined;
        statistics::Scalar squashedNonSpecRemoved;
        // Also include number of instructions rescheduled and replayed.
 
        // statistics::VectorDistribution queueResDist;
        statistics::Distribution numIssuedDist;
        // statistics::VectorDistribution issueDelayDist;
 
        statistics::Vector statFuBusy;
        // statistics::Vector dist_unissued;
        statistics::Vector2d statIssuedInstType;
 
        statistics::Formula issueRate;
 
        statistics::Vector fuBusy;
        statistics::Formula fuBusyRate;
    } iqStats;
 
   public:
    struct IQIOStats : public statistics::Group
    {
        IQIOStats(statistics::Group *parent);
        statistics::Scalar intInstQueueReads;
        statistics::Scalar intInstQueueWrites;
        statistics::Scalar intInstQueueWakeupAccesses;
        statistics::Scalar fpInstQueueReads;
        statistics::Scalar fpInstQueueWrites;
        statistics::Scalar fpInstQueueWakeupAccesses;
        statistics::Scalar vecInstQueueReads;
        statistics::Scalar vecInstQueueWrites;
        statistics::Scalar vecInstQueueWakeupAccesses;
 
        statistics::Scalar intAluAccesses;
        statistics::Scalar fpAluAccesses;
        statistics::Scalar vecAluAccesses;
    } iqIOStats;
};
 
} // namespace o3
} // namespace gem5
 
#endif //__CPU_O3_INST_QUEUE_HH__