gem5  v22.0.0.1
inst_queue.hh
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41 
42 #ifndef __CPU_O3_INST_QUEUE_HH__
43 #define __CPU_O3_INST_QUEUE_HH__
44 
45 #include <list>
46 #include <map>
47 #include <queue>
48 #include <vector>
49 
50 #include "base/statistics.hh"
51 #include "base/types.hh"
52 #include "cpu/inst_seq.hh"
53 #include "cpu/o3/comm.hh"
54 #include "cpu/o3/dep_graph.hh"
55 #include "cpu/o3/dyn_inst_ptr.hh"
56 #include "cpu/o3/limits.hh"
57 #include "cpu/o3/mem_dep_unit.hh"
58 #include "cpu/o3/store_set.hh"
59 #include "cpu/op_class.hh"
60 #include "cpu/timebuf.hh"
61 #include "enums/SMTQueuePolicy.hh"
62 #include "sim/eventq.hh"
63 
64 namespace gem5
65 {
66 
67 struct BaseO3CPUParams;
68 
69 namespace memory
70 {
71 class MemInterface;
72 } // namespace memory
73 
74 namespace o3
75 {
76 
77 class FUPool;
78 class CPU;
79 class IEW;
80 
99 {
100  public:
101  // Typedef of iterator through the list of instructions.
103 
105  class FUCompletion : public Event
106  {
107  private:
110 
112  int fuIdx;
113 
116 
120  bool freeFU;
121 
122  public:
124  FUCompletion(const DynInstPtr &_inst, int fu_idx,
125  InstructionQueue *iq_ptr);
126 
127  virtual void process();
128  virtual const char *description() const;
129  void setFreeFU() { freeFU = true; }
130  };
131 
133  InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
134  const BaseO3CPUParams &params);
135 
138 
140  std::string name() const;
141 
143  void resetState();
144 
147 
150 
153 
155  bool isDrained() const;
156 
158  void drainSanityCheck() const;
159 
161  void takeOverFrom();
162 
164  int entryAmount(ThreadID num_threads);
165 
167  void resetEntries();
168 
170  unsigned numFreeEntries();
171 
173  unsigned numFreeEntries(ThreadID tid);
174 
176  bool isFull();
177 
179  bool isFull(ThreadID tid);
180 
182  bool hasReadyInsts();
183 
185  void insert(const DynInstPtr &new_inst);
186 
188  void insertNonSpec(const DynInstPtr &new_inst);
189 
193  void insertBarrier(const DynInstPtr &barr_inst);
194 
199 
204 
209 
214  void
216  {
217  addToProducers(inst);
218  }
219 
221  void processFUCompletion(const DynInstPtr &inst, int fu_idx);
222 
227  void scheduleReadyInsts();
228 
230  void scheduleNonSpec(const InstSeqNum &inst);
231 
236  void commit(const InstSeqNum &inst, ThreadID tid = 0);
237 
239  int wakeDependents(const DynInstPtr &completed_inst);
240 
242  void addReadyMemInst(const DynInstPtr &ready_inst);
243 
248  void rescheduleMemInst(const DynInstPtr &resched_inst);
249 
251  void replayMemInst(const DynInstPtr &replay_inst);
252 
257  void deferMemInst(const DynInstPtr &deferred_inst);
258 
260  void blockMemInst(const DynInstPtr &blocked_inst);
261 
263  void cacheUnblocked();
264 
266  void violation(const DynInstPtr &store, const DynInstPtr &faulting_load);
267 
272  void squash(ThreadID tid);
273 
275  unsigned getCount(ThreadID tid) { return count[tid]; };
276 
278  void printInsts();
279 
280  private:
282  void doSquash(ThreadID tid);
283 
285  // Various pointers
287 
290 
293 
296 
301 
306 
309 
312 
315 
317  // Instruction lists, ready queues, and ordering
319 
322 
325 
330 
333 
338 
346  struct PqCompare
347  {
348  bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const;
349  };
350 
351  typedef std::priority_queue<
353 
358 
366  std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
367 
368  typedef std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
369 
372  {
373  OpClass queueType;
375  };
376 
385 
387 
390 
395 
397  void addToOrderList(OpClass op_class);
398 
403  void moveToYoungerInst(ListOrderIt age_order_it);
404 
406 
408  // Various parameters
410 
412  SMTQueuePolicy iqPolicy;
413 
416 
419 
421  unsigned count[MaxThreads];
422 
425 
427  unsigned freeEntries;
428 
430  unsigned numEntries;
431 
433  unsigned totalWidth;
434 
436  unsigned numPhysRegs;
437 
440 
445 
448 
456 
458  bool addToDependents(const DynInstPtr &new_inst);
459 
461  void addToProducers(const DynInstPtr &new_inst);
462 
464  void addIfReady(const DynInstPtr &inst);
465 
470  int countInsts();
471 
476  void dumpLists();
477 
481  void dumpInsts();
482 
483  struct IQStats : public statistics::Group
484  {
485  IQStats(CPU *cpu, const unsigned &total_width);
490 
516  // Also include number of instructions rescheduled and replayed.
517 
521  // statistics::VectorDistribution queueResDist;
527  // statistics::VectorDistribution issueDelayDist;
528 
533  // statistics::Vector dist_unissued;
536 
539 
544  } iqStats;
545 
546  public:
547  struct IQIOStats : public statistics::Group
548  {
549  IQIOStats(statistics::Group *parent);
559 
563  } iqIOStats;
564 };
565 
566 } // namespace o3
567 } // namespace gem5
568 
569 #endif //__CPU_O3_INST_QUEUE_HH__
gem5::o3::InstructionQueue::IQStats::miscInstsIssued
statistics::Scalar miscInstsIssued
Stat for number of miscellaneous instructions issued.
Definition: inst_queue.hh:501
gem5::o3::InstructionQueue::readyIt
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Definition: inst_queue.hh:394
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::o3::InstructionQueue::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
Definition: inst_queue.cc:1088
gem5::o3::InstructionQueue::addToOrderList
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
Definition: inst_queue.cc:677
gem5::o3::InstructionQueue::maxEntries
unsigned maxEntries[MaxThreads]
Max IQ Entries Per Thread.
Definition: inst_queue.hh:424
gem5::o3::InstructionQueue::resetEntries
void resetEntries()
Resets max entries for all threads.
Definition: inst_queue.cc:490
gem5::o3::InstructionQueue::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: inst_queue.cc:464
gem5::o3::InstructionQueue::issueToExecuteQueue
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
Definition: inst_queue.hh:305
gem5::o3::InstructionQueue::IQStats::statIssuedInstType
statistics::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
Definition: inst_queue.hh:535
gem5::o3::InstructionQueue::IQIOStats::fpAluAccesses
statistics::Scalar fpAluAccesses
Definition: inst_queue.hh:561
gem5::o3::InstructionQueue::IQStats::squashedInstsIssued
statistics::Scalar squashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
Definition: inst_queue.hh:504
gem5::o3::InstructionQueue::countInsts
int countInsts()
Debugging function to count how many entries are in the IQ.
Definition: inst_queue.cc:1454
gem5::o3::InstructionQueue::instsToExecute
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
Definition: inst_queue.hh:324
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2084
gem5::o3::InstructionQueue::IQStats::instsIssued
statistics::Scalar instsIssued
Definition: inst_queue.hh:491
gem5::o3::InstructionQueue::getDeferredMemInstToExecute
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
Definition: inst_queue.cc:1134
op_class.hh
gem5::o3::InstructionQueue::IQIOStats::IQIOStats
IQIOStats(statistics::Group *parent)
Definition: inst_queue.cc:327
gem5::o3::InstructionQueue::regScoreboard
std::vector< bool > regScoreboard
A cache of the recently woken registers.
Definition: inst_queue.hh:455
gem5::o3::InstructionQueue::isFull
bool isFull()
Returns whether or not the IQ is full.
Definition: inst_queue.cc:526
memory
Definition: mem.h:38
gem5::o3::InstructionQueue::queueOnList
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
Definition: inst_queue.hh:389
gem5::o3::InstructionQueue::ReadyInstQueue
std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, PqCompare > ReadyInstQueue
Definition: inst_queue.hh:352
gem5::o3::InstructionQueue::nonSpecInsts
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit.
Definition: inst_queue.hh:366
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::o3::InstructionQueue::getBlockedMemInstToExecute
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
Definition: inst_queue.cc:1148
gem5::o3::InstructionQueue::dcacheInterface
memory::MemInterface * dcacheInterface
Cache interface.
Definition: inst_queue.hh:292
gem5::o3::InstructionQueue::IQStats::issueRate
statistics::Formula issueRate
Number of instructions issued per cycle.
Definition: inst_queue.hh:538
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWrites
statistics::Scalar vecInstQueueWrites
Definition: inst_queue.hh:557
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::o3::InstructionQueue::cpu
CPU * cpu
Pointer to the CPU.
Definition: inst_queue.hh:289
gem5::o3::InstructionQueue::commit
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
Definition: inst_queue.cc:948
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWakeupAccesses
statistics::Scalar vecInstQueueWakeupAccesses
Definition: inst_queue.hh:558
gem5::o3::DependencyGraph
Array of linked list that maintains the dependencies between producing instructions and consuming ins...
Definition: dep_graph.hh:77
gem5::o3::InstructionQueue::FUCompletion::freeFU
bool freeFU
Should the FU be added to the list to be freed upon completing this event.
Definition: inst_queue.hh:120
gem5::o3::InstructionQueue::IQStats::squashedInstsExamined
statistics::Scalar squashedInstsExamined
Stat for number of squashed instructions examined when squashing.
Definition: inst_queue.hh:507
gem5::statistics::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2058
gem5::o3::InstructionQueue::IQStats::instsAdded
statistics::Scalar instsAdded
Stat for number of instructions added.
Definition: inst_queue.hh:487
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::o3::InstructionQueue::PqCompare::operator()
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
Definition: inst_queue.cc:1326
gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads
statistics::Scalar intInstQueueReads
Definition: inst_queue.hh:550
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueReads
statistics::Scalar vecInstQueueReads
Definition: inst_queue.hh:556
std::vector
STL vector class.
Definition: stl.hh:37
gem5::o3::InstructionQueue::numEntries
unsigned numEntries
The number of entries in the instruction queue.
Definition: inst_queue.hh:430
gem5::o3::InstructionQueue::recordProducer
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
Definition: inst_queue.hh:215
gem5::o3::MemDepUnit
Memory dependency unit class.
Definition: mem_dep_unit.hh:90
gem5::o3::InstructionQueue::addToDependents
bool addToDependents(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
Definition: inst_queue.cc:1333
gem5::o3::InstructionQueue::cacheUnblocked
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Definition: inst_queue.cc:1124
gem5::o3::InstructionQueue::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: inst_queue.cc:473
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWakeupAccesses
statistics::Scalar intInstQueueWakeupAccesses
Definition: inst_queue.hh:552
gem5::o3::InstructionQueue::numPhysRegs
unsigned numPhysRegs
The number of physical registers in the CPU.
Definition: inst_queue.hh:436
gem5::o3::InstructionQueue::resetState
void resetState()
Resets all instruction queue state.
Definition: inst_queue.cc:393
gem5::o3::InstructionQueue::setIssueToExecuteQueue
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
Definition: inst_queue.cc:438
gem5::o3::InstructionQueue::FUCompletion::inst
DynInstPtr inst
Executing instruction.
Definition: inst_queue.hh:109
gem5::o3::InstructionQueue::ListOrderEntry::queueType
OpClass queueType
Definition: inst_queue.hh:373
gem5::o3::InstructionQueue::dependGraph
DependencyGraph< DynInstPtr > dependGraph
Definition: inst_queue.hh:405
gem5::o3::InstructionQueue::freeEntries
unsigned freeEntries
Number of free IQ entries left.
Definition: inst_queue.hh:427
gem5::RefCountingPtr< DynInst >
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::InstructionQueue::ListOrderIt
std::list< ListOrderEntry >::iterator ListOrderIt
Definition: inst_queue.hh:386
gem5::o3::InstructionQueue::wakeDependents
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
Definition: inst_queue.cc:965
gem5::o3::InstructionQueue::IQIOStats::vecAluAccesses
statistics::Scalar vecAluAccesses
Definition: inst_queue.hh:562
gem5::o3::InstructionQueue::iewStage
IEW * iewStage
Pointer to IEW stage.
Definition: inst_queue.hh:295
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
store_set.hh
gem5::o3::InstructionQueue::memDepUnit
MemDepUnit memDepUnit[MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
Definition: inst_queue.hh:300
gem5::o3::InstructionQueue::deferredMemInsts
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress).
Definition: inst_queue.hh:329
gem5::o3::InstructionQueue::iqIOStats
gem5::o3::InstructionQueue::IQIOStats iqIOStats
timebuf.hh
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueReads
statistics::Scalar fpInstQueueReads
Definition: inst_queue.hh:553
comm.hh
gem5::o3::InstructionQueue::addIfReady
void addIfReady(const DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
Definition: inst_queue.cc:1415
gem5::o3::InstructionQueue::FUCompletion::setFreeFU
void setFreeFU()
Definition: inst_queue.hh:129
gem5::o3::InstructionQueue::IQIOStats::intAluAccesses
statistics::Scalar intAluAccesses
Definition: inst_queue.hh:560
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::InstructionQueue::IQStats::squashedOperandsExamined
statistics::Scalar squashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
Definition: inst_queue.hh:511
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:74
gem5::o3::InstructionQueue::name
std::string name() const
Returns the name of the IQ.
Definition: inst_queue.cc:174
gem5::o3::InstructionQueue::FUCompletion
FU completion event class.
Definition: inst_queue.hh:105
gem5::o3::InstructionQueue::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Definition: inst_queue.cc:444
gem5::o3::InstructionQueue::IQStats
Definition: inst_queue.hh:483
gem5::Event
Definition: eventq.hh:251
gem5::o3::InstructionQueue::doSquash
void doSquash(ThreadID tid)
Does the actual squashing.
Definition: inst_queue.cc:1184
gem5::o3::InstructionQueue::IQStats::branchInstsIssued
statistics::Scalar branchInstsIssued
Stat for number of branch instructions issued.
Definition: inst_queue.hh:497
statistics.hh
gem5::o3::InstructionQueue::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: inst_queue.hh:418
gem5::o3::InstructionQueue::IQStats::squashedNonSpecRemoved
statistics::Scalar squashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
Definition: inst_queue.hh:515
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::InstructionQueue::deferMemInst
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
Definition: inst_queue.cc:1107
mem_dep_unit.hh
gem5::o3::InstructionQueue::retryMemInsts
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
Definition: inst_queue.hh:337
gem5::o3::InstructionQueue::commitToIEWDelay
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
Definition: inst_queue.hh:444
gem5::o3::InstructionQueue::totalWidth
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
Definition: inst_queue.hh:433
gem5::o3::InstructionQueue::IQIOStats
Definition: inst_queue.hh:547
gem5::o3::InstructionQueue::numFreeEntries
unsigned numFreeEntries()
Returns total number of free entries.
Definition: inst_queue.cc:512
gem5::o3::InstructionQueue::IQStats::nonSpecInstsAdded
statistics::Scalar nonSpecInstsAdded
Stat for number of non-speculative instructions added.
Definition: inst_queue.hh:489
gem5::o3::InstructionQueue::addToProducers
void addToProducers(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
Definition: inst_queue.cc:1380
gem5::o3::InstructionQueue::IQStats::fuBusyRate
statistics::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
Definition: inst_queue.hh:543
gem5::o3::InstructionQueue::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
Definition: inst_queue.hh:311
gem5::o3::InstructionQueue::fuPool
FUPool * fuPool
Function unit pool.
Definition: inst_queue.hh:314
gem5::o3::InstructionQueue::printInsts
void printInsts()
Debug function to print all instructions.
gem5::o3::InstructionQueue::dumpInsts
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
Definition: inst_queue.cc:1502
gem5::o3::InstructionQueue::IQStats::memInstsIssued
statistics::Scalar memInstsIssued
Stat for number of memory instructions issued.
Definition: inst_queue.hh:499
gem5::o3::InstructionQueue::scheduleNonSpec
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
Definition: inst_queue.cc:921
dyn_inst_ptr.hh
gem5::o3::InstructionQueue::processFUCompletion
void processFUCompletion(const DynInstPtr &inst, int fu_idx)
Process FU completion event.
Definition: inst_queue.cc:728
gem5::o3::InstructionQueue::getInstToExecute
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Definition: inst_queue.cc:661
gem5::o3::InstructionQueue::PqCompare
Struct for comparing entries to be added to the priority queue.
Definition: inst_queue.hh:346
gem5::o3::InstructionQueue::IQStats::intInstsIssued
statistics::Scalar intInstsIssued
Stat for number of integer instructions issued.
Definition: inst_queue.hh:493
gem5::o3::InstructionQueue::iqStats
gem5::o3::InstructionQueue::IQStats iqStats
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWrites
statistics::Scalar intInstQueueWrites
Definition: inst_queue.hh:551
gem5::o3::InstructionQueue::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Definition: inst_queue.cc:653
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::InstructionQueue::FUCompletion::process
virtual void process()
Definition: inst_queue.cc:74
gem5::o3::InstructionQueue::IQStats::floatInstsIssued
statistics::Scalar floatInstsIssued
Stat for number of floating point instructions issued.
Definition: inst_queue.hh:495
gem5::o3::InstructionQueue::iqPolicy
SMTQueuePolicy iqPolicy
IQ sharing policy for SMT.
Definition: inst_queue.hh:412
gem5::o3::InstructionQueue::squash
void squash(ThreadID tid)
Squashes instructions for a thread.
Definition: inst_queue.cc:1168
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWrites
statistics::Scalar fpInstQueueWrites
Definition: inst_queue.hh:554
gem5::o3::InstructionQueue::~InstructionQueue
~InstructionQueue()
Destructs the IQ.
Definition: inst_queue.cc:164
gem5::o3::InstructionQueue::InstructionQueue
InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)
Constructs an IQ.
Definition: inst_queue.cc:87
types.hh
gem5::o3::InstructionQueue::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: inst_queue.hh:102
gem5::o3::InstructionQueue::isDrained
bool isDrained() const
Determine if we are drained.
Definition: inst_queue.cc:452
gem5::o3::InstructionQueue::FUCompletion::description
virtual const char * description() const
Return a C string describing the event.
Definition: inst_queue.cc:82
gem5::o3::InstructionQueue::moveToYoungerInst
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Definition: inst_queue.cc:703
gem5::o3::InstructionQueue::insertNonSpec
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
Definition: inst_queue.cc:607
gem5::o3::InstructionQueue::blockedMemInsts
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
Definition: inst_queue.hh:332
gem5::o3::InstructionQueue::addReadyMemInst
void addReadyMemInst(const DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
Definition: inst_queue.cc:1066
gem5::o3::InstructionQueue::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
Definition: inst_queue.cc:432
gem5::o3::InstructionQueue::count
unsigned count[MaxThreads]
Per Thread IQ count.
Definition: inst_queue.hh:421
gem5::o3::InstructionQueue::blockMemInst
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Definition: inst_queue.cc:1113
gem5::o3::InstructionQueue::IQStats::IQStats
IQStats(CPU *cpu, const unsigned &total_width)
Definition: inst_queue.cc:179
gem5::o3::InstructionQueue::IQStats::statFuBusy
statistics::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
Definition: inst_queue.hh:532
gem5::o3::InstructionQueue::insert
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
Definition: inst_queue.cc:562
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::InstructionQueue::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
Definition: inst_queue.cc:479
gem5::o3::InstructionQueue::IQStats::fuBusy
statistics::Vector fuBusy
Number of times the FU was busy.
Definition: inst_queue.hh:541
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::InstructionQueue::replayMemInst
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
Definition: inst_queue.cc:1101
gem5::o3::InstructionQueue::IQStats::numIssuedDist
statistics::Distribution numIssuedDist
Distribution of number of instructions in the queue.
Definition: inst_queue.hh:523
gem5::o3::InstructionQueue::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Definition: inst_queue.hh:308
gem5::Num_OpClasses
static const OpClass Num_OpClasses
Definition: op_class.hh:108
gem5::o3::InstructionQueue::numThreads
ThreadID numThreads
Number of Total Threads.
Definition: inst_queue.hh:415
gem5::o3::InstructionQueue::scheduleReadyInsts
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Definition: inst_queue.cc:751
gem5::o3::InstructionQueue::NonSpecMapIt
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
Definition: inst_queue.hh:368
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::InstructionQueue::dumpLists
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
Definition: inst_queue.cc:1460
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::InstructionQueue::wbOutstanding
int wbOutstanding
Number of instructions currently in flight to FUs.
Definition: inst_queue.hh:439
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWakeupAccesses
statistics::Scalar fpInstQueueWakeupAccesses
Definition: inst_queue.hh:555
gem5::o3::InstructionQueue::FUCompletion::iqPtr
InstructionQueue * iqPtr
Pointer back to the instruction queue.
Definition: inst_queue.hh:115
gem5::o3::InstructionQueue::FUCompletion::fuIdx
int fuIdx
Index of the FU used for executing.
Definition: inst_queue.hh:112
limits.hh
gem5::o3::InstructionQueue::squashedSeqNum
InstSeqNum squashedSeqNum[MaxThreads]
The sequence number of the squashed instruction.
Definition: inst_queue.hh:447
gem5::o3::InstructionQueue::ListOrderEntry::oldestInst
InstSeqNum oldestInst
Definition: inst_queue.hh:374
dep_graph.hh
gem5::o3::FUPool
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:75
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::InstructionQueue::listOrder
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
Definition: inst_queue.hh:384
gem5::o3::InstructionQueue::instList
std::list< DynInstPtr > instList[MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
Definition: inst_queue.hh:321
gem5::o3::InstructionQueue::readyInsts
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
Definition: inst_queue.hh:357
gem5::o3::InstructionQueue::violation
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Definition: inst_queue.cc:1160
gem5::o3::InstructionQueue::ListOrderEntry
Entry for the list age ordering by op class.
Definition: inst_queue.hh:371
gem5::o3::InstructionQueue::hasReadyInsts
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Definition: inst_queue.cc:546
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:275
gem5::o3::InstructionQueue::FUCompletion::FUCompletion
FUCompletion(const DynInstPtr &_inst, int fu_idx, InstructionQueue *iq_ptr)
Construct a FU completion event.
Definition: inst_queue.cc:66
eventq.hh

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