gem5  v21.1.0.2
inst_queue.hh
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41 
42 #ifndef __CPU_O3_INST_QUEUE_HH__
43 #define __CPU_O3_INST_QUEUE_HH__
44 
45 #include <list>
46 #include <map>
47 #include <queue>
48 #include <vector>
49 
50 #include "base/statistics.hh"
51 #include "base/types.hh"
52 #include "cpu/inst_seq.hh"
53 #include "cpu/o3/comm.hh"
54 #include "cpu/o3/dep_graph.hh"
55 #include "cpu/o3/dyn_inst_ptr.hh"
56 #include "cpu/o3/limits.hh"
57 #include "cpu/o3/mem_dep_unit.hh"
58 #include "cpu/o3/store_set.hh"
59 #include "cpu/op_class.hh"
60 #include "cpu/timebuf.hh"
61 #include "enums/SMTQueuePolicy.hh"
62 #include "sim/eventq.hh"
63 
64 namespace gem5
65 {
66 
67 struct O3CPUParams;
68 
69 namespace memory
70 {
71 class MemInterface;
72 } // namespace memory
73 
74 namespace o3
75 {
76 
77 class FUPool;
78 class CPU;
79 class IEW;
80 
99 {
100  public:
101  // Typedef of iterator through the list of instructions.
103 
105  class FUCompletion : public Event
106  {
107  private:
110 
112  int fuIdx;
113 
116 
120  bool freeFU;
121 
122  public:
124  FUCompletion(const DynInstPtr &_inst, int fu_idx,
125  InstructionQueue *iq_ptr);
126 
127  virtual void process();
128  virtual const char *description() const;
129  void setFreeFU() { freeFU = true; }
130  };
131 
133  InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params);
134 
137 
139  std::string name() const;
140 
142  void resetState();
143 
146 
149 
152 
154  bool isDrained() const;
155 
157  void drainSanityCheck() const;
158 
160  void takeOverFrom();
161 
163  int entryAmount(ThreadID num_threads);
164 
166  void resetEntries();
167 
169  unsigned numFreeEntries();
170 
172  unsigned numFreeEntries(ThreadID tid);
173 
175  bool isFull();
176 
178  bool isFull(ThreadID tid);
179 
181  bool hasReadyInsts();
182 
184  void insert(const DynInstPtr &new_inst);
185 
187  void insertNonSpec(const DynInstPtr &new_inst);
188 
192  void insertBarrier(const DynInstPtr &barr_inst);
193 
198 
203 
208 
213  void
215  {
216  addToProducers(inst);
217  }
218 
220  void processFUCompletion(const DynInstPtr &inst, int fu_idx);
221 
226  void scheduleReadyInsts();
227 
229  void scheduleNonSpec(const InstSeqNum &inst);
230 
235  void commit(const InstSeqNum &inst, ThreadID tid = 0);
236 
238  int wakeDependents(const DynInstPtr &completed_inst);
239 
241  void addReadyMemInst(const DynInstPtr &ready_inst);
242 
247  void rescheduleMemInst(const DynInstPtr &resched_inst);
248 
250  void replayMemInst(const DynInstPtr &replay_inst);
251 
256  void deferMemInst(const DynInstPtr &deferred_inst);
257 
259  void blockMemInst(const DynInstPtr &blocked_inst);
260 
262  void cacheUnblocked();
263 
265  void violation(const DynInstPtr &store, const DynInstPtr &faulting_load);
266 
271  void squash(ThreadID tid);
272 
274  unsigned getCount(ThreadID tid) { return count[tid]; };
275 
277  void printInsts();
278 
279  private:
281  void doSquash(ThreadID tid);
282 
284  // Various pointers
286 
289 
292 
295 
300 
305 
308 
311 
314 
316  // Instruction lists, ready queues, and ordering
318 
321 
324 
329 
332 
337 
345  struct PqCompare
346  {
347  bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const;
348  };
349 
350  typedef std::priority_queue<
352 
357 
365  std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
366 
367  typedef std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
368 
371  {
372  OpClass queueType;
374  };
375 
384 
386 
389 
394 
396  void addToOrderList(OpClass op_class);
397 
402  void moveToYoungerInst(ListOrderIt age_order_it);
403 
405 
407  // Various parameters
409 
411  SMTQueuePolicy iqPolicy;
412 
415 
418 
420  unsigned count[MaxThreads];
421 
424 
426  unsigned freeEntries;
427 
429  unsigned numEntries;
430 
432  unsigned totalWidth;
433 
435  unsigned numPhysRegs;
436 
439 
444 
447 
455 
457  bool addToDependents(const DynInstPtr &new_inst);
458 
460  void addToProducers(const DynInstPtr &new_inst);
461 
463  void addIfReady(const DynInstPtr &inst);
464 
469  int countInsts();
470 
475  void dumpLists();
476 
480  void dumpInsts();
481 
482  struct IQStats : public statistics::Group
483  {
484  IQStats(CPU *cpu, const unsigned &total_width);
489 
515  // Also include number of instructions rescheduled and replayed.
516 
520  // statistics::VectorDistribution queueResDist;
526  // statistics::VectorDistribution issueDelayDist;
527 
532  // statistics::Vector dist_unissued;
535 
538 
543  } iqStats;
544 
545  public:
546  struct IQIOStats : public statistics::Group
547  {
548  IQIOStats(statistics::Group *parent);
558 
562  } iqIOStats;
563 };
564 
565 } // namespace o3
566 } // namespace gem5
567 
568 #endif //__CPU_O3_INST_QUEUE_HH__
gem5::o3::InstructionQueue::IQStats::miscInstsIssued
statistics::Scalar miscInstsIssued
Stat for number of miscellaneous instructions issued.
Definition: inst_queue.hh:500
gem5::o3::InstructionQueue::readyIt
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Definition: inst_queue.hh:393
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::InstructionQueue::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &resched_inst)
Reschedules a memory instruction.
Definition: inst_queue.cc:1085
gem5::o3::InstructionQueue::addToOrderList
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
Definition: inst_queue.cc:674
gem5::o3::InstructionQueue::maxEntries
unsigned maxEntries[MaxThreads]
Max IQ Entries Per Thread.
Definition: inst_queue.hh:423
gem5::o3::InstructionQueue::resetEntries
void resetEntries()
Resets max entries for all threads.
Definition: inst_queue.cc:487
gem5::o3::InstructionQueue::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: inst_queue.cc:461
gem5::o3::InstructionQueue::issueToExecuteQueue
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
Definition: inst_queue.hh:304
gem5::o3::InstructionQueue::IQStats::statIssuedInstType
statistics::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
Definition: inst_queue.hh:534
gem5::o3::InstructionQueue::IQIOStats::fpAluAccesses
statistics::Scalar fpAluAccesses
Definition: inst_queue.hh:560
gem5::o3::InstructionQueue::IQStats::squashedInstsIssued
statistics::Scalar squashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
Definition: inst_queue.hh:503
gem5::o3::InstructionQueue::countInsts
int countInsts()
Debugging function to count how many entries are in the IQ.
Definition: inst_queue.cc:1451
gem5::o3::InstructionQueue::instsToExecute
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
Definition: inst_queue.hh:323
gem5::statistics::Distribution
A simple distribution stat.
Definition: statistics.hh:2081
gem5::o3::InstructionQueue::IQStats::instsIssued
statistics::Scalar instsIssued
Definition: inst_queue.hh:490
gem5::o3::InstructionQueue::getDeferredMemInstToExecute
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
Definition: inst_queue.cc:1131
op_class.hh
gem5::o3::InstructionQueue::IQIOStats::IQIOStats
IQIOStats(statistics::Group *parent)
Definition: inst_queue.cc:324
gem5::o3::InstructionQueue::regScoreboard
std::vector< bool > regScoreboard
A cache of the recently woken registers.
Definition: inst_queue.hh:454
gem5::o3::InstructionQueue::isFull
bool isFull()
Returns whether or not the IQ is full.
Definition: inst_queue.cc:523
memory
Definition: mem.h:38
gem5::o3::InstructionQueue::queueOnList
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
Definition: inst_queue.hh:388
gem5::o3::InstructionQueue::ReadyInstQueue
std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, PqCompare > ReadyInstQueue
Definition: inst_queue.hh:351
gem5::o3::InstructionQueue::nonSpecInsts
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit.
Definition: inst_queue.hh:365
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::o3::InstructionQueue::getBlockedMemInstToExecute
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
Definition: inst_queue.cc:1145
gem5::o3::InstructionQueue::dcacheInterface
memory::MemInterface * dcacheInterface
Cache interface.
Definition: inst_queue.hh:291
gem5::o3::InstructionQueue::IQStats::issueRate
statistics::Formula issueRate
Number of instructions issued per cycle.
Definition: inst_queue.hh:537
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWrites
statistics::Scalar vecInstQueueWrites
Definition: inst_queue.hh:556
gem5::o3::DynInstPtr
RefCountingPtr< DynInst > DynInstPtr
Definition: dyn_inst_ptr.hh:55
gem5::o3::InstructionQueue::cpu
CPU * cpu
Pointer to the CPU.
Definition: inst_queue.hh:288
gem5::o3::InstructionQueue::commit
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread.
Definition: inst_queue.cc:945
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueWakeupAccesses
statistics::Scalar vecInstQueueWakeupAccesses
Definition: inst_queue.hh:557
gem5::o3::DependencyGraph
Array of linked list that maintains the dependencies between producing instructions and consuming ins...
Definition: dep_graph.hh:77
gem5::o3::InstructionQueue::FUCompletion::freeFU
bool freeFU
Should the FU be added to the list to be freed upon completing this event.
Definition: inst_queue.hh:120
gem5::o3::InstructionQueue::IQStats::squashedInstsExamined
statistics::Scalar squashedInstsExamined
Stat for number of squashed instructions examined when squashing.
Definition: inst_queue.hh:506
gem5::statistics::Vector2d
A 2-Dimensional vecto of scalar stats.
Definition: statistics.hh:2055
gem5::o3::InstructionQueue::IQStats::instsAdded
statistics::Scalar instsAdded
Stat for number of instructions added.
Definition: inst_queue.hh:486
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::o3::InstructionQueue::PqCompare::operator()
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
Definition: inst_queue.cc:1323
gem5::o3::InstructionQueue::IQIOStats::intInstQueueReads
statistics::Scalar intInstQueueReads
Definition: inst_queue.hh:549
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::o3::InstructionQueue::IQIOStats::vecInstQueueReads
statistics::Scalar vecInstQueueReads
Definition: inst_queue.hh:555
std::vector
STL vector class.
Definition: stl.hh:37
gem5::o3::InstructionQueue::numEntries
unsigned numEntries
The number of entries in the instruction queue.
Definition: inst_queue.hh:429
gem5::o3::InstructionQueue::recordProducer
void recordProducer(const DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ.
Definition: inst_queue.hh:214
gem5::o3::MemDepUnit
Memory dependency unit class.
Definition: mem_dep_unit.hh:90
gem5::o3::InstructionQueue::addToDependents
bool addToDependents(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
Definition: inst_queue.cc:1330
gem5::o3::InstructionQueue::cacheUnblocked
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
Definition: inst_queue.cc:1121
gem5::o3::InstructionQueue::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: inst_queue.cc:470
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWakeupAccesses
statistics::Scalar intInstQueueWakeupAccesses
Definition: inst_queue.hh:551
gem5::o3::InstructionQueue::numPhysRegs
unsigned numPhysRegs
The number of physical registers in the CPU.
Definition: inst_queue.hh:435
gem5::o3::InstructionQueue::resetState
void resetState()
Resets all instruction queue state.
Definition: inst_queue.cc:390
gem5::o3::InstructionQueue::setIssueToExecuteQueue
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
Definition: inst_queue.cc:435
gem5::o3::InstructionQueue::FUCompletion::inst
DynInstPtr inst
Executing instruction.
Definition: inst_queue.hh:109
gem5::o3::InstructionQueue::ListOrderEntry::queueType
OpClass queueType
Definition: inst_queue.hh:372
gem5::o3::InstructionQueue::dependGraph
DependencyGraph< DynInstPtr > dependGraph
Definition: inst_queue.hh:404
gem5::o3::InstructionQueue::freeEntries
unsigned freeEntries
Number of free IQ entries left.
Definition: inst_queue.hh:426
gem5::RefCountingPtr< DynInst >
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::InstructionQueue::ListOrderIt
std::list< ListOrderEntry >::iterator ListOrderIt
Definition: inst_queue.hh:385
gem5::o3::InstructionQueue::wakeDependents
int wakeDependents(const DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
Definition: inst_queue.cc:962
gem5::o3::InstructionQueue::IQIOStats::vecAluAccesses
statistics::Scalar vecAluAccesses
Definition: inst_queue.hh:561
gem5::o3::InstructionQueue::iewStage
IEW * iewStage
Pointer to IEW stage.
Definition: inst_queue.hh:294
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
store_set.hh
gem5::o3::InstructionQueue::memDepUnit
MemDepUnit memDepUnit[MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
Definition: inst_queue.hh:299
gem5::o3::InstructionQueue::deferredMemInsts
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress).
Definition: inst_queue.hh:328
gem5::o3::InstructionQueue::iqIOStats
gem5::o3::InstructionQueue::IQIOStats iqIOStats
timebuf.hh
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueReads
statistics::Scalar fpInstQueueReads
Definition: inst_queue.hh:552
comm.hh
gem5::o3::InstructionQueue::InstructionQueue
InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
Constructs an IQ.
Definition: inst_queue.cc:87
gem5::o3::InstructionQueue::addIfReady
void addIfReady(const DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
Definition: inst_queue.cc:1412
gem5::o3::InstructionQueue::FUCompletion::setFreeFU
void setFreeFU()
Definition: inst_queue.hh:129
gem5::o3::InstructionQueue::IQIOStats::intAluAccesses
statistics::Scalar intAluAccesses
Definition: inst_queue.hh:559
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::InstructionQueue::IQStats::squashedOperandsExamined
statistics::Scalar squashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
Definition: inst_queue.hh:510
gem5::memory::MemInterface
General interface to memory device Includes functions and parameters shared across media types.
Definition: mem_interface.hh:77
gem5::o3::InstructionQueue::name
std::string name() const
Returns the name of the IQ.
Definition: inst_queue.cc:171
gem5::o3::InstructionQueue::FUCompletion
FU completion event class.
Definition: inst_queue.hh:105
gem5::o3::InstructionQueue::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
Definition: inst_queue.cc:441
gem5::o3::InstructionQueue::IQStats
Definition: inst_queue.hh:482
gem5::Event
Definition: eventq.hh:251
gem5::o3::InstructionQueue::doSquash
void doSquash(ThreadID tid)
Does the actual squashing.
Definition: inst_queue.cc:1181
gem5::o3::InstructionQueue::IQStats::branchInstsIssued
statistics::Scalar branchInstsIssued
Stat for number of branch instructions issued.
Definition: inst_queue.hh:496
statistics.hh
gem5::o3::InstructionQueue::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: inst_queue.hh:417
gem5::o3::InstructionQueue::IQStats::squashedNonSpecRemoved
statistics::Scalar squashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
Definition: inst_queue.hh:514
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::InstructionQueue::deferMemInst
void deferMemInst(const DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk.
Definition: inst_queue.cc:1104
mem_dep_unit.hh
gem5::o3::InstructionQueue::retryMemInsts
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
Definition: inst_queue.hh:336
gem5::o3::InstructionQueue::commitToIEWDelay
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
Definition: inst_queue.hh:443
gem5::o3::InstructionQueue::totalWidth
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
Definition: inst_queue.hh:432
gem5::o3::InstructionQueue::IQIOStats
Definition: inst_queue.hh:546
gem5::o3::InstructionQueue::numFreeEntries
unsigned numFreeEntries()
Returns total number of free entries.
Definition: inst_queue.cc:509
gem5::o3::InstructionQueue::IQStats::nonSpecInstsAdded
statistics::Scalar nonSpecInstsAdded
Stat for number of non-speculative instructions added.
Definition: inst_queue.hh:488
gem5::o3::InstructionQueue::addToProducers
void addToProducers(const DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
Definition: inst_queue.cc:1377
gem5::o3::InstructionQueue::IQStats::fuBusyRate
statistics::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
Definition: inst_queue.hh:542
gem5::o3::InstructionQueue::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
Definition: inst_queue.hh:310
gem5::o3::InstructionQueue::fuPool
FUPool * fuPool
Function unit pool.
Definition: inst_queue.hh:313
gem5::o3::InstructionQueue::printInsts
void printInsts()
Debug function to print all instructions.
gem5::o3::InstructionQueue::dumpInsts
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
Definition: inst_queue.cc:1499
gem5::o3::InstructionQueue::IQStats::memInstsIssued
statistics::Scalar memInstsIssued
Stat for number of memory instructions issued.
Definition: inst_queue.hh:498
gem5::o3::InstructionQueue::scheduleNonSpec
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
Definition: inst_queue.cc:918
dyn_inst_ptr.hh
gem5::o3::InstructionQueue::processFUCompletion
void processFUCompletion(const DynInstPtr &inst, int fu_idx)
Process FU completion event.
Definition: inst_queue.cc:725
gem5::o3::InstructionQueue::getInstToExecute
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Definition: inst_queue.cc:658
gem5::o3::InstructionQueue::PqCompare
Struct for comparing entries to be added to the priority queue.
Definition: inst_queue.hh:345
gem5::o3::InstructionQueue::IQStats::intInstsIssued
statistics::Scalar intInstsIssued
Stat for number of integer instructions issued.
Definition: inst_queue.hh:492
gem5::o3::InstructionQueue::iqStats
gem5::o3::InstructionQueue::IQStats iqStats
gem5::o3::InstructionQueue::IQIOStats::intInstQueueWrites
statistics::Scalar intInstQueueWrites
Definition: inst_queue.hh:550
gem5::o3::InstructionQueue::insertBarrier
void insertBarrier(const DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly.
Definition: inst_queue.cc:650
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::InstructionQueue::FUCompletion::process
virtual void process()
Definition: inst_queue.cc:74
gem5::o3::InstructionQueue::IQStats::floatInstsIssued
statistics::Scalar floatInstsIssued
Stat for number of floating point instructions issued.
Definition: inst_queue.hh:494
gem5::o3::InstructionQueue::iqPolicy
SMTQueuePolicy iqPolicy
IQ sharing policy for SMT.
Definition: inst_queue.hh:411
gem5::o3::InstructionQueue::squash
void squash(ThreadID tid)
Squashes instructions for a thread.
Definition: inst_queue.cc:1165
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWrites
statistics::Scalar fpInstQueueWrites
Definition: inst_queue.hh:553
gem5::o3::InstructionQueue::~InstructionQueue
~InstructionQueue()
Destructs the IQ.
Definition: inst_queue.cc:161
types.hh
gem5::o3::InstructionQueue::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: inst_queue.hh:102
gem5::o3::InstructionQueue::isDrained
bool isDrained() const
Determine if we are drained.
Definition: inst_queue.cc:449
gem5::o3::InstructionQueue::FUCompletion::description
virtual const char * description() const
Return a C string describing the event.
Definition: inst_queue.cc:82
gem5::o3::InstructionQueue::moveToYoungerInst
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Definition: inst_queue.cc:700
gem5::o3::InstructionQueue::insertNonSpec
void insertNonSpec(const DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
Definition: inst_queue.cc:604
gem5::o3::InstructionQueue::blockedMemInsts
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
Definition: inst_queue.hh:331
gem5::o3::InstructionQueue::addReadyMemInst
void addReadyMemInst(const DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
Definition: inst_queue.cc:1063
gem5::o3::InstructionQueue::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
Definition: inst_queue.cc:429
gem5::o3::InstructionQueue::count
unsigned count[MaxThreads]
Per Thread IQ count.
Definition: inst_queue.hh:420
gem5::o3::InstructionQueue::blockMemInst
void blockMemInst(const DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Definition: inst_queue.cc:1110
gem5::o3::InstructionQueue::IQStats::IQStats
IQStats(CPU *cpu, const unsigned &total_width)
Definition: inst_queue.cc:176
gem5::o3::InstructionQueue::IQStats::statFuBusy
statistics::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
Definition: inst_queue.hh:531
gem5::o3::InstructionQueue::insert
void insert(const DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
Definition: inst_queue.cc:559
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::InstructionQueue::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
Definition: inst_queue.cc:476
gem5::o3::InstructionQueue::IQStats::fuBusy
statistics::Vector fuBusy
Number of times the FU was busy.
Definition: inst_queue.hh:540
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::InstructionQueue::replayMemInst
void replayMemInst(const DynInstPtr &replay_inst)
Replays a memory instruction.
Definition: inst_queue.cc:1098
gem5::o3::InstructionQueue::IQStats::numIssuedDist
statistics::Distribution numIssuedDist
Distribution of number of instructions in the queue.
Definition: inst_queue.hh:522
gem5::o3::InstructionQueue::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Definition: inst_queue.hh:307
gem5::Num_OpClasses
static const OpClass Num_OpClasses
Definition: op_class.hh:108
gem5::o3::InstructionQueue::numThreads
ThreadID numThreads
Number of Total Threads.
Definition: inst_queue.hh:414
gem5::o3::InstructionQueue::scheduleReadyInsts
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute.
Definition: inst_queue.cc:748
gem5::o3::InstructionQueue::NonSpecMapIt
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
Definition: inst_queue.hh:367
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::InstructionQueue::dumpLists
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
Definition: inst_queue.cc:1457
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::InstructionQueue::wbOutstanding
int wbOutstanding
Number of instructions currently in flight to FUs.
Definition: inst_queue.hh:438
gem5::o3::InstructionQueue::IQIOStats::fpInstQueueWakeupAccesses
statistics::Scalar fpInstQueueWakeupAccesses
Definition: inst_queue.hh:554
gem5::o3::InstructionQueue::FUCompletion::iqPtr
InstructionQueue * iqPtr
Pointer back to the instruction queue.
Definition: inst_queue.hh:115
gem5::o3::InstructionQueue::FUCompletion::fuIdx
int fuIdx
Index of the FU used for executing.
Definition: inst_queue.hh:112
limits.hh
gem5::o3::InstructionQueue::squashedSeqNum
InstSeqNum squashedSeqNum[MaxThreads]
The sequence number of the squashed instruction.
Definition: inst_queue.hh:446
gem5::o3::InstructionQueue::ListOrderEntry::oldestInst
InstSeqNum oldestInst
Definition: inst_queue.hh:373
dep_graph.hh
gem5::o3::FUPool
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:75
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::InstructionQueue::listOrder
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
Definition: inst_queue.hh:383
gem5::o3::InstructionQueue::instList
std::list< DynInstPtr > instList[MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
Definition: inst_queue.hh:320
gem5::o3::InstructionQueue::readyInsts
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
Definition: inst_queue.hh:356
gem5::o3::InstructionQueue::violation
void violation(const DynInstPtr &store, const DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Definition: inst_queue.cc:1157
gem5::o3::InstructionQueue::ListOrderEntry
Entry for the list age ordering by op class.
Definition: inst_queue.hh:370
gem5::o3::InstructionQueue::hasReadyInsts
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Definition: inst_queue.cc:543
gem5::o3::InstructionQueue::getCount
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Definition: inst_queue.hh:274
gem5::o3::InstructionQueue::FUCompletion::FUCompletion
FUCompletion(const DynInstPtr &_inst, int fu_idx, InstructionQueue *iq_ptr)
Construct a FU completion event.
Definition: inst_queue.cc:66
eventq.hh

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