gem5 v24.0.0.0
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events.cc
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1/*
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by the University of Cambridge Computer
6 * Laboratory as part of the CTSRD Project, with support from the UK Higher
7 * Education Innovation Fund (HEIF).
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are
11 * met: redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer;
13 * redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution;
16 * neither the name of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
34
35#include <sstream>
36
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "debug/DebugPrintf.hh"
40#include "kern/system_events.hh"
41#include "sim/core.hh"
42#include "sim/system.hh"
43
44namespace gem5
45{
46
47namespace free_bsd
48{
49
50void
51onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
52{
53 // convert parameter to ns
54 if (div)
55 time /= div;
56
57 time *= mul;
58
59 // Currently, only ARM full-system simulation uses UDelayEvents to skip
60 // __delay and __loop_delay functions. One form involves setting quiesce
61 // time to 0 with the assumption that quiesce will not happen. To avoid
62 // the quiesce handling in this case, only execute the quiesce if time > 0.
63 if (time > 0)
65}
66
67} // namespace free_bsd
68} // namespace gem5
ThreadContext is the external interface to all thread state for anything outside of the CPU.
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
T div(T rs1, T rs2)
Definition utility.hh:192
void onUDelay(ThreadContext *tc, uint64_t div, uint64_t mul, uint64_t time)
Definition events.cc:51
Tick ns
nanosecond
Definition core.cc:68
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
Tick curTick()
The universal simulation clock.
Definition cur_tick.hh:46

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