gem5  v21.1.0.2
utility.hh
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1 /*
2  * Copyright (c) 2013 ARM Limited
3  * Copyright (c) 2014-2015 Sven Karlsson
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43 
44 #ifndef __ARCH_RISCV_UTILITY_HH__
45 #define __ARCH_RISCV_UTILITY_HH__
46 
47 #include <cmath>
48 #include <cstdint>
49 #include <sstream>
50 #include <string>
51 
52 #include "arch/riscv/regs/float.hh"
53 #include "arch/riscv/regs/int.hh"
54 #include "base/types.hh"
55 #include "cpu/reg_class.hh"
56 #include "cpu/static_inst.hh"
57 #include "cpu/thread_context.hh"
58 
59 namespace gem5
60 {
61 
62 namespace RiscvISA
63 {
64 
65 template<typename T> inline bool
67 {
68  return false;
69 }
70 
71 template<> inline bool
73 {
74  return std::isnan(val)
75  && (reinterpret_cast<uint32_t&>(val)&0x00400000);
76 }
77 
78 template<> inline bool
80 {
81  return std::isnan(val)
82  && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
83 }
84 
85 template<typename T> inline bool
87 {
88  return false;
89 }
90 
91 template<> inline bool
93 {
94  return std::isnan(val)
95  && (reinterpret_cast<uint32_t&>(val)&0x00200000);
96 }
97 
98 template<> inline bool
100 {
101  return std::isnan(val)
102  && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
103 }
104 
105 inline std::string
107 {
108  if (reg.is(IntRegClass)) {
109  if (reg.index() >= NumIntArchRegs) {
110  /*
111  * This should only happen if a instruction is being speculatively
112  * executed along a not-taken branch, and if that instruction's
113  * width was incorrectly predecoded (i.e., it was predecoded as a
114  * full instruction rather than a compressed one or vice versa).
115  * It also should only happen if a debug flag is on that prints
116  * disassembly information, so rather than panic the incorrect
117  * value is printed for debugging help.
118  */
119  std::stringstream str;
120  str << "?? (x" << reg.index() << ')';
121  return str.str();
122  }
123  return IntRegNames[reg.index()];
124  } else {
125  if (reg.index() >= NumFloatRegs) {
126  std::stringstream str;
127  str << "?? (f" << reg.index() << ')';
128  return str.str();
129  }
130  return FloatRegNames[reg.index()];
131  }
132 }
133 
134 } // namespace RiscvISA
135 } // namespace gem5
136 
137 #endif // __ARCH_RISCV_UTILITY_HH__
gem5::RiscvISA::IntRegNames
const std::vector< std::string > IntRegNames
Definition: int.hh:72
gem5::RiscvISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:93
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
float.hh
gem5::RiscvISA::issignalingnan< double >
bool issignalingnan< double >(double val)
Definition: utility.hh:99
gem5::RiscvISA::isquietnan< double >
bool isquietnan< double >(double val)
Definition: utility.hh:79
gem5::RiscvISA::isquietnan
bool isquietnan(T val)
Definition: utility.hh:66
gem5::RiscvISA::registerName
std::string registerName(RegId reg)
Definition: utility.hh:106
gem5::RiscvISA::isquietnan< float >
bool isquietnan< float >(float val)
Definition: utility.hh:72
gem5::RiscvISA::issignalingnan< float >
bool issignalingnan< float >(float val)
Definition: utility.hh:92
gem5::RiscvISA::NumIntArchRegs
const int NumIntArchRegs
Definition: int.hh:58
static_inst.hh
gem5::RiscvISA::issignalingnan
bool issignalingnan(T val)
Definition: utility.hh:86
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::RiscvISA::FloatRegNames
const std::vector< std::string > FloatRegNames
Definition: float.hh:95
types.hh
reg_class.hh
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
int.hh
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88

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