gem5  v21.1.0.2
thread_context.hh
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41 
42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
44 
45 #include <iostream>
46 #include <string>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/isa.hh"
50 #include "arch/pcstate.hh"
51 #include "arch/vecregs.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/reg_class.hh"
56 
57 namespace gem5
58 {
59 
60 // @todo: Figure out a more architecture independent way to obtain the ITB and
61 // DTB pointers.
62 namespace TheISA
63 {
64  class Decoder;
65 }
66 class BaseCPU;
67 class BaseMMU;
68 class BaseTLB;
69 class CheckerCPU;
70 class Checkpoint;
71 class PortProxy;
72 class Process;
73 class System;
74 class Packet;
75 using PacketPtr = Packet *;
76 
94 {
95  protected:
96  bool useForClone = false;
97 
98  public:
99 
100  bool getUseForClone() { return useForClone; }
101 
102  void setUseForClone(bool new_val) { useForClone = new_val; }
103 
104  enum Status
105  {
109 
113 
117 
122  };
123 
124  virtual ~ThreadContext() { };
125 
126  virtual BaseCPU *getCpuPtr() = 0;
127 
128  virtual int cpuId() const = 0;
129 
130  virtual uint32_t socketId() const = 0;
131 
132  virtual int threadId() const = 0;
133 
134  virtual void setThreadId(int id) = 0;
135 
136  virtual ContextID contextId() const = 0;
137 
138  virtual void setContextId(ContextID id) = 0;
139 
140  virtual BaseMMU *getMMUPtr() = 0;
141 
142  virtual CheckerCPU *getCheckerCpuPtr() = 0;
143 
144  virtual BaseISA *getIsaPtr() = 0;
145 
146  virtual TheISA::Decoder *getDecoderPtr() = 0;
147 
148  virtual System *getSystemPtr() = 0;
149 
150  virtual PortProxy &getVirtProxy() = 0;
151 
152  virtual void sendFunctional(PacketPtr pkt);
153 
160  virtual void initMemProxies(ThreadContext *tc) = 0;
161 
162  virtual Process *getProcessPtr() = 0;
163 
164  virtual void setProcessPtr(Process *p) = 0;
165 
166  virtual Status status() const = 0;
167 
168  virtual void setStatus(Status new_status) = 0;
169 
171  virtual void activate() = 0;
172 
174  virtual void suspend() = 0;
175 
177  virtual void halt() = 0;
178 
180  void quiesce();
181 
183  void quiesceTick(Tick resume);
184 
185  virtual void takeOverFrom(ThreadContext *old_context) = 0;
186 
187  virtual void regStats(const std::string &name) {};
188 
189  virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
190  virtual void descheduleInstCountEvent(Event *event) = 0;
191  virtual Tick getCurrentInstCount() = 0;
192 
193  // Not necessarily the best location for these...
194  // Having an extra function just to read these is obnoxious
195  virtual Tick readLastActivate() = 0;
196  virtual Tick readLastSuspend() = 0;
197 
198  virtual void copyArchRegs(ThreadContext *tc) = 0;
199 
200  virtual void clearArchRegs() = 0;
201 
202  //
203  // New accessors for new decoder.
204  //
205  virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
206 
207  virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
208 
209  virtual const TheISA::VecRegContainer&
210  readVecReg(const RegId& reg) const = 0;
211  virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
212 
213  virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
214 
216  const RegId& reg) const = 0;
218  const RegId& reg) = 0;
219 
220  virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
221 
222  virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
223 
224  virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
225 
226  virtual void setVecReg(const RegId& reg,
227  const TheISA::VecRegContainer& val) = 0;
228 
229  virtual void setVecElem(const RegId& reg, const TheISA::VecElem& val) = 0;
230 
231  virtual void setVecPredReg(const RegId& reg,
232  const TheISA::VecPredRegContainer& val) = 0;
233 
234  virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
235 
236  virtual TheISA::PCState pcState() const = 0;
237 
238  virtual void pcState(const TheISA::PCState &val) = 0;
239 
240  void
242  {
243  TheISA::PCState pc_state = pcState();
244  pc_state.setNPC(val);
245  pcState(pc_state);
246  }
247 
248  virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
249 
250  virtual Addr instAddr() const = 0;
251 
252  virtual Addr nextInstAddr() const = 0;
253 
254  virtual MicroPC microPC() const = 0;
255 
256  virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
257 
258  virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
259 
260  virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
261 
262  virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
263 
264  virtual RegId flattenRegId(const RegId& reg_id) const = 0;
265 
266  // Also not necessarily the best location for these two. Hopefully will go
267  // away once we decide upon where st cond failures goes.
268  virtual unsigned readStCondFailures() const = 0;
269 
270  virtual void setStCondFailures(unsigned sc_failures) = 0;
271 
272  // This function exits the thread context in the CPU and returns
273  // 1 if the CPU has no more active threads (meaning it's OK to exit);
274  // Used in syscall-emulation mode when a thread calls the exit syscall.
275  virtual int exit() { return 1; };
276 
278  static void compare(ThreadContext *one, ThreadContext *two);
279 
292  virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
293  virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
294 
295  virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
296  virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
297 
298  virtual const TheISA::VecRegContainer&
299  readVecRegFlat(RegIndex idx) const = 0;
301  virtual void setVecRegFlat(RegIndex idx,
302  const TheISA::VecRegContainer& val) = 0;
303 
304  virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
305  const ElemIndex& elem_idx) const = 0;
306  virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
307  const TheISA::VecElem& val) = 0;
308 
309  virtual const TheISA::VecPredRegContainer &
310  readVecPredRegFlat(RegIndex idx) const = 0;
312  RegIndex idx) = 0;
313  virtual void setVecPredRegFlat(RegIndex idx,
314  const TheISA::VecPredRegContainer& val) = 0;
315 
316  virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
317  virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
320  // hardware transactional memory
321  virtual void htmAbortTransaction(uint64_t htm_uid,
322  HtmFailureFaultCause cause) = 0;
324  virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
325 };
326 
337 void serialize(const ThreadContext &tc, CheckpointOut &cp);
338 void unserialize(ThreadContext &tc, CheckpointIn &cp);
339 
353 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
354 
355 } // namespace gem5
356 
357 #endif
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const TheISA::PCState &val)=0
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
htm.hh
gem5::ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:59
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:108
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::ThreadContext::readLastSuspend
virtual Tick readLastSuspend()=0
gem5::ThreadContext::getUseForClone
bool getUseForClone()
Definition: thread_context.hh:100
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ThreadContext::readVecElem
virtual const TheISA::VecElem & readVecElem(const RegId &reg) const =0
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::ThreadContext::readVecPredReg
virtual const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const =0
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:104
gem5::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const =0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::ThreadContext::setVecElem
virtual void setVecElem(const RegId &reg, const TheISA::VecElem &val)=0
gem5::ThreadContext::instAddr
virtual Addr instAddr() const =0
gem5::ThreadContext::readVecPredRegFlat
virtual const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const =0
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:187
gem5::ThreadContext::halt
virtual void halt()=0
Set the status to Halted.
gem5::ThreadContext::setUseForClone
void setUseForClone(bool new_val)
Definition: thread_context.hh:102
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
gem5::ThreadContext::setProcessPtr
virtual void setProcessPtr(Process *p)=0
gem5::ThreadContext::getDecoderPtr
virtual TheISA::Decoder * getDecoderPtr()=0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::BaseMMU
Definition: mmu.hh:50
gem5::ThreadContext::status
virtual Status status() const =0
gem5::ThreadContext::getCurrentInstCount
virtual Tick getCurrentInstCount()=0
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::ThreadContext::setThreadId
virtual void setThreadId(int id)=0
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
gem5::ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:151
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::System
Definition: system.hh:77
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:144
gem5::ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
gem5::ThreadContext::flattenRegId
virtual RegId flattenRegId(const RegId &reg_id) const =0
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:112
gem5::Event
Definition: eventq.hh:251
gem5::ps2::one
Bitfield< 3 > one
Definition: types.hh:123
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ThreadContext::getWritableVecPredReg
virtual TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg)=0
gem5::ThreadContext::getWritableVecPredRegFlat
virtual TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx)=0
gem5::ThreadContext::setNPC
void setNPC(Addr val)
Definition: thread_context.hh:241
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::readLastActivate
virtual Tick readLastActivate()=0
gem5::ThreadContext::readVecElemFlat
virtual const TheISA::VecElem & readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const =0
gem5::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::ThreadContext::getWritableVecReg
virtual TheISA::VecRegContainer & getWritableVecReg(const RegId &reg)=0
gem5::BaseCPU
Definition: base.hh:107
gem5::ThreadContext::initMemProxies
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU.
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
gem5::ThreadContext::takeOverFrom
virtual void takeOverFrom(ThreadContext *old_context)=0
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::sendFunctional
virtual void sendFunctional(PacketPtr pkt)
Definition: thread_context.cc:135
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::getHtmCheckpointPtr
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
gem5::ThreadContext::readStCondFailures
virtual unsigned readStCondFailures() const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, const TheISA::VecElem &val)=0
name
const std::string & name()
Definition: trace.cc:49
gem5::ThreadContext::htmAbortTransaction
virtual void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0
gem5::ThreadContext::setVecPredReg
virtual void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val)=0
gem5::ThreadContext::scheduleInstCountEvent
virtual void scheduleInstCountEvent(Event *event, Tick count)=0
gem5::ThreadContext::useForClone
bool useForClone
Definition: thread_context.hh:96
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:67
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
isa.hh
gem5::ThreadContext::suspend
virtual void suspend()=0
Set the status to Suspended.
pc_event.hh
gem5::ThreadContext::descheduleInstCountEvent
virtual void descheduleInstCountEvent(Event *event)=0
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
types.hh
gem5::ThreadContext::getWritableVecRegFlat
virtual TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx)=0
gem5::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.hh:124
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:116
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
reg_class.hh
gem5::ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
gem5::ThreadContext::nextInstAddr
virtual Addr nextInstAddr() const =0
gem5::ThreadContext::microPC
virtual MicroPC microPC() const =0
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)=0
gem5::BaseISA
Definition: isa.hh:54
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
gem5::ThreadContext::setStCondFailures
virtual void setStCondFailures(unsigned sc_failures)=0
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
gem5::ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val)=0
gem5::ThreadContext::readVecRegFlat
virtual const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const =0
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ThreadContext::exit
virtual int exit()
Definition: thread_context.hh:275
gem5::PCEventScope
Definition: pc_event.hh:67
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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