gem5  v21.2.1.1
thread_context.hh
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41 
42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
44 
45 #include <iostream>
46 #include <string>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/isa.hh"
50 #include "arch/generic/pcstate.hh"
51 #include "arch/vecregs.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/reg_class.hh"
56 
57 namespace gem5
58 {
59 
60 // @todo: Figure out a more architecture independent way to obtain the ITB and
61 // DTB pointers.
62 namespace TheISA
63 {
64  class Decoder;
65 }
66 class BaseCPU;
67 class BaseMMU;
68 class BaseTLB;
69 class CheckerCPU;
70 class Checkpoint;
71 class InstDecoder;
72 class PortProxy;
73 class Process;
74 class System;
75 class Packet;
76 using PacketPtr = Packet *;
77 
95 {
96  protected:
97  bool useForClone = false;
98 
99  public:
100 
101  bool getUseForClone() { return useForClone; }
102 
103  void setUseForClone(bool new_val) { useForClone = new_val; }
104 
105  enum Status
106  {
110 
114 
118 
123  };
124 
125  virtual ~ThreadContext() { };
126 
127  virtual BaseCPU *getCpuPtr() = 0;
128 
129  virtual int cpuId() const = 0;
130 
131  virtual uint32_t socketId() const = 0;
132 
133  virtual int threadId() const = 0;
134 
135  virtual void setThreadId(int id) = 0;
136 
137  virtual ContextID contextId() const = 0;
138 
139  virtual void setContextId(ContextID id) = 0;
140 
141  virtual BaseMMU *getMMUPtr() = 0;
142 
143  virtual CheckerCPU *getCheckerCpuPtr() = 0;
144 
145  virtual BaseISA *getIsaPtr() = 0;
146 
147  virtual InstDecoder *getDecoderPtr() = 0;
148 
149  virtual System *getSystemPtr() = 0;
150 
151  virtual void sendFunctional(PacketPtr pkt);
152 
153  virtual Process *getProcessPtr() = 0;
154 
155  virtual void setProcessPtr(Process *p) = 0;
156 
157  virtual Status status() const = 0;
158 
159  virtual void setStatus(Status new_status) = 0;
160 
162  virtual void activate() = 0;
163 
165  virtual void suspend() = 0;
166 
168  virtual void halt() = 0;
169 
171  void quiesce();
172 
174  void quiesceTick(Tick resume);
175 
176  virtual void takeOverFrom(ThreadContext *old_context) = 0;
177 
178  virtual void regStats(const std::string &name) {};
179 
180  virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
181  virtual void descheduleInstCountEvent(Event *event) = 0;
182  virtual Tick getCurrentInstCount() = 0;
183 
184  // Not necessarily the best location for these...
185  // Having an extra function just to read these is obnoxious
186  virtual Tick readLastActivate() = 0;
187  virtual Tick readLastSuspend() = 0;
188 
189  virtual void copyArchRegs(ThreadContext *tc) = 0;
190 
191  virtual void clearArchRegs() = 0;
192 
193  //
194  // New accessors for new decoder.
195  //
196  virtual RegVal readIntReg(RegIndex reg_idx) const = 0;
197 
198  virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
199 
200  virtual const TheISA::VecRegContainer&
201  readVecReg(const RegId& reg) const = 0;
202  virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
203 
204  virtual RegVal readVecElem(const RegId& reg) const = 0;
205 
207  const RegId& reg) const = 0;
209  const RegId& reg) = 0;
210 
211  virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
212 
213  virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0;
214 
215  virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
216 
217  virtual void setVecReg(const RegId& reg,
218  const TheISA::VecRegContainer& val) = 0;
219 
220  virtual void setVecElem(const RegId& reg, RegVal val) = 0;
221 
222  virtual void setVecPredReg(const RegId& reg,
223  const TheISA::VecPredRegContainer& val) = 0;
224 
225  virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
226 
227  virtual const PCStateBase &pcState() const = 0;
228 
229  virtual void pcState(const PCStateBase &val) = 0;
230  void
232  {
233  std::unique_ptr<PCStateBase> new_pc(getIsaPtr()->newPCState(addr));
234  pcState(*new_pc);
235  }
236 
237  virtual void pcStateNoRecord(const PCStateBase &val) = 0;
238 
239  virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
240 
241  virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
242 
243  virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
244 
245  virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
246 
247  virtual RegId flattenRegId(const RegId& reg_id) const = 0;
248 
249  // Also not necessarily the best location for these two. Hopefully will go
250  // away once we decide upon where st cond failures goes.
251  virtual unsigned readStCondFailures() const = 0;
252 
253  virtual void setStCondFailures(unsigned sc_failures) = 0;
254 
255  // This function exits the thread context in the CPU and returns
256  // 1 if the CPU has no more active threads (meaning it's OK to exit);
257  // Used in syscall-emulation mode when a thread calls the exit syscall.
258  virtual int exit() { return 1; };
259 
261  static void compare(ThreadContext *one, ThreadContext *two);
262 
275  virtual RegVal readIntRegFlat(RegIndex idx) const = 0;
276  virtual void setIntRegFlat(RegIndex idx, RegVal val) = 0;
277 
278  virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
279  virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
280 
281  virtual const TheISA::VecRegContainer&
282  readVecRegFlat(RegIndex idx) const = 0;
284  virtual void setVecRegFlat(RegIndex idx,
285  const TheISA::VecRegContainer& val) = 0;
286 
287  virtual RegVal readVecElemFlat(RegIndex idx,
288  const ElemIndex& elem_idx) const = 0;
289  virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
290  RegVal val) = 0;
291 
292  virtual const TheISA::VecPredRegContainer &
293  readVecPredRegFlat(RegIndex idx) const = 0;
295  RegIndex idx) = 0;
296  virtual void setVecPredRegFlat(RegIndex idx,
297  const TheISA::VecPredRegContainer& val) = 0;
298 
299  virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
300  virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
303  // hardware transactional memory
304  virtual void htmAbortTransaction(uint64_t htm_uid,
305  HtmFailureFaultCause cause) = 0;
307  virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
308 };
309 
320 void serialize(const ThreadContext &tc, CheckpointOut &cp);
321 void unserialize(ThreadContext &tc, CheckpointIn &cp);
322 
336 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
337 
338 } // namespace gem5
339 
340 #endif
gem5::ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
htm.hh
gem5::ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:59
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::ThreadContext::readLastSuspend
virtual Tick readLastSuspend()=0
gem5::ThreadContext::getUseForClone
bool getUseForClone()
Definition: thread_context.hh:101
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::ThreadContext::readVecPredReg
virtual const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const =0
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::pcState
void pcState(Addr addr)
Definition: thread_context.hh:231
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const =0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::ThreadContext::readVecPredRegFlat
virtual const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const =0
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:178
gem5::ThreadContext::halt
virtual void halt()=0
Set the status to Halted.
gem5::ThreadContext::setUseForClone
void setUseForClone(bool new_val)
Definition: thread_context.hh:103
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
gem5::ThreadContext::setProcessPtr
virtual void setProcessPtr(Process *p)=0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::BaseMMU
Definition: mmu.hh:53
gem5::ThreadContext::status
virtual Status status() const =0
gem5::ThreadContext::getCurrentInstCount
virtual Tick getCurrentInstCount()=0
gem5::ThreadContext::setThreadId
virtual void setThreadId(int id)=0
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
gem5::ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:151
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::ThreadContext::setVecElemFlat
virtual void setVecElemFlat(RegIndex idx, const ElemIndex &elem_idx, RegVal val)=0
gem5::System
Definition: system.hh:75
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:144
gem5::ThreadContext::flattenRegId
virtual RegId flattenRegId(const RegId &reg_id) const =0
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::Event
Definition: eventq.hh:251
gem5::ThreadContext::readVecElemFlat
virtual RegVal readVecElemFlat(RegIndex idx, const ElemIndex &elem_idx) const =0
gem5::ps2::one
Bitfield< 3 > one
Definition: types.hh:123
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::ThreadContext::getWritableVecPredReg
virtual TheISA::VecPredRegContainer & getWritableVecPredReg(const RegId &reg)=0
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::ThreadContext::getWritableVecPredRegFlat
virtual TheISA::VecPredRegContainer & getWritableVecPredRegFlat(RegIndex idx)=0
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::readLastActivate
virtual Tick readLastActivate()=0
gem5::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::getWritableVecReg
virtual TheISA::VecRegContainer & getWritableVecReg(const RegId &reg)=0
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::ThreadContext::setFloatReg
virtual void setFloatReg(RegIndex reg_idx, RegVal val)=0
gem5::ThreadContext::takeOverFrom
virtual void takeOverFrom(ThreadContext *old_context)=0
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::ThreadContext::sendFunctional
virtual void sendFunctional(PacketPtr pkt)
Definition: thread_context.cc:135
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::getHtmCheckpointPtr
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
gem5::ThreadContext::readStCondFailures
virtual unsigned readStCondFailures() const =0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
name
const std::string & name()
Definition: trace.cc:49
gem5::ThreadContext::htmAbortTransaction
virtual void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0
gem5::ThreadContext::setVecPredReg
virtual void setVecPredReg(const RegId &reg, const TheISA::VecPredRegContainer &val)=0
gem5::ThreadContext::scheduleInstCountEvent
virtual void scheduleInstCountEvent(Event *event, Tick count)=0
gem5::ThreadContext::useForClone
bool useForClone
Definition: thread_context.hh:97
gem5::ThreadContext::readVecElem
virtual RegVal readVecElem(const RegId &reg) const =0
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:68
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const PCStateBase &val)=0
pcstate.hh
isa.hh
gem5::ThreadContext::suspend
virtual void suspend()=0
Set the status to Suspended.
pc_event.hh
gem5::ThreadContext::descheduleInstCountEvent
virtual void descheduleInstCountEvent(Event *event)=0
types.hh
gem5::ThreadContext::getWritableVecRegFlat
virtual TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx)=0
gem5::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.hh:125
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:117
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
reg_class.hh
gem5::ThreadContext::setVecElem
virtual void setVecElem(const RegId &reg, RegVal val)=0
gem5::ThreadContext::setCCReg
virtual void setCCReg(RegIndex reg_idx, RegVal val)=0
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)=0
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
gem5::ThreadContext::setStCondFailures
virtual void setStCondFailures(unsigned sc_failures)=0
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::ThreadContext::setVecReg
virtual void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)=0
gem5::ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val)=0
gem5::ThreadContext::readVecRegFlat
virtual const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const =0
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ThreadContext::exit
virtual int exit()
Definition: thread_context.hh:258
gem5::PCEventScope
Definition: pc_event.hh:67
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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