42#ifndef __CPU_THREAD_CONTEXT_HH__
43#define __CPU_THREAD_CONTEXT_HH__
203 std::unique_ptr<PCStateBase> new_pc(
getIsaPtr()->newPCState(
addr));
226 virtual int exit() {
return 1; };
Generic definitions for hardware transactional memory.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Register ID: describe an architectural register with its class and index.
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void activate()=0
Set the status to Active.
virtual RegVal readMiscReg(RegIndex misc_reg)=0
virtual void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
virtual void pcStateNoRecord(const PCStateBase &val)=0
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
virtual void setStatus(Status new_status)=0
virtual RegVal getReg(const RegId ®) const
virtual uint32_t socketId() const =0
virtual void descheduleInstCountEvent(Event *event)=0
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual System * getSystemPtr()=0
virtual void clearArchRegs()=0
virtual void regStats(const std::string &name)
virtual void setProcessPtr(Process *p)=0
virtual void copyArchRegs(ThreadContext *tc)=0
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
virtual BaseISA * getIsaPtr() const =0
virtual void halt()=0
Set the status to Halted.
virtual Tick getCurrentInstCount()=0
virtual BaseCPU * getCpuPtr()=0
virtual void scheduleInstCountEvent(Event *event, Tick count)=0
virtual void takeOverFrom(ThreadContext *old_context)=0
virtual Tick readLastActivate()=0
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
virtual Tick readLastSuspend()=0
virtual void pcState(const PCStateBase &val)=0
virtual void setReg(const RegId ®, RegVal val)
void quiesce()
Quiesce thread context.
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
virtual CheckerCPU * getCheckerCpuPtr()=0
@ Halted
Permanently shut down.
@ Halting
Trying to exit and waiting for an event to completely exit.
@ Suspended
Temporarily inactive.
virtual InstDecoder * getDecoderPtr()=0
virtual void getReg(const RegId ®, void *val) const =0
virtual void * getWritableReg(const RegId ®)=0
virtual void setStCondFailures(unsigned sc_failures)=0
virtual unsigned readStCondFailures() const =0
virtual const PCStateBase & pcState() const =0
virtual int threadId() const =0
virtual Status status() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual BaseMMU * getMMUPtr()=0
virtual void setReg(const RegId ®, const void *val)=0
virtual Process * getProcessPtr()=0
virtual ContextID contextId() const =0
virtual void sendFunctional(PacketPtr pkt)
virtual void setThreadId(int id)=0
virtual void suspend()=0
Set the status to Suspended.
virtual void setContextId(ContextID id)=0
void setUseForClone(bool new_val)
virtual int cpuId() const =0
ProbePointArg< PacketInfo > Packet
Packet probe point.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
std::ostream CheckpointOut
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void unserialize(ThreadContext &tc, CheckpointIn &cp)
uint64_t Tick
Tick count type.
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
int ContextID
Globally unique thread context ID.
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
const std::string & name()