gem5  v22.0.0.2
thread_context.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
44 
45 #include <iostream>
46 #include <string>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/isa.hh"
50 #include "arch/generic/pcstate.hh"
51 #include "arch/vecregs.hh"
52 #include "base/types.hh"
53 #include "config/the_isa.hh"
54 #include "cpu/pc_event.hh"
55 #include "cpu/reg_class.hh"
56 
57 namespace gem5
58 {
59 
60 // @todo: Figure out a more architecture independent way to obtain the ITB and
61 // DTB pointers.
62 namespace TheISA
63 {
64  class Decoder;
65 }
66 class BaseCPU;
67 class BaseMMU;
68 class BaseTLB;
69 class CheckerCPU;
70 class Checkpoint;
71 class InstDecoder;
72 class PortProxy;
73 class Process;
74 class System;
75 class Packet;
76 using PacketPtr = Packet *;
77 
95 {
96  protected:
97  bool useForClone = false;
98 
99  public:
100 
101  bool getUseForClone() { return useForClone; }
102 
103  void setUseForClone(bool new_val) { useForClone = new_val; }
104 
105  enum Status
106  {
110 
114 
118 
123  };
124 
125  virtual ~ThreadContext() { };
126 
127  virtual BaseCPU *getCpuPtr() = 0;
128 
129  virtual int cpuId() const = 0;
130 
131  virtual uint32_t socketId() const = 0;
132 
133  virtual int threadId() const = 0;
134 
135  virtual void setThreadId(int id) = 0;
136 
137  virtual ContextID contextId() const = 0;
138 
139  virtual void setContextId(ContextID id) = 0;
140 
141  virtual BaseMMU *getMMUPtr() = 0;
142 
143  virtual CheckerCPU *getCheckerCpuPtr() = 0;
144 
145  virtual BaseISA *getIsaPtr() const = 0;
146 
147  virtual InstDecoder *getDecoderPtr() = 0;
148 
149  virtual System *getSystemPtr() = 0;
150 
151  virtual void sendFunctional(PacketPtr pkt);
152 
153  virtual Process *getProcessPtr() = 0;
154 
155  virtual void setProcessPtr(Process *p) = 0;
156 
157  virtual Status status() const = 0;
158 
159  virtual void setStatus(Status new_status) = 0;
160 
162  virtual void activate() = 0;
163 
165  virtual void suspend() = 0;
166 
168  virtual void halt() = 0;
169 
171  void quiesce();
172 
174  void quiesceTick(Tick resume);
175 
176  virtual void takeOverFrom(ThreadContext *old_context) = 0;
177 
178  virtual void regStats(const std::string &name) {};
179 
180  virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
181  virtual void descheduleInstCountEvent(Event *event) = 0;
182  virtual Tick getCurrentInstCount() = 0;
183 
184  // Not necessarily the best location for these...
185  // Having an extra function just to read these is obnoxious
186  virtual Tick readLastActivate() = 0;
187  virtual Tick readLastSuspend() = 0;
188 
189  virtual void copyArchRegs(ThreadContext *tc) = 0;
190 
191  virtual void clearArchRegs() = 0;
192 
193  //
194  // New accessors for new decoder.
195  //
196  virtual RegVal getReg(const RegId &reg) const;
197  virtual void getReg(const RegId &reg, void *val) const;
198  virtual void *getWritableReg(const RegId &reg);
199 
200  virtual void setReg(const RegId &reg, RegVal val);
201  virtual void setReg(const RegId &reg, const void *val);
202 
203  RegVal
204  readIntReg(RegIndex reg_idx) const
205  {
206  return getReg(RegId(IntRegClass, reg_idx));
207  }
208 
209  RegVal
210  readFloatReg(RegIndex reg_idx) const
211  {
212  return getReg(RegId(FloatRegClass, reg_idx));
213  }
214 
216  readVecReg(const RegId &reg) const
217  {
219  getReg(reg, &val);
220  return val;
221  }
224  {
226  }
227 
228  RegVal
229  readVecElem(const RegId& reg) const
230  {
231  return getReg(reg);
232  }
233 
234  RegVal
235  readCCReg(RegIndex reg_idx) const
236  {
237  return getReg(RegId(CCRegClass, reg_idx));
238  }
239 
240  void
242  {
243  setReg(RegId(IntRegClass, reg_idx), val);
244  }
245 
246  void
248  {
249  setReg(RegId(FloatRegClass, reg_idx), val);
250  }
251 
252  void
254  {
255  setReg(reg, &val);
256  }
257 
258  void
260  {
261  setReg(reg, val);
262  }
263 
264  void
266  {
267  setReg(RegId(CCRegClass, reg_idx), val);
268  }
269 
270  virtual const PCStateBase &pcState() const = 0;
271 
272  virtual void pcState(const PCStateBase &val) = 0;
273  void
275  {
276  std::unique_ptr<PCStateBase> new_pc(getIsaPtr()->newPCState(addr));
277  pcState(*new_pc);
278  }
279 
280  virtual void pcStateNoRecord(const PCStateBase &val) = 0;
281 
282  virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
283 
284  virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
285 
286  virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
287 
288  virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
289 
290  virtual RegId flattenRegId(const RegId& reg_id) const = 0;
291 
292  // Also not necessarily the best location for these two. Hopefully will go
293  // away once we decide upon where st cond failures goes.
294  virtual unsigned readStCondFailures() const = 0;
295 
296  virtual void setStCondFailures(unsigned sc_failures) = 0;
297 
298  // This function exits the thread context in the CPU and returns
299  // 1 if the CPU has no more active threads (meaning it's OK to exit);
300  // Used in syscall-emulation mode when a thread calls the exit syscall.
301  virtual int exit() { return 1; };
302 
304  static void compare(ThreadContext *one, ThreadContext *two);
305 
318  virtual RegVal getRegFlat(const RegId &reg) const;
319  virtual void getRegFlat(const RegId &reg, void *val) const = 0;
320  virtual void *getWritableRegFlat(const RegId &reg) = 0;
321 
322  virtual void setRegFlat(const RegId &reg, RegVal val);
323  virtual void setRegFlat(const RegId &reg, const void *val) = 0;
324 
325  RegVal
327  {
328  return getRegFlat(RegId(IntRegClass, idx));
329  }
330  void
332  {
334  }
335 
336  RegVal
338  {
339  return getRegFlat(RegId(FloatRegClass, idx));
340  }
341  void
343  {
345  }
346 
349  {
351  getRegFlat(RegId(VecRegClass, idx), &val);
352  return val;
353  }
356  {
357  return *(TheISA::VecRegContainer *)
359  }
360  void
362  {
363  setRegFlat(RegId(VecRegClass, idx), &val);
364  }
365 
366  RegVal
368  {
369  return getRegFlat(RegId(VecElemClass, idx));
370  }
371  void
373  {
375  }
376 
377  RegVal
379  {
380  return getRegFlat(RegId(CCRegClass, idx));
381  }
382  void
384  {
385  setRegFlat(RegId(CCRegClass, idx), val);
386  }
389  // hardware transactional memory
390  virtual void htmAbortTransaction(uint64_t htm_uid,
391  HtmFailureFaultCause cause) = 0;
393  virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
394 };
395 
406 void serialize(const ThreadContext &tc, CheckpointOut &cp);
407 void unserialize(ThreadContext &tc, CheckpointIn &cp);
408 
422 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
423 
424 } // namespace gem5
425 
426 #endif
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:264
htm.hh
gem5::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:331
gem5::ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:61
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:109
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::ThreadContext::readLastSuspend
virtual Tick readLastSuspend()=0
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
gem5::ThreadContext::getUseForClone
bool getUseForClone()
Definition: thread_context.hh:101
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ThreadContext::readVecRegFlat
TheISA::VecRegContainer readVecRegFlat(RegIndex idx) const
Definition: thread_context.hh:348
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:63
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
gem5::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const
Definition: thread_context.hh:326
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::ThreadContext::getMMUPtr
virtual BaseMMU * getMMUPtr()=0
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::ThreadContext::pcState
void pcState(Addr addr)
Definition: thread_context.hh:274
gem5::MipsISA::event
Bitfield< 10, 5 > event
Definition: pra_constants.hh:300
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ThreadContext::Status
Status
Definition: thread_context.hh:105
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
gem5::ThreadContext::activate
virtual void activate()=0
Set the status to Active.
gem5::ThreadContext::getRegFlat
virtual RegVal getRegFlat(const RegId &reg) const
Flat register interfaces.
Definition: thread_context.cc:201
gem5::ThreadContext::getWritableReg
virtual void * getWritableReg(const RegId &reg)
Definition: thread_context.cc:177
gem5::ThreadContext::regStats
virtual void regStats(const std::string &name)
Definition: thread_context.hh:178
gem5::ThreadContext::halt
virtual void halt()=0
Set the status to Halted.
gem5::ThreadContext::setUseForClone
void setUseForClone(bool new_val)
Definition: thread_context.hh:103
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
gem5::ThreadContext::setCCReg
void setCCReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:265
gem5::ThreadContext::getWritableRegFlat
virtual void * getWritableRegFlat(const RegId &reg)=0
gem5::ThreadContext::setProcessPtr
virtual void setProcessPtr(Process *p)=0
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::BaseMMU
Definition: mmu.hh:53
gem5::ThreadContext::status
virtual Status status() const =0
gem5::ThreadContext::getCurrentInstCount
virtual Tick getCurrentInstCount()=0
gem5::ThreadContext::setThreadId
virtual void setThreadId(int id)=0
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
gem5::ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:165
gem5::ThreadContext::setHtmCheckpointPtr
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
gem5::System
Definition: system.hh:75
gem5::ThreadContext::socketId
virtual uint32_t socketId() const =0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:158
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ThreadContext::flattenRegId
virtual RegId flattenRegId(const RegId &reg_id) const =0
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
gem5::ThreadContext::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(const RegId &reg)
Definition: thread_context.hh:223
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:113
gem5::Event
Definition: eventq.hh:251
gem5::ps2::one
Bitfield< 3 > one
Definition: types.hh:123
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::CheckerCPU
CheckerCPU class.
Definition: cpu.hh:84
gem5::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const
Definition: thread_context.hh:378
gem5::ThreadContext::readLastActivate
virtual Tick readLastActivate()=0
gem5::ThreadContext::readVecReg
TheISA::VecRegContainer readVecReg(const RegId &reg) const
Definition: thread_context.hh:216
gem5::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:383
gem5::ThreadContext::setVecElemFlat
void setVecElemFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:372
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::ThreadContext::getWritableVecRegFlat
TheISA::VecRegContainer & getWritableVecRegFlat(RegIndex idx)
Definition: thread_context.hh:355
gem5::ThreadContext::takeOverFrom
virtual void takeOverFrom(ThreadContext *old_context)=0
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
gem5::ThreadContext::sendFunctional
virtual void sendFunctional(PacketPtr pkt)
Definition: thread_context.cc:149
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::setRegFlat
virtual void setRegFlat(const RegId &reg, RegVal val)
Definition: thread_context.cc:209
gem5::ThreadContext::getHtmCheckpointPtr
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
gem5::ThreadContext::readStCondFailures
virtual unsigned readStCondFailures() const =0
gem5::ThreadContext::readVecElemFlat
RegVal readVecElemFlat(RegIndex idx) const
Definition: thread_context.hh:367
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
gem5::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const
Definition: thread_context.hh:337
name
const std::string & name()
Definition: trace.cc:49
gem5::ThreadContext::htmAbortTransaction
virtual void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0
gem5::ThreadContext::scheduleInstCountEvent
virtual void scheduleInstCountEvent(Event *event, Tick count)=0
gem5::ThreadContext::useForClone
bool useForClone
Definition: thread_context.hh:97
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Process
Definition: process.hh:68
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::ThreadContext::pcStateNoRecord
virtual void pcStateNoRecord(const PCStateBase &val)=0
pcstate.hh
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
isa.hh
gem5::ThreadContext::suspend
virtual void suspend()=0
Set the status to Suspended.
gem5::ThreadContext::setVecElem
void setVecElem(const RegId &reg, RegVal val)
Definition: thread_context.hh:259
pc_event.hh
gem5::ThreadContext::descheduleInstCountEvent
virtual void descheduleInstCountEvent(Event *event)=0
types.hh
gem5::ThreadContext::setVecReg
void setVecReg(const RegId &reg, const TheISA::VecRegContainer &val)
Definition: thread_context.hh:253
gem5::ThreadContext::~ThreadContext
virtual ~ThreadContext()
Definition: thread_context.hh:125
gem5::ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:117
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
reg_class.hh
gem5::ThreadContext::readVecElem
RegVal readVecElem(const RegId &reg) const
Definition: thread_context.hh:229
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ThreadContext::clearArchRegs
virtual void clearArchRegs()=0
gem5::ThreadContext::threadId
virtual int threadId() const =0
gem5::ThreadContext::setFloatReg
void setFloatReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:247
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::BaseISA
Definition: isa.hh:57
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ThreadContext::setStCondFailures
virtual void setStCondFailures(unsigned sc_failures)=0
gem5::ThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const
Definition: thread_context.hh:235
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)
Definition: thread_context.hh:361
gem5::ThreadContext::getCheckerCpuPtr
virtual CheckerCPU * getCheckerCpuPtr()=0
gem5::ThreadContext::exit
virtual int exit()
Definition: thread_context.hh:301
gem5::PCEventScope
Definition: pc_event.hh:67
gem5::ThreadContext::setIntReg
void setIntReg(RegIndex reg_idx, RegVal val)
Definition: thread_context.hh:241
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:342

Generated on Thu Jul 28 2022 13:32:22 for gem5 by doxygen 1.8.17