gem5  v22.1.0.0
thread_context.hh
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41 
42 #ifndef __CPU_THREAD_CONTEXT_HH__
43 #define __CPU_THREAD_CONTEXT_HH__
44 
45 #include <iostream>
46 #include <string>
47 
48 #include "arch/generic/htm.hh"
49 #include "arch/generic/isa.hh"
50 #include "arch/generic/pcstate.hh"
51 #include "base/types.hh"
52 #include "cpu/pc_event.hh"
53 #include "cpu/reg_class.hh"
54 
55 namespace gem5
56 {
57 
58 // @todo: Figure out a more architecture independent way to obtain the ITB and
59 // DTB pointers.
60 class BaseCPU;
61 class BaseMMU;
62 class BaseTLB;
63 class CheckerCPU;
64 class Checkpoint;
65 class InstDecoder;
66 class PortProxy;
67 class Process;
68 class System;
69 class Packet;
70 using PacketPtr = Packet *;
71 
89 {
90  protected:
91  bool useForClone = false;
92 
93  public:
94 
95  bool getUseForClone() { return useForClone; }
96 
97  void setUseForClone(bool new_val) { useForClone = new_val; }
98 
99  enum Status
100  {
104 
108 
112 
116  Halted
117  };
118 
119  virtual ~ThreadContext() { };
120 
121  virtual BaseCPU *getCpuPtr() = 0;
122 
123  virtual int cpuId() const = 0;
124 
125  virtual uint32_t socketId() const = 0;
126 
127  virtual int threadId() const = 0;
128 
129  virtual void setThreadId(int id) = 0;
130 
131  virtual ContextID contextId() const = 0;
132 
133  virtual void setContextId(ContextID id) = 0;
134 
135  virtual BaseMMU *getMMUPtr() = 0;
136 
137  virtual CheckerCPU *getCheckerCpuPtr() = 0;
138 
139  virtual BaseISA *getIsaPtr() const = 0;
140 
141  virtual InstDecoder *getDecoderPtr() = 0;
142 
143  virtual System *getSystemPtr() = 0;
144 
145  virtual void sendFunctional(PacketPtr pkt);
146 
147  virtual Process *getProcessPtr() = 0;
148 
149  virtual void setProcessPtr(Process *p) = 0;
150 
151  virtual Status status() const = 0;
152 
153  virtual void setStatus(Status new_status) = 0;
154 
156  virtual void activate() = 0;
157 
159  virtual void suspend() = 0;
160 
162  virtual void halt() = 0;
163 
165  void quiesce();
166 
168  void quiesceTick(Tick resume);
169 
170  virtual void takeOverFrom(ThreadContext *old_context) = 0;
171 
172  virtual void regStats(const std::string &name) {};
173 
176  virtual Tick getCurrentInstCount() = 0;
177 
178  // Not necessarily the best location for these...
179  // Having an extra function just to read these is obnoxious
180  virtual Tick readLastActivate() = 0;
181  virtual Tick readLastSuspend() = 0;
182 
183  virtual void copyArchRegs(ThreadContext *tc) = 0;
184 
185  virtual void clearArchRegs() = 0;
186 
187  //
188  // New accessors for new decoder.
189  //
190  virtual RegVal getReg(const RegId &reg) const;
191  virtual void getReg(const RegId &reg, void *val) const = 0;
192  virtual void *getWritableReg(const RegId &reg) = 0;
193 
194  virtual void setReg(const RegId &reg, RegVal val);
195  virtual void setReg(const RegId &reg, const void *val) = 0;
196 
197  virtual const PCStateBase &pcState() const = 0;
198 
199  virtual void pcState(const PCStateBase &val) = 0;
200  void
202  {
203  std::unique_ptr<PCStateBase> new_pc(getIsaPtr()->newPCState(addr));
204  pcState(*new_pc);
205  }
206 
207  virtual void pcStateNoRecord(const PCStateBase &val) = 0;
208 
209  virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
210 
211  virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
212 
213  virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
214 
215  virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
216 
217  // Also not necessarily the best location for these two. Hopefully will go
218  // away once we decide upon where st cond failures goes.
219  virtual unsigned readStCondFailures() const = 0;
220 
221  virtual void setStCondFailures(unsigned sc_failures) = 0;
222 
223  // This function exits the thread context in the CPU and returns
224  // 1 if the CPU has no more active threads (meaning it's OK to exit);
225  // Used in syscall-emulation mode when a thread calls the exit syscall.
226  virtual int exit() { return 1; };
227 
229  static void compare(ThreadContext *one, ThreadContext *two);
230 
231  // hardware transactional memory
232  virtual void htmAbortTransaction(uint64_t htm_uid,
233  HtmFailureFaultCause cause) = 0;
236 };
237 
248 void serialize(const ThreadContext &tc, CheckpointOut &cp);
249 void unserialize(ThreadContext &tc, CheckpointIn &cp);
250 
264 void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
265 
266 } // namespace gem5
267 
268 #endif
Generic definitions for hardware transactional memory.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
CheckerCPU class.
Definition: cpu.hh:85
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void activate()=0
Set the status to Active.
virtual void * getWritableReg(const RegId &reg)=0
virtual RegVal readMiscReg(RegIndex misc_reg)=0
virtual void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)=0
virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt)=0
virtual void pcStateNoRecord(const PCStateBase &val)=0
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
virtual void setStatus(Status new_status)=0
virtual RegVal getReg(const RegId &reg) const
virtual uint32_t socketId() const =0
virtual void descheduleInstCountEvent(Event *event)=0
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
virtual const PCStateBase & pcState() const =0
virtual void clearArchRegs()=0
virtual System * getSystemPtr()=0
virtual void regStats(const std::string &name)
virtual void setProcessPtr(Process *p)=0
virtual void copyArchRegs(ThreadContext *tc)=0
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
virtual void halt()=0
Set the status to Halted.
virtual Tick getCurrentInstCount()=0
virtual BaseISA * getIsaPtr() const =0
virtual CheckerCPU * getCheckerCpuPtr()=0
virtual void scheduleInstCountEvent(Event *event, Tick count)=0
virtual void takeOverFrom(ThreadContext *old_context)=0
virtual Tick readLastActivate()=0
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
virtual Tick readLastSuspend()=0
virtual void pcState(const PCStateBase &val)=0
virtual void setReg(const RegId &reg, RegVal val)
void quiesce()
Quiesce thread context.
@ Halted
Permanently shut down.
@ Halting
Trying to exit and waiting for an event to completely exit.
@ Suspended
Temporarily inactive.
virtual void getReg(const RegId &reg, void *val) const =0
void pcState(Addr addr)
virtual InstDecoder * getDecoderPtr()=0
virtual BaseCPU * getCpuPtr()=0
virtual void setStCondFailures(unsigned sc_failures)=0
virtual unsigned readStCondFailures() const =0
virtual int threadId() const =0
virtual Status status() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual BaseHTMCheckpointPtr & getHtmCheckpointPtr()=0
virtual void setReg(const RegId &reg, const void *val)=0
virtual ContextID contextId() const =0
virtual void sendFunctional(PacketPtr pkt)
virtual void setThreadId(int id)=0
virtual void suspend()=0
Set the status to Suspended.
virtual Process * getProcessPtr()=0
virtual BaseMMU * getMMUPtr()=0
virtual void setContextId(ContextID id)=0
void setUseForClone(bool new_val)
virtual int cpuId() const =0
Bitfield< 10, 5 > event
Bitfield< 54 > p
Definition: pagetable.hh:70
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 63 > val
Definition: misc.hh:776
Bitfield< 3 > addr
Definition: types.hh:84
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
Bitfield< 3 > one
Definition: types.hh:123
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
std::ostream CheckpointOut
Definition: serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
void unserialize(ThreadContext &tc, CheckpointIn &cp)
uint64_t Tick
Tick count type.
Definition: types.hh:58
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
uint64_t RegVal
Definition: types.hh:173
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
HtmFailureFaultCause
Definition: htm.hh:48
const std::string & name()
Definition: trace.cc:49

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