gem5  v22.0.0.2
thread_context.cc
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41 
42 #include "cpu/thread_context.hh"
43 
44 #include <vector>
45 
47 #include "base/logging.hh"
48 #include "base/trace.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/base.hh"
51 #include "debug/Context.hh"
52 #include "debug/Quiesce.hh"
53 #include "mem/port.hh"
54 #include "params/BaseCPU.hh"
55 #include "sim/full_system.hh"
56 
57 namespace gem5
58 {
59 
60 void
62 {
63  const auto &regClasses = one->getIsaPtr()->regClasses();
64 
65  DPRINTF(Context, "Comparing thread contexts\n");
66 
67  // First loop through the integer registers.
68  for (int i = 0; i < regClasses.at(IntRegClass).numRegs(); ++i) {
69  RegVal t1 = one->readIntReg(i);
70  RegVal t2 = two->readIntReg(i);
71  if (t1 != t2)
72  panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
73  i, t1, t2);
74  }
75 
76  // Then loop through the floating point registers.
77  for (int i = 0; i < regClasses.at(FloatRegClass).numRegs(); ++i) {
78  RegVal t1 = one->readFloatReg(i);
79  RegVal t2 = two->readFloatReg(i);
80  if (t1 != t2)
81  panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
82  i, t1, t2);
83  }
84 
85  // Then loop through the vector registers.
86  const auto &vec_class = regClasses.at(VecRegClass);
87  std::vector<uint8_t> vec1(vec_class.regBytes());
88  std::vector<uint8_t> vec2(vec_class.regBytes());
89  for (int i = 0; i < vec_class.numRegs(); ++i) {
90  RegId rid(VecRegClass, i);
91 
92  one->getReg(rid, vec1.data());
93  two->getReg(rid, vec2.data());
94  if (vec1 != vec2) {
95  panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
96  i, vec_class.valString(vec1.data()),
97  vec_class.valString(vec2.data()));
98  }
99  }
100 
101  // Then loop through the predicate registers.
102  const auto &vec_pred_class = regClasses.at(VecPredRegClass);
103  std::vector<uint8_t> pred1(vec_pred_class.regBytes());
104  std::vector<uint8_t> pred2(vec_pred_class.regBytes());
105  for (int i = 0; i < vec_pred_class.numRegs(); ++i) {
106  RegId rid(VecPredRegClass, i);
107 
108  one->getReg(rid, pred1.data());
109  two->getReg(rid, pred2.data());
110  if (pred1 != pred2) {
111  panic("Pred reg idx %d doesn't match, one: %s, two: %s",
112  i, vec_pred_class.valString(pred1.data()),
113  vec_pred_class.valString(pred2.data()));
114  }
115  }
116 
117  for (int i = 0; i < regClasses.at(MiscRegClass).numRegs(); ++i) {
118  RegVal t1 = one->readMiscRegNoEffect(i);
119  RegVal t2 = two->readMiscRegNoEffect(i);
120  if (t1 != t2)
121  panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
122  i, t1, t2);
123  }
124 
125  // loop through the Condition Code registers.
126  for (int i = 0; i < regClasses.at(CCRegClass).numRegs(); ++i) {
127  RegVal t1 = one->readCCReg(i);
128  RegVal t2 = two->readCCReg(i);
129  if (t1 != t2)
130  panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
131  i, t1, t2);
132  }
133  if (one->pcState() != two->pcState())
134  panic("PC state doesn't match.");
135  int id1 = one->cpuId();
136  int id2 = two->cpuId();
137  if (id1 != id2)
138  panic("CPU ids don't match, one: %d, two: %d", id1, id2);
139 
140  const ContextID cid1 = one->contextId();
141  const ContextID cid2 = two->contextId();
142  if (cid1 != cid2)
143  panic("Context ids don't match, one: %d, two: %d", id1, id2);
144 
145 
146 }
147 
148 void
150 {
151  const auto *port =
152  dynamic_cast<const RequestPort *>(&getCpuPtr()->getDataPort());
153  assert(port);
154  port->sendFunctional(pkt);
155 }
156 
157 void
159 {
161 }
162 
163 
164 void
166 {
168 }
169 
170 RegVal
172 {
173  return getRegFlat(flattenRegId(reg));
174 }
175 
176 void *
178 {
180 }
181 
182 void
184 {
186 }
187 
188 void
189 ThreadContext::getReg(const RegId &reg, void *val) const
190 {
192 }
193 
194 void
195 ThreadContext::setReg(const RegId &reg, const void *val)
196 {
198 }
199 
200 RegVal
202 {
203  RegVal val;
204  getRegFlat(reg, &val);
205  return val;
206 }
207 
208 void
210 {
211  setRegFlat(reg, &val);
212 }
213 
214 void
216 {
217  // Cast away the const so we can get the non-const ISA ptr, which we then
218  // use to get the const register classes.
219  auto &nc_tc = const_cast<ThreadContext &>(tc);
220  const auto &regClasses = nc_tc.getIsaPtr()->regClasses();
221 
222  const size_t numFloats = regClasses.at(FloatRegClass).numRegs();
223  RegVal floatRegs[numFloats];
224  for (int i = 0; i < numFloats; ++i)
225  floatRegs[i] = tc.readFloatRegFlat(i);
226  // This is a bit ugly, but needed to maintain backwards
227  // compatibility.
228  arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats);
229 
230  const size_t numVecs = regClasses.at(VecRegClass).numRegs();
231  std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
232  for (int i = 0; i < numVecs; ++i) {
233  vecRegs[i] = tc.readVecRegFlat(i);
234  }
235  SERIALIZE_CONTAINER(vecRegs);
236 
237  const size_t numPreds = regClasses.at(VecPredRegClass).numRegs();
238  std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
239  for (int i = 0; i < numPreds; ++i) {
240  tc.getRegFlat(RegId(VecPredRegClass, i), &vecPredRegs[i]);
241  }
242  SERIALIZE_CONTAINER(vecPredRegs);
243 
244  const size_t numInts = regClasses.at(IntRegClass).numRegs();
245  RegVal intRegs[numInts];
246  for (int i = 0; i < numInts; ++i)
247  intRegs[i] = tc.readIntRegFlat(i);
248  SERIALIZE_ARRAY(intRegs, numInts);
249 
250  const size_t numCcs = regClasses.at(CCRegClass).numRegs();
251  if (numCcs) {
252  RegVal ccRegs[numCcs];
253  for (int i = 0; i < numCcs; ++i)
254  ccRegs[i] = tc.readCCRegFlat(i);
255  SERIALIZE_ARRAY(ccRegs, numCcs);
256  }
257 
258  tc.pcState().serialize(cp);
259 
260  // thread_num and cpu_id are deterministic from the config
261 }
262 
263 void
265 {
266  const auto &regClasses = tc.getIsaPtr()->regClasses();
267 
268  const size_t numFloats = regClasses.at(FloatRegClass).numRegs();
269  RegVal floatRegs[numFloats];
270  // This is a bit ugly, but needed to maintain backwards
271  // compatibility.
272  arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats);
273  for (int i = 0; i < numFloats; ++i)
274  tc.setFloatRegFlat(i, floatRegs[i]);
275 
276  const size_t numVecs = regClasses.at(VecRegClass).numRegs();
277  std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
278  UNSERIALIZE_CONTAINER(vecRegs);
279  for (int i = 0; i < numVecs; ++i) {
280  tc.setVecRegFlat(i, vecRegs[i]);
281  }
282 
283  const size_t numPreds = regClasses.at(VecPredRegClass).numRegs();
284  std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
285  UNSERIALIZE_CONTAINER(vecPredRegs);
286  for (int i = 0; i < numPreds; ++i) {
287  tc.setRegFlat(RegId(VecPredRegClass, i), &vecPredRegs[i]);
288  }
289 
290  const size_t numInts = regClasses.at(IntRegClass).numRegs();
291  RegVal intRegs[numInts];
292  UNSERIALIZE_ARRAY(intRegs, numInts);
293  for (int i = 0; i < numInts; ++i)
294  tc.setIntRegFlat(i, intRegs[i]);
295 
296  const size_t numCcs = regClasses.at(CCRegClass).numRegs();
297  if (numCcs) {
298  RegVal ccRegs[numCcs];
299  UNSERIALIZE_ARRAY(ccRegs, numCcs);
300  for (int i = 0; i < numCcs; ++i)
301  tc.setCCRegFlat(i, ccRegs[i]);
302  }
303 
304  std::unique_ptr<PCStateBase> pc_state(tc.pcState().clone());
305  pc_state->unserialize(cp);
306  tc.pcState(*pc_state);
307 
308  // thread_num and cpu_id are deterministic from the config
309 }
310 
311 void
313 {
314  assert(ntc.getProcessPtr() == otc.getProcessPtr());
315 
316  ntc.setStatus(otc.status());
317  ntc.copyArchRegs(&otc);
318  ntc.setContextId(otc.contextId());
319  ntc.setThreadId(otc.threadId());
320 
321  if (FullSystem)
322  assert(ntc.getSystemPtr() == otc.getSystemPtr());
323 
325 }
326 
327 } // namespace gem5
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:264
gem5::ThreadContext::setIntRegFlat
void setIntRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:331
gem5::ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:61
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::ThreadContext::readFloatReg
RegVal readFloatReg(RegIndex reg_idx) const
Definition: thread_context.hh:210
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ThreadContext::readVecRegFlat
TheISA::VecRegContainer readVecRegFlat(RegIndex idx) const
Definition: thread_context.hh:348
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:122
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:171
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::ThreadContext::readIntRegFlat
RegVal readIntRegFlat(RegIndex idx) const
Definition: thread_context.hh:326
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:65
gem5::System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:152
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
std::vector< uint8_t >
gem5::ThreadContext::getRegFlat
virtual RegVal getRegFlat(const RegId &reg) const
Flat register interfaces.
Definition: thread_context.cc:201
gem5::ThreadContext::getWritableReg
virtual void * getWritableReg(const RegId &reg)
Definition: thread_context.cc:177
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
gem5::ThreadContext::getWritableRegFlat
virtual void * getWritableRegFlat(const RegId &reg)=0
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:64
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:312
gem5::ThreadContext::status
virtual Status status() const =0
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::ArmISA::t1
Bitfield< 1 > t1
Definition: misc_types.hh:233
gem5::System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:163
gem5::ThreadContext::setThreadId
virtual void setThreadId(int id)=0
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
gem5::ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:165
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:158
gem5::ThreadContext::flattenRegId
virtual RegId flattenRegId(const RegId &reg_id) const =0
gem5::ThreadContext::readIntReg
RegVal readIntReg(RegIndex reg_idx) const
Definition: thread_context.hh:204
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ps2::one
Bitfield< 3 > one
Definition: types.hh:123
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ThreadContext::readCCRegFlat
RegVal readCCRegFlat(RegIndex idx) const
Definition: thread_context.hh:378
gem5::ThreadContext::setCCRegFlat
void setCCRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:383
port.hh
gem5::BaseISA::regClasses
const RegClasses & regClasses() const
Definition: isa.hh:78
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:215
gem5::ThreadContext::sendFunctional
virtual void sendFunctional(PacketPtr pkt)
Definition: thread_context.cc:149
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ThreadContext::setRegFlat
virtual void setRegFlat(const RegId &reg, RegVal val)
Definition: thread_context.cc:209
vec_pred_reg.hh
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
gem5::ThreadContext::readFloatRegFlat
RegVal readFloatRegFlat(RegIndex idx) const
Definition: thread_context.hh:337
gem5::ArmISA::t2
Bitfield< 2 > t2
Definition: misc_types.hh:232
gem5::arrayParamOut
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T &param)
Definition: serialize.hh:409
full_system.hh
gem5::PCStateBase::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pcstate.hh:133
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
base.hh
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:66
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::System::threads
Threads threads
Definition: system.hh:314
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
logging.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ThreadContext::threadId
virtual int threadId() const =0
trace.hh
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:61
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr() const =0
gem5::arrayParamIn
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:257
gem5::ThreadContext::readCCReg
RegVal readCCReg(RegIndex reg_idx) const
Definition: thread_context.hh:235
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ThreadContext::setVecRegFlat
void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)
Definition: thread_context.hh:361
thread_context.hh
gem5::PCStateBase::clone
virtual PCStateBase * clone() const =0
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:183
gem5::ThreadContext::setFloatRegFlat
void setFloatRegFlat(RegIndex idx, RegVal val)
Definition: thread_context.hh:342

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