gem5  v22.1.0.0
thread_context.cc
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41 
42 #include "cpu/thread_context.hh"
43 
44 #include <vector>
45 
47 #include "base/logging.hh"
48 #include "base/trace.hh"
49 #include "cpu/base.hh"
50 #include "debug/Context.hh"
51 #include "debug/Quiesce.hh"
52 #include "mem/port.hh"
53 #include "params/BaseCPU.hh"
54 #include "sim/full_system.hh"
55 
56 namespace gem5
57 {
58 
59 void
61 {
62  const auto &regClasses = one->getIsaPtr()->regClasses();
63 
64  DPRINTF(Context, "Comparing thread contexts\n");
65 
66  // First loop through the integer registers.
67  for (auto &id: *regClasses.at(IntRegClass)) {
68  RegVal t1 = one->getReg(id);
69  RegVal t2 = two->getReg(id);
70  if (t1 != t2)
71  panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
72  id.index(), t1, t2);
73  }
74 
75  // Then loop through the floating point registers.
76  for (auto &id: *regClasses.at(FloatRegClass)) {
77  RegVal t1 = one->getReg(id);
78  RegVal t2 = two->getReg(id);
79  if (t1 != t2)
80  panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
81  id.index(), t1, t2);
82  }
83 
84  // Then loop through the vector registers.
85  const auto *vec_class = regClasses.at(VecRegClass);
86  std::vector<uint8_t> vec1(vec_class->regBytes());
87  std::vector<uint8_t> vec2(vec_class->regBytes());
88  for (auto &id: *regClasses.at(VecRegClass)) {
89  one->getReg(id, vec1.data());
90  two->getReg(id, vec2.data());
91  if (vec1 != vec2) {
92  panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
93  id.index(), vec_class->valString(vec1.data()),
94  vec_class->valString(vec2.data()));
95  }
96  }
97 
98  // Then loop through the predicate registers.
99  const auto *vec_pred_class = regClasses.at(VecPredRegClass);
100  std::vector<uint8_t> pred1(vec_pred_class->regBytes());
101  std::vector<uint8_t> pred2(vec_pred_class->regBytes());
102  for (auto &id: *regClasses.at(VecPredRegClass)) {
103  one->getReg(id, pred1.data());
104  two->getReg(id, pred2.data());
105  if (pred1 != pred2) {
106  panic("Pred reg idx %d doesn't match, one: %s, two: %s",
107  id.index(), vec_pred_class->valString(pred1.data()),
108  vec_pred_class->valString(pred2.data()));
109  }
110  }
111 
112  for (int i = 0; i < regClasses.at(MiscRegClass)->numRegs(); ++i) {
113  RegVal t1 = one->readMiscRegNoEffect(i);
114  RegVal t2 = two->readMiscRegNoEffect(i);
115  if (t1 != t2)
116  panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
117  i, t1, t2);
118  }
119 
120  // loop through the Condition Code registers.
121  for (auto &id: *regClasses.at(CCRegClass)) {
122  RegVal t1 = one->getReg(id);
123  RegVal t2 = two->getReg(id);
124  if (t1 != t2)
125  panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
126  id.index(), t1, t2);
127  }
128  if (one->pcState() != two->pcState())
129  panic("PC state doesn't match.");
130  int id1 = one->cpuId();
131  int id2 = two->cpuId();
132  if (id1 != id2)
133  panic("CPU ids don't match, one: %d, two: %d", id1, id2);
134 
135  const ContextID cid1 = one->contextId();
136  const ContextID cid2 = two->contextId();
137  if (cid1 != cid2)
138  panic("Context ids don't match, one: %d, two: %d", id1, id2);
139 
140 
141 }
142 
143 void
145 {
146  const auto *port =
147  dynamic_cast<const RequestPort *>(&getCpuPtr()->getDataPort());
148  assert(port);
149  port->sendFunctional(pkt);
150 }
151 
152 void
154 {
156 }
157 
158 
159 void
161 {
163 }
164 
165 RegVal
167 {
168  RegVal val;
169  getReg(reg, &val);
170  return val;
171 }
172 
173 void
175 {
176  setReg(reg, &val);
177 }
178 
179 void
181 {
182  for (const auto *reg_class: tc.getIsaPtr()->regClasses()) {
183  // MiscRegs are serialized elsewhere.
184  if (reg_class->type() == MiscRegClass)
185  continue;
186 
187  const size_t reg_bytes = reg_class->regBytes();
188  const size_t reg_count = reg_class->numRegs();
189  const size_t array_bytes = reg_bytes * reg_count;
190 
191  uint8_t regs[array_bytes];
192  auto *reg_ptr = regs;
193  for (const auto &id: *reg_class) {
194  tc.getReg(id, reg_ptr);
195  reg_ptr += reg_bytes;
196  }
197 
198  arrayParamOut(cp, std::string("regs.") + reg_class->name(), regs,
199  array_bytes);
200  }
201 
202  tc.pcState().serialize(cp);
203 
204  // thread_num and cpu_id are deterministic from the config
205 }
206 
207 void
209 {
210  for (const auto *reg_class: tc.getIsaPtr()->regClasses()) {
211  // MiscRegs are serialized elsewhere.
212  if (reg_class->type() == MiscRegClass)
213  continue;
214 
215  const size_t reg_bytes = reg_class->regBytes();
216  const size_t reg_count = reg_class->numRegs();
217  const size_t array_bytes = reg_bytes * reg_count;
218 
219  uint8_t regs[array_bytes];
220  arrayParamIn(cp, std::string("regs.") + reg_class->name(), regs,
221  array_bytes);
222 
223  auto *reg_ptr = regs;
224  for (const auto &id: *reg_class) {
225  tc.setReg(id, reg_ptr);
226  reg_ptr += reg_bytes;
227  }
228  }
229 
230  std::unique_ptr<PCStateBase> pc_state(tc.pcState().clone());
231  pc_state->unserialize(cp);
232  tc.pcState(*pc_state);
233 
234  // thread_num and cpu_id are deterministic from the config
235 }
236 
237 void
239 {
240  assert(ntc.getProcessPtr() == otc.getProcessPtr());
241 
242  ntc.setStatus(otc.status());
243  ntc.copyArchRegs(&otc);
244  ntc.setContextId(otc.contextId());
245  ntc.setThreadId(otc.threadId());
246 
247  if (FullSystem)
248  assert(ntc.getSystemPtr() == otc.getSystemPtr());
249 
251 }
252 
253 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
const RegClasses & regClasses() const
Definition: isa.hh:86
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pcstate.hh:133
virtual PCStateBase * clone() const =0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:91
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:79
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:154
void quiesce(ContextID id)
Definition: system.cc:145
Threads threads
Definition: system.hh:313
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void setStatus(Status new_status)=0
virtual RegVal getReg(const RegId &reg) const
virtual const PCStateBase & pcState() const =0
virtual System * getSystemPtr()=0
virtual void copyArchRegs(ThreadContext *tc)=0
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
virtual BaseISA * getIsaPtr() const =0
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
virtual void setReg(const RegId &reg, RegVal val)
void quiesce()
Quiesce thread context.
@ Halted
Permanently shut down.
virtual BaseCPU * getCpuPtr()=0
virtual int threadId() const =0
virtual Status status() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual ContextID contextId() const =0
virtual void sendFunctional(PacketPtr pkt)
virtual void setThreadId(int id)=0
virtual Process * getProcessPtr()=0
virtual void setContextId(ContextID id)=0
virtual int cpuId() const =0
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T &param)
Definition: serialize.hh:409
Port Object Declaration.
Bitfield< 2 > t2
Definition: misc_types.hh:233
Bitfield< 7 > i
Definition: misc_types.hh:67
Bitfield< 1 > t1
Definition: misc_types.hh:234
Bitfield< 30, 0 > index
Bitfield< 5, 3 > reg
Definition: types.hh:92
Bitfield< 63 > val
Definition: misc.hh:776
Bitfield< 3 > one
Definition: types.hh:123
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::ostream CheckpointOut
Definition: serialize.hh:66
void unserialize(ThreadContext &tc, CheckpointIn &cp)
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:220
uint64_t Tick
Tick count type.
Definition: types.hh:58
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
uint64_t RegVal
Definition: types.hh:173
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:257
@ VecPredRegClass
Definition: reg_class.hh:66
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:61
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:67
@ VecRegClass
Vector Register.
Definition: reg_class.hh:63
@ IntRegClass
Integer register.
Definition: reg_class.hh:60
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:68

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