gem5  v21.1.0.2
thread_context.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012, 2016-2017 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #include "cpu/thread_context.hh"
43 
45 #include "base/logging.hh"
46 #include "base/trace.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "debug/Context.hh"
50 #include "debug/Quiesce.hh"
51 #include "mem/port.hh"
52 #include "params/BaseCPU.hh"
53 #include "sim/full_system.hh"
54 
55 namespace gem5
56 {
57 
58 void
60 {
61  const auto &regClasses = one->getIsaPtr()->regClasses();
62 
63  DPRINTF(Context, "Comparing thread contexts\n");
64 
65  // First loop through the integer registers.
66  for (int i = 0; i < regClasses.at(IntRegClass).size(); ++i) {
67  RegVal t1 = one->readIntReg(i);
68  RegVal t2 = two->readIntReg(i);
69  if (t1 != t2)
70  panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
71  i, t1, t2);
72  }
73 
74  // Then loop through the floating point registers.
75  for (int i = 0; i < regClasses.at(FloatRegClass).size(); ++i) {
76  RegVal t1 = one->readFloatReg(i);
77  RegVal t2 = two->readFloatReg(i);
78  if (t1 != t2)
79  panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
80  i, t1, t2);
81  }
82 
83  // Then loop through the vector registers.
84  for (int i = 0; i < regClasses.at(VecRegClass).size(); ++i) {
85  RegId rid(VecRegClass, i);
86  const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
87  const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
88  if (t1 != t2)
89  panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
90  i, t1, t2);
91  }
92 
93  // Then loop through the predicate registers.
94  for (int i = 0; i < regClasses.at(VecPredRegClass).size(); ++i) {
95  RegId rid(VecPredRegClass, i);
96  const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
98  if (t1 != t2)
99  panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
100  i, t1, t2);
101  }
102 
103  for (int i = 0; i < regClasses.at(MiscRegClass).size(); ++i) {
104  RegVal t1 = one->readMiscRegNoEffect(i);
105  RegVal t2 = two->readMiscRegNoEffect(i);
106  if (t1 != t2)
107  panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
108  i, t1, t2);
109  }
110 
111  // loop through the Condition Code registers.
112  for (int i = 0; i < regClasses.at(CCRegClass).size(); ++i) {
113  RegVal t1 = one->readCCReg(i);
114  RegVal t2 = two->readCCReg(i);
115  if (t1 != t2)
116  panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
117  i, t1, t2);
118  }
119  if (!(one->pcState() == two->pcState()))
120  panic("PC state doesn't match.");
121  int id1 = one->cpuId();
122  int id2 = two->cpuId();
123  if (id1 != id2)
124  panic("CPU ids don't match, one: %d, two: %d", id1, id2);
125 
126  const ContextID cid1 = one->contextId();
127  const ContextID cid2 = two->contextId();
128  if (cid1 != cid2)
129  panic("Context ids don't match, one: %d, two: %d", id1, id2);
130 
131 
132 }
133 
134 void
136 {
137  const auto *port =
138  dynamic_cast<const RequestPort *>(&getCpuPtr()->getDataPort());
139  assert(port);
140  port->sendFunctional(pkt);
141 }
142 
143 void
145 {
147 }
148 
149 
150 void
152 {
154 }
155 
156 void
158 {
159  // Cast away the const so we can get the non-const ISA ptr, which we then
160  // use to get the const register classes.
161  auto &nc_tc = const_cast<ThreadContext &>(tc);
162  const auto &regClasses = nc_tc.getIsaPtr()->regClasses();
163 
164  const size_t numFloats = regClasses.at(FloatRegClass).size();
165  RegVal floatRegs[numFloats];
166  for (int i = 0; i < numFloats; ++i)
167  floatRegs[i] = tc.readFloatRegFlat(i);
168  // This is a bit ugly, but needed to maintain backwards
169  // compatibility.
170  arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats);
171 
172  const size_t numVecs = regClasses.at(VecRegClass).size();
173  std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
174  for (int i = 0; i < numVecs; ++i) {
175  vecRegs[i] = tc.readVecRegFlat(i);
176  }
177  SERIALIZE_CONTAINER(vecRegs);
178 
179  const size_t numPreds = regClasses.at(VecPredRegClass).size();
180  std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
181  for (int i = 0; i < numPreds; ++i) {
182  vecPredRegs[i] = tc.readVecPredRegFlat(i);
183  }
184  SERIALIZE_CONTAINER(vecPredRegs);
185 
186  const size_t numInts = regClasses.at(IntRegClass).size();
187  RegVal intRegs[numInts];
188  for (int i = 0; i < numInts; ++i)
189  intRegs[i] = tc.readIntRegFlat(i);
190  SERIALIZE_ARRAY(intRegs, numInts);
191 
192  const size_t numCcs = regClasses.at(CCRegClass).size();
193  if (numCcs) {
194  RegVal ccRegs[numCcs];
195  for (int i = 0; i < numCcs; ++i)
196  ccRegs[i] = tc.readCCRegFlat(i);
197  SERIALIZE_ARRAY(ccRegs, numCcs);
198  }
199 
200  tc.pcState().serialize(cp);
201 
202  // thread_num and cpu_id are deterministic from the config
203 }
204 
205 void
207 {
208  const auto &regClasses = tc.getIsaPtr()->regClasses();
209 
210  const size_t numFloats = regClasses.at(FloatRegClass).size();
211  RegVal floatRegs[numFloats];
212  // This is a bit ugly, but needed to maintain backwards
213  // compatibility.
214  arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats);
215  for (int i = 0; i < numFloats; ++i)
216  tc.setFloatRegFlat(i, floatRegs[i]);
217 
218  const size_t numVecs = regClasses.at(VecRegClass).size();
219  std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
220  UNSERIALIZE_CONTAINER(vecRegs);
221  for (int i = 0; i < numVecs; ++i) {
222  tc.setVecRegFlat(i, vecRegs[i]);
223  }
224 
225  const size_t numPreds = regClasses.at(VecPredRegClass).size();
226  std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
227  UNSERIALIZE_CONTAINER(vecPredRegs);
228  for (int i = 0; i < numPreds; ++i) {
229  tc.setVecPredRegFlat(i, vecPredRegs[i]);
230  }
231 
232  const size_t numInts = regClasses.at(IntRegClass).size();
233  RegVal intRegs[numInts];
234  UNSERIALIZE_ARRAY(intRegs, numInts);
235  for (int i = 0; i < numInts; ++i)
236  tc.setIntRegFlat(i, intRegs[i]);
237 
238  const size_t numCcs = regClasses.at(CCRegClass).size();
239  if (numCcs) {
240  RegVal ccRegs[numCcs];
241  UNSERIALIZE_ARRAY(ccRegs, numCcs);
242  for (int i = 0; i < numCcs; ++i)
243  tc.setCCRegFlat(i, ccRegs[i]);
244  }
245 
246  TheISA::PCState pcState;
247  pcState.unserialize(cp);
248  tc.pcState(pcState);
249 
250  // thread_num and cpu_id are deterministic from the config
251 }
252 
253 void
255 {
256  assert(ntc.getProcessPtr() == otc.getProcessPtr());
257 
258  ntc.setStatus(otc.status());
259  ntc.copyArchRegs(&otc);
260  ntc.setContextId(otc.contextId());
261  ntc.setThreadId(otc.threadId());
262 
263  if (FullSystem)
264  assert(ntc.getSystemPtr() == otc.getSystemPtr());
265 
267 }
268 
269 } // namespace gem5
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:64
gem5::ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:59
gem5::ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:121
gem5::ThreadContext::readVecPredReg
virtual const TheISA::VecPredRegContainer & readVecPredReg(const RegId &reg) const =0
gem5::ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:171
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const =0
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:63
gem5::ThreadContext::contextId
virtual ContextID contextId() const =0
std::vector< TheISA::VecRegContainer >
gem5::ThreadContext::readVecPredRegFlat
virtual const TheISA::VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const =0
gem5::ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::ThreadContext::cpuId
virtual int cpuId() const =0
gem5::ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:254
gem5::ThreadContext::status
virtual Status status() const =0
gem5::GenericISA::DelaySlotPCState::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: types.hh:366
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::ArmISA::t1
Bitfield< 1 > t1
Definition: misc_types.hh:232
gem5::System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:182
gem5::ThreadContext::setThreadId
virtual void setThreadId(int id)=0
gem5::BaseCPU::getDataPort
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
gem5::ThreadContext::readVecReg
virtual const TheISA::VecRegContainer & readVecReg(const RegId &reg) const =0
gem5::ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
gem5::ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:151
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:144
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ps2::one
Bitfield< 3 > one
Definition: types.hh:123
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)=0
gem5::ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
port.hh
gem5::BaseISA::regClasses
const RegClasses & regClasses() const
Definition: isa.hh:86
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
gem5::ThreadContext::sendFunctional
virtual void sendFunctional(PacketPtr pkt)
Definition: thread_context.cc:135
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
vec_pred_reg.hh
gem5::ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
gem5::ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
gem5::ArmISA::t2
Bitfield< 2 > t2
Definition: misc_types.hh:231
gem5::arrayParamOut
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T &param)
Definition: serialize.hh:409
full_system.hh
gem5::ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
gem5::FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:223
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:60
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::System::threads
Threads threads
Definition: system.hh:316
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
logging.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ThreadContext::getCpuPtr
virtual BaseCPU * getCpuPtr()=0
gem5::ThreadContext::threadId
virtual int threadId() const =0
trace.hh
gem5::ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer &val)=0
gem5::arrayParamIn
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:257
gem5::ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const TheISA::VecPredRegContainer &val)=0
gem5::ThreadContext::readVecRegFlat
virtual const TheISA::VecRegContainer & readVecRegFlat(RegIndex idx) const =0
thread_context.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

Generated on Tue Sep 21 2021 12:24:24 for gem5 by doxygen 1.8.17