50 #include "debug/Context.hh"
51 #include "debug/Quiesce.hh"
53 #include "params/BaseCPU.hh"
62 const auto ®Classes =
one->getIsaPtr()->regClasses();
71 panic(
"Int reg idx %d doesn't match, one: %#x, two: %#x",
80 panic(
"Float reg idx %d doesn't match, one: %#x, two: %#x",
89 one->getReg(
id, vec1.data());
90 two->
getReg(
id, vec2.data());
92 panic(
"Vec reg idx %d doesn't match, one: %#x, two: %#x",
93 id.
index(), vec_class->valString(vec1.data()),
94 vec_class->valString(vec2.data()));
103 one->getReg(
id, pred1.data());
104 two->
getReg(
id, pred2.data());
105 if (pred1 != pred2) {
106 panic(
"Pred reg idx %d doesn't match, one: %s, two: %s",
107 id.
index(), vec_pred_class->valString(pred1.data()),
108 vec_pred_class->valString(pred2.data()));
116 panic(
"Misc reg idx %d doesn't match, one: %#x, two: %#x",
125 panic(
"CC reg idx %d doesn't match, one: %#x, two: %#x",
129 panic(
"PC state doesn't match.");
130 int id1 =
one->cpuId();
131 int id2 = two->
cpuId();
133 panic(
"CPU ids don't match, one: %d, two: %d", id1, id2);
138 panic(
"Context ids don't match, one: %d, two: %d", id1, id2);
149 port->sendFunctional(pkt);
187 const size_t reg_bytes = reg_class->regBytes();
188 const size_t reg_count = reg_class->numRegs();
189 const size_t array_bytes = reg_bytes * reg_count;
191 uint8_t regs[array_bytes];
192 auto *reg_ptr = regs;
193 for (
const auto &
id: *reg_class) {
195 reg_ptr += reg_bytes;
198 arrayParamOut(cp, std::string(
"regs.") + reg_class->name(), regs,
215 const size_t reg_bytes = reg_class->regBytes();
216 const size_t reg_count = reg_class->numRegs();
217 const size_t array_bytes = reg_bytes * reg_count;
219 uint8_t regs[array_bytes];
220 arrayParamIn(cp, std::string(
"regs.") + reg_class->name(), regs,
223 auto *reg_ptr = regs;
224 for (
const auto &
id: *reg_class) {
226 reg_ptr += reg_bytes;
230 std::unique_ptr<PCStateBase> pc_state(tc.
pcState().
clone());
231 pc_state->unserialize(cp);
virtual Port & getDataPort()=0
Purely virtual method that returns a reference to the data port.
const RegClasses & regClasses() const
void serialize(CheckpointOut &cp) const override
Serialize an object.
virtual PCStateBase * clone() const =0
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Register ID: describe an architectural register with its class and index.
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
void quiesceTick(ContextID id, Tick when)
void quiesce(ContextID id)
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual void setStatus(Status new_status)=0
virtual RegVal getReg(const RegId ®) const
virtual const PCStateBase & pcState() const =0
virtual System * getSystemPtr()=0
virtual void copyArchRegs(ThreadContext *tc)=0
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
virtual BaseISA * getIsaPtr() const =0
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
virtual void setReg(const RegId ®, RegVal val)
void quiesce()
Quiesce thread context.
@ Halted
Permanently shut down.
virtual BaseCPU * getCpuPtr()=0
virtual int threadId() const =0
virtual Status status() const =0
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
virtual ContextID contextId() const =0
virtual void sendFunctional(PacketPtr pkt)
virtual void setThreadId(int id)=0
virtual Process * getProcessPtr()=0
virtual void setContextId(ContextID id)=0
virtual int cpuId() const =0
#define panic(...)
This implements a cprintf based panic() function.
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T ¶m)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::ostream CheckpointOut
void unserialize(ThreadContext &tc, CheckpointIn &cp)
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
uint64_t Tick
Tick count type.
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
int ContextID
Globally unique thread context ID.
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > ¶m)
@ FloatRegClass
Floating-point register.
@ CCRegClass
Condition-code register.
@ VecRegClass
Vector Register.
@ IntRegClass
Integer register.
@ MiscRegClass
Control (misc) register.