gem5 v24.0.0.0
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if_test.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 if_test.h --
23
24 Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38
39#include "common.h"
40
41SC_MODULE( if_test )
42{
43 SC_HAS_PROCESS( if_test );
44
45 sc_in_clk clk;
46
47 const sc_signal<bool>& reset ;
48 const sc_signal_bool_vector& in_value1;
49 const sc_signal_bool_vector& in_value2;
50 const sc_signal_bool_vector& in_value3;
51 const sc_signal_bool_vector& in_value4;
52 const sc_signal<int>& in_value5 ;
53 const sc_signal<bool>& in_valid;
54 sc_signal_bool_vector& out_value1;
55 sc_signal_bool_vector& out_value2;
56 sc_signal_bool_vector& out_value3;
57 sc_signal_bool_vector& out_value4;
58 sc_signal<int>& out_value5;
59 sc_signal<bool>& out_valid;
60
61 //
62 // Constructor
63 //
64
65 if_test(
66 sc_module_name NAME, // referense name
67 sc_clock& CLK, // clock
68 const sc_signal<bool>& RESET,
69 const sc_signal_bool_vector& IN_VALUE1,
70 const sc_signal_bool_vector& IN_VALUE2,
71 const sc_signal_bool_vector& IN_VALUE3,
72 const sc_signal_bool_vector& IN_VALUE4,
73 const sc_signal<int>& IN_VALUE5,
74 const sc_signal<bool>& IN_VALID, // Input port
75 sc_signal_bool_vector& OUT_VALUE1,
76 sc_signal_bool_vector& OUT_VALUE2,
77 sc_signal_bool_vector& OUT_VALUE3,
78 sc_signal_bool_vector& OUT_VALUE4,
79 sc_signal<int>& OUT_VALUE5,
80 sc_signal<bool>& OUT_VALID // Input port
81 )
82 :
83 reset (RESET),
84 in_value1 (IN_VALUE1),
85 in_value2 (IN_VALUE2),
86 in_value3 (IN_VALUE3),
87 in_value4 (IN_VALUE4),
88 in_value5 (IN_VALUE5),
89 in_valid (IN_VALID),
90 out_value1 (OUT_VALUE1),
91 out_value2 (OUT_VALUE2),
92 out_value3 (OUT_VALUE3),
93 out_value4 (OUT_VALUE4),
94 out_value5 (OUT_VALUE5),
95 out_valid (OUT_VALID)
96 {
97 clk (CLK);
98 SC_CTHREAD( entry, clk.pos() );
99 reset_signal_is(reset,true);
100 };
101
102 //
103
104 void entry ();
105
106};
107
108// EOF
sc_signal< sc_bv< 8 > > sc_signal_bool_vector
Definition common.h:43
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
#define SC_MODULE(name)
Definition sc_module.hh:295
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301

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