gem5 v24.0.0.0
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malta.cc
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1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
33#include "dev/mips/malta.hh"
34
35#include "debug/Malta.hh"
37#include "dev/mips/malta_io.hh"
38#include "params/Malta.hh"
39
40namespace gem5
41{
42
44 : Platform(p)
45{
46 for (int i = 0; i < Malta::Max_CPUs; i++)
47 intr_sum_type[i] = 0;
48}
49
50void
52{
53 //see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c
54 io->postIntr(0x10/*HW4*/);
55}
56
57void
59{
60 //FIXME: implement clearConsoleInt()
61 io->clearIntr(0x10/*HW4*/);
62}
63
64void
66{
67 panic("Malta::postPciInt() has not been implemented.");
68}
69
70void
72{
73 panic("Malta::clearPciInt() has not been implemented.");
74}
75
76void
81
82void
87
88} // namespace gem5
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
Definition malta_io.cc:96
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
Definition malta_io.cc:103
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition malta.cc:51
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition malta.cc:77
int intr_sum_type[Malta::Max_CPUs]
Definition malta.hh:69
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition malta.cc:71
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
Definition malta.hh:61
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition malta.cc:83
MaltaParams Params
Definition malta.hh:73
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition malta.cc:65
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition malta.hh:58
Malta(const Params &p)
Definition malta.cc:43
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
Definition malta.cc:58
#define panic(...)
This implements a cprintf based panic() function.
Definition logging.hh:188
#define UNSERIALIZE_ARRAY(member, size)
Definition serialize.hh:618
#define SERIALIZE_ARRAY(member, size)
Definition serialize.hh:610
Declaration of top level class for the Malta chipset.
Emulation of the Malta CChip CSRs.
Malta I/O Space mapping including RTC/timer interrupts.
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66

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