35#include "debug/Malta.hh"
38#include "params/Malta.hh"
67 panic(
"Malta::postPciInt() has not been implemented.");
73 panic(
"Malta::clearPciInt() has not been implemented.");
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
void serialize(CheckpointOut &cp) const override
Serialize an object.
int intr_sum_type[Malta::Max_CPUs]
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
static const int Max_CPUs
Max number of CPUs in a Malta.
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
#define panic(...)
This implements a cprintf based panic() function.
#define UNSERIALIZE_ARRAY(member, size)
#define SERIALIZE_ARRAY(member, size)
Declaration of top level class for the Malta chipset.
Emulation of the Malta CChip CSRs.
Malta I/O Space mapping including RTC/timer interrupts.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
std::ostream CheckpointOut