gem5  v21.1.0.2
malta.cc
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28 
33 #include "dev/mips/malta.hh"
34 
35 #include "debug/Malta.hh"
36 #include "dev/mips/malta_cchip.hh"
37 #include "dev/mips/malta_io.hh"
38 #include "params/Malta.hh"
39 
40 namespace gem5
41 {
42 
44  : Platform(p)
45 {
46  for (int i = 0; i < Malta::Max_CPUs; i++)
47  intr_sum_type[i] = 0;
48 }
49 
50 void
52 {
53  //see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c
54  io->postIntr(0x10/*HW4*/);
55 }
56 
57 void
59 {
60  //FIXME: implement clearConsoleInt()
61  io->clearIntr(0x10/*HW4*/);
62 }
63 
64 void
66 {
67  panic("Malta::postPciInt() has not been implemented.");
68 }
69 
70 void
72 {
73  panic("Malta::clearPciInt() has not been implemented.");
74 }
75 
76 void
78 {
80 }
81 
82 void
84 {
86 }
87 
88 } // namespace gem5
gem5::scmi::Platform
Definition: scmi_platform.hh:264
malta.hh
gem5::Malta::postConsoleInt
void postConsoleInt() override
Cause the cpu to post a serial interrupt to the CPU.
Definition: malta.cc:51
gem5::Malta::clearPciInt
void clearPciInt(int line) override
Clear a posted PCI->CPU interrupt.
Definition: malta.cc:71
malta_io.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MaltaIO::postIntr
void postIntr(uint8_t interrupt)
Post an Interrupt to the CPU.
Definition: malta_io.cc:96
gem5::Malta::postPciInt
void postPciInt(int line) override
Cause the chipset to post a cpi interrupt to the CPU.
Definition: malta.cc:65
gem5::Malta::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: malta.cc:83
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
malta_cchip.hh
gem5::MaltaIO::clearIntr
void clearIntr(uint8_t interrupt)
Clear an Interrupt to the CPU.
Definition: malta_io.cc:103
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Malta::io
MaltaIO * io
Pointer to the MaltaIO device which has the RTC.
Definition: malta.hh:61
gem5::Malta::Malta
Malta(const Params &p)
Definition: malta.cc:43
gem5::Malta::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: malta.cc:77
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::Malta::Max_CPUs
static const int Max_CPUs
Max number of CPUs in a Malta.
Definition: malta.hh:58
gem5::Malta::Params
MaltaParams Params
Definition: malta.hh:73
gem5::Malta::clearConsoleInt
void clearConsoleInt() override
Clear a posted CPU interrupt (id=55)
Definition: malta.cc:58
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:618
gem5::Malta::intr_sum_type
int intr_sum_type[Malta::Max_CPUs]
Definition: malta.hh:69
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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