gem5  v21.1.0.2
neon64_mem.hh
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37 
40 
41 #ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__
42 #define __ARCH_ARM_INSTS_NEON64_MEM_HH__
43 
44 #include <cassert>
45 #include <cstdint>
46 
47 namespace gem5
48 {
49 
50 namespace ArmISA
51 {
52 
53 typedef uint64_t XReg;
54 
56 struct VReg
57 {
60 };
61 
63 inline void
64 writeVecElem(VReg *dest, XReg src, int index, int eSize)
65 {
66  // eSize must be less than 4:
67  // 0 -> 8-bit elems,
68  // 1 -> 16-bit elems,
69  // 2 -> 32-bit elems,
70  // 3 -> 64-bit elems
71  assert(eSize <= 3);
72 
73  int eBits = 8 << eSize;
74  int lsbPos = index * eBits;
75  assert(lsbPos < 128);
76  int shiftAmt = lsbPos % 64;
77 
78  XReg maskBits = -1;
79  if (eBits == 64) {
80  maskBits = 0;
81  } else {
82  maskBits = maskBits << eBits;
83  }
84  maskBits = ~maskBits;
85 
86  XReg sMask = maskBits;
87  maskBits = sMask << shiftAmt;
88 
89  if (lsbPos < 64) {
90  dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt);
91  } else {
92  dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt);
93  }
94 }
95 
97 inline XReg
98 readVecElem(VReg src, int index, int eSize)
99 {
100  // eSize must be less than 4:
101  // 0 -> 8-bit elems,
102  // 1 -> 16-bit elems,
103  // 2 -> 32-bit elems,
104  // 3 -> 64-bit elems
105  assert(eSize <= 3);
106 
107  XReg data;
108 
109  int eBits = 8 << eSize;
110  int lsbPos = index * eBits;
111  assert(lsbPos < 128);
112  int shiftAmt = lsbPos % 64;
113 
114  XReg maskBits = -1;
115  if (eBits == 64) {
116  maskBits = 0;
117  } else {
118  maskBits = maskBits << eBits;
119  }
120  maskBits = ~maskBits;
121 
122  if (lsbPos < 64) {
123  data = (src.lo >> shiftAmt) & maskBits;
124  } else {
125  data = (src.hi >> shiftAmt) & maskBits;
126  }
127  return data;
128 }
129 
130 } // namespace ArmISA
131 } // namespace gem5
132 
133 #endif // __ARCH_ARM_INSTS_NEON64_MEM_HH__
gem5::ArmISA::VReg
128-bit NEON vector register.
Definition: neon64_mem.hh:56
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::ArmISA::readVecElem
XReg readVecElem(VReg src, int index, int eSize)
Read a single NEON vector element.
Definition: neon64_mem.hh:98
gem5::ArmISA::VReg::hi
XReg hi
Definition: neon64_mem.hh:58
gem5::ArmISA::XReg
uint64_t XReg
Definition: neon64_mem.hh:53
gem5::ArmISA::VReg::lo
XReg lo
Definition: neon64_mem.hh:59
gem5::ArmISA::writeVecElem
void writeVecElem(VReg *dest, XReg src, int index, int eSize)
Write a single NEON vector element leaving the others untouched.
Definition: neon64_mem.hh:64
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40

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