neon64_mem.hh

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/*
 * Copyright (c) 2012-2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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#ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__
#define __ARCH_ARM_INSTS_NEON64_MEM_HH__
 
#include <cassert>
#include <cstdint>
 
namespace gem5
{
 
namespace ArmISA
{
 
typedef uint64_t XReg;
 
struct VReg
{
    XReg hi;
    XReg lo;
};
 
inline void
writeVecElem(VReg *dest, XReg src, int index, int eSize)
{
    // eSize must be less than 4:
    // 0 -> 8-bit elems,
    // 1 -> 16-bit elems,
    // 2 -> 32-bit elems,
    // 3 -> 64-bit elems
    assert(eSize <= 3);
 
    int eBits = 8 << eSize;
    int lsbPos = index * eBits;
    assert(lsbPos < 128);
    int shiftAmt = lsbPos % 64;
 
    XReg maskBits = -1;
    if (eBits == 64) {
        maskBits = 0;
    } else {
        maskBits = maskBits << eBits;
    }
    maskBits = ~maskBits;
 
    XReg sMask = maskBits;
    maskBits = sMask << shiftAmt;
 
    if (lsbPos < 64) {
        dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt);
    } else {
        dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt);
    }
}
 
inline XReg
readVecElem(VReg src, int index, int eSize)
{
    // eSize must be less than 4:
    // 0 -> 8-bit elems,
    // 1 -> 16-bit elems,
    // 2 -> 32-bit elems,
    // 3 -> 64-bit elems
    assert(eSize <= 3);
 
    XReg data;
 
    int eBits = 8 << eSize;
    int lsbPos = index * eBits;
    assert(lsbPos < 128);
    int shiftAmt = lsbPos % 64;
 
    XReg maskBits = -1;
    if (eBits == 64) {
        maskBits = 0;
    } else {
        maskBits = maskBits << eBits;
    }
    maskBits = ~maskBits;
 
    if (lsbPos < 64) {
        data = (src.lo >> shiftAmt) & maskBits;
    } else {
        data = (src.hi >> shiftAmt) & maskBits;
    }
    return data;
}
 
} // namespace ArmISA
} // namespace gem5
 
#endif  // __ARCH_ARM_INSTS_NEON64_MEM_HH__