gem5 v24.0.0.0
Loading...
Searching...
No Matches
decode.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __CPU_O3_DECODE_HH__
42#define __CPU_O3_DECODE_HH__
43
44#include <queue>
45
46#include "base/statistics.hh"
47#include "cpu/o3/comm.hh"
49#include "cpu/o3/limits.hh"
50#include "cpu/timebuf.hh"
51
52namespace gem5
53{
54
55struct BaseO3CPUParams;
56
57namespace o3
58{
59
60class CPU;
61
69class Decode
70{
71 public:
80
91
92 private:
95
98
99 public:
101 Decode(CPU *_cpu, const BaseO3CPUParams &params);
102
103 void startupStage();
104
106 void clearStates(ThreadID tid);
107
108 void resetStage();
109
111 std::string name() const;
112
115
118
121
124
126 void drainSanityCheck() const;
127
129 bool isDrained() const;
130
133
137 void tick();
138
144 void decode(bool &status_change, ThreadID tid);
145
151 void decodeInsts(ThreadID tid);
152
153 private:
157 void skidInsert(ThreadID tid);
158
160 bool skidsEmpty();
161
163 void updateStatus();
164
168 void sortInsts();
169
171 void readStallSignals(ThreadID tid);
172
175
177 bool checkStall(ThreadID tid) const;
178
180 bool fetchInstsValid();
181
186 bool block(ThreadID tid);
187
192 bool unblock(ThreadID tid);
193
197 void squash(const DynInstPtr &inst, ThreadID tid);
198
199 public:
203 unsigned squash(ThreadID tid);
204
205 private:
206 // Interfaces to objects outside of decode.
209
212
215
218
221
223 // Might not be the best name as not only fetch will read it.
225
228
231
234
237
239 std::queue<DynInstPtr> insts[MaxThreads];
240
242 std::queue<DynInstPtr> skidBuffer[MaxThreads];
243
248
250 struct Stalls
251 {
252 bool rename;
253 };
254
257
260
263
266
269
271 unsigned decodeWidth;
272
275
278
281
284
287
290
296
324};
325
326} // namespace o3
327} // namespace gem5
328
329#endif // __CPU_O3_DECODE_HH__
Cycles is a wrapper class for representing cycle counts, i.e.
Definition types.hh:79
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition cpu.hh:94
Decode class handles both single threaded and SMT decode.
Definition decode.hh:70
DecodeStatus _status
Decode status.
Definition decode.hh:94
std::queue< DynInstPtr > skidBuffer[MaxThreads]
Skid buffer between fetch and decode.
Definition decode.hh:242
bool wroteToTimeBuffer
Variable that tracks if decode has written to the time buffer this cycle.
Definition decode.hh:247
bool unblock(ThreadID tid)
Switches decode to unblocking if the skid buffer is empty, and signals back that decode has unblocked...
Definition decode.cc:265
bool squashAfterDelaySlot[MaxThreads]
Tells when their is a pending delay slot inst.
Definition decode.hh:295
void readStallSignals(ThreadID tid)
Reads all stall signals from the backwards communication timebuffer.
Definition decode.cc:474
gem5::o3::Decode::DecodeStats stats
DynInstPtr squashInst[MaxThreads]
Instruction used for squashing branch (used for MIPS)
Definition decode.hh:289
CPU * cpu
CPU interface.
Definition decode.hh:208
Cycles iewToDecodeDelay
IEW to decode delay.
Definition decode.hh:262
void decodeInsts(ThreadID tid)
Processes instructions from fetch and passes them on to rename.
Definition decode.cc:622
Stalls stalls[MaxThreads]
Tracks which stages are telling decode to stall.
Definition decode.hh:256
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition decode.hh:224
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition decode.hh:283
Cycles commitToDecodeDelay
Commit to decode delay.
Definition decode.hh:265
void decode(bool &status_change, ThreadID tid)
Determines what to do based on decode's current status.
Definition decode.cc:578
bool fetchInstsValid()
Returns if there any instructions from fetch on this cycle.
Definition decode.cc:230
bool checkSignalsAndUpdate(ThreadID tid)
Checks all input signals and updates decode's status appropriately.
Definition decode.cc:487
void startupStage()
Definition decode.cc:91
TimeBuffer< DecodeStruct >::wire toRename
Wire used to write any information heading to rename.
Definition decode.hh:230
Cycles renameToDecodeDelay
Rename to decode delay.
Definition decode.hh:259
Cycles fetchToDecodeDelay
Fetch to decode delay.
Definition decode.hh:268
std::queue< DynInstPtr > insts[MaxThreads]
Queue of all instructions coming from fetch this cycle.
Definition decode.hh:239
void setFetchQueue(TimeBuffer< FetchStruct > *fq_ptr)
Sets pointer to time buffer coming from fetch.
Definition decode.cc:182
void takeOverFrom()
Takes over from another CPU's thread.
Definition decode.hh:132
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the main backwards communication time buffer pointer.
Definition decode.cc:159
ThreadStatus decodeStatus[MaxThreads]
Per-thread status.
Definition decode.hh:97
void sortInsts()
Separates instructions from fetch into individual lists of instructions sorted by thread.
Definition decode.cc:465
ThreadStatus
Individual thread status.
Definition decode.hh:83
unsigned toRenameIndex
Index of instructions being sent to rename.
Definition decode.hh:274
void setDecodeQueue(TimeBuffer< DecodeStruct > *dq_ptr)
Sets pointer to time buffer used to communicate to the next stage.
Definition decode.cc:173
TimeBuffer< DecodeStruct > * decodeQueue
Decode instruction queue.
Definition decode.hh:227
void squash(const DynInstPtr &inst, ThreadID tid)
Squashes if there is a PC-relative branch that was predicted incorrectly.
Definition decode.cc:283
void updateStatus()
Updates overall decode status based on all of the threads' statuses.
Definition decode.cc:427
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition decode.cc:412
unsigned decodeWidth
The width of decode, in instructions.
Definition decode.hh:271
bool isDrained() const
Has the stage drained?
Definition decode.cc:206
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's information from backwards time buffer.
Definition decode.hh:220
ThreadID numThreads
number of Active Threads
Definition decode.hh:277
TimeBuffer< TimeStruct > * timeBuffer
Time buffer interface.
Definition decode.hh:211
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition decode.cc:191
void resetStage()
Definition decode.cc:104
TimeBuffer< FetchStruct >::wire fromFetch
Wire to get fetch's output from fetch queue.
Definition decode.hh:236
TimeBuffer< TimeStruct >::wire fromRename
Wire to get rename's output from backwards time buffer.
Definition decode.hh:214
Addr bdelayDoneSeqNum[MaxThreads]
SeqNum of Squashing Branch Delay Instruction (used for MIPS)
Definition decode.hh:286
DecodeStatus
Overall decode stage status.
Definition decode.hh:76
TimeBuffer< TimeStruct >::wire fromIEW
Wire to get iew's information from backwards time buffer.
Definition decode.hh:217
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition decode.cc:97
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition decode.cc:197
std::list< ThreadID > * activeThreads
List of active thread ids.
Definition decode.hh:280
void tick()
Ticks decode, processing all input signals and decoding as many instructions as possible.
Definition decode.cc:543
Decode(CPU *_cpu, const BaseO3CPUParams &params)
Decode constructor.
Definition decode.cc:64
bool block(ThreadID tid)
Switches decode to blocking, and signals back that decode has become blocked.
Definition decode.cc:236
std::string name() const
Returns the name of decode.
Definition decode.cc:117
void skidInsert(ThreadID tid)
Inserts a thread's instructions into the skid buffer, to be decoded once decode unblocks.
Definition decode.cc:388
TimeBuffer< FetchStruct > * fetchQueue
Fetch instruction queue interface.
Definition decode.hh:233
bool checkStall(ThreadID tid) const
Checks all stall signals, and returns if any are true.
Definition decode.cc:217
Statistics container.
Definition group.hh:93
This is a simple scalar statistic, like a counter.
STL list class.
Definition stl.hh:51
static constexpr int MaxThreads
Definition limits.hh:38
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
Declaration of Statistics objects.
statistics::Scalar branchResolved
Stat for number of times a branch is resolved at decode.
Definition decode.hh:312
statistics::Scalar squashCycles
Stat for total number of squashing cycles.
Definition decode.hh:310
statistics::Scalar runCycles
Stat for total number of normal running cycles.
Definition decode.hh:306
statistics::Scalar squashedInsts
Stat for total number of squashed instructions.
Definition decode.hh:322
statistics::Scalar idleCycles
Stat for total number of idle cycles.
Definition decode.hh:302
statistics::Scalar branchMispred
Stat for number of times a branch mispredict is detected.
Definition decode.hh:314
statistics::Scalar decodedInsts
Stat for total number of decoded instructions.
Definition decode.hh:320
statistics::Scalar blockedCycles
Stat for total number of blocked cycles.
Definition decode.hh:304
statistics::Scalar controlMispred
Stat for number of times decode detected a non-control instruction incorrectly predicted as a branch.
Definition decode.hh:318
statistics::Scalar unblockCycles
Stat for total number of unblocking cycles.
Definition decode.hh:308
Source of possible stalls.
Definition decode.hh:251

Generated on Tue Jun 18 2024 16:24:01 for gem5 by doxygen 1.11.0