int.hh File Reference

#include "cpu/reg_class.hh"
#include "debug/IntRegs.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 Arm Limited All rights reserved.
namespace	gem5::PowerISA
namespace	gem5::PowerISA::int_reg

Enumerations
enum	: RegIndex {   gem5::PowerISA::int_reg::_R0Idx , gem5::PowerISA::int_reg::_R1Idx , gem5::PowerISA::int_reg::_R2Idx , gem5::PowerISA::int_reg::_R3Idx ,   gem5::PowerISA::int_reg::_R4Idx , gem5::PowerISA::int_reg::_R5Idx , gem5::PowerISA::int_reg::_R6Idx , gem5::PowerISA::int_reg::_R7Idx ,   gem5::PowerISA::int_reg::_R8Idx , gem5::PowerISA::int_reg::_R9Idx , gem5::PowerISA::int_reg::_R10Idx , gem5::PowerISA::int_reg::_R11Idx ,   gem5::PowerISA::int_reg::_R12Idx , gem5::PowerISA::int_reg::_R13Idx , gem5::PowerISA::int_reg::_R14Idx , gem5::PowerISA::int_reg::_R15Idx ,   gem5::PowerISA::int_reg::_R16Idx , gem5::PowerISA::int_reg::_R17Idx , gem5::PowerISA::int_reg::_R18Idx , gem5::PowerISA::int_reg::_R19Idx ,   gem5::PowerISA::int_reg::_R20Idx , gem5::PowerISA::int_reg::_R21Idx , gem5::PowerISA::int_reg::_R22Idx , gem5::PowerISA::int_reg::_R23Idx ,   gem5::PowerISA::int_reg::_R24Idx , gem5::PowerISA::int_reg::_R25Idx , gem5::PowerISA::int_reg::_R26Idx , gem5::PowerISA::int_reg::_R27Idx ,   gem5::PowerISA::int_reg::_R28Idx , gem5::PowerISA::int_reg::_R29Idx , gem5::PowerISA::int_reg::_R30Idx , gem5::PowerISA::int_reg::_R31Idx ,   gem5::PowerISA::int_reg::NumArchRegs , gem5::PowerISA::int_reg::_CrIdx = NumArchRegs , gem5::PowerISA::int_reg::_XerIdx , gem5::PowerISA::int_reg::_LrIdx ,   gem5::PowerISA::int_reg::_CtrIdx , gem5::PowerISA::int_reg::_TarIdx , gem5::PowerISA::int_reg::_FpscrIdx , gem5::PowerISA::int_reg::_MsrIdx ,   gem5::PowerISA::int_reg::_RsvIdx , gem5::PowerISA::int_reg::_RsvLenIdx , gem5::PowerISA::int_reg::_RsvAddrIdx , gem5::PowerISA::int_reg::NumRegs }

Functions
constexpr RegClass	gem5::PowerISA::intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)

Variables
constexpr RegId	gem5::PowerISA::int_reg::R0 = intRegClass[_R0Idx]
constexpr RegId	gem5::PowerISA::int_reg::R1 = intRegClass[_R1Idx]
constexpr RegId	gem5::PowerISA::int_reg::R2 = intRegClass[_R2Idx]
constexpr RegId	gem5::PowerISA::int_reg::R3 = intRegClass[_R3Idx]
constexpr RegId	gem5::PowerISA::int_reg::R4 = intRegClass[_R4Idx]
constexpr RegId	gem5::PowerISA::int_reg::R5 = intRegClass[_R5Idx]
constexpr RegId	gem5::PowerISA::int_reg::R6 = intRegClass[_R6Idx]
constexpr RegId	gem5::PowerISA::int_reg::R7 = intRegClass[_R7Idx]
constexpr RegId	gem5::PowerISA::int_reg::R8 = intRegClass[_R8Idx]
constexpr RegId	gem5::PowerISA::int_reg::R9 = intRegClass[_R9Idx]
constexpr RegId	gem5::PowerISA::int_reg::R10 = intRegClass[_R10Idx]
constexpr RegId	gem5::PowerISA::int_reg::R11 = intRegClass[_R11Idx]
constexpr RegId	gem5::PowerISA::int_reg::R12 = intRegClass[_R12Idx]
constexpr RegId	gem5::PowerISA::int_reg::R13 = intRegClass[_R13Idx]
constexpr RegId	gem5::PowerISA::int_reg::R14 = intRegClass[_R14Idx]
constexpr RegId	gem5::PowerISA::int_reg::R15 = intRegClass[_R15Idx]
constexpr RegId	gem5::PowerISA::int_reg::R16 = intRegClass[_R16Idx]
constexpr RegId	gem5::PowerISA::int_reg::R17 = intRegClass[_R17Idx]
constexpr RegId	gem5::PowerISA::int_reg::R18 = intRegClass[_R18Idx]
constexpr RegId	gem5::PowerISA::int_reg::R19 = intRegClass[_R19Idx]
constexpr RegId	gem5::PowerISA::int_reg::R20 = intRegClass[_R20Idx]
constexpr RegId	gem5::PowerISA::int_reg::R21 = intRegClass[_R21Idx]
constexpr RegId	gem5::PowerISA::int_reg::R22 = intRegClass[_R22Idx]
constexpr RegId	gem5::PowerISA::int_reg::R23 = intRegClass[_R23Idx]
constexpr RegId	gem5::PowerISA::int_reg::R24 = intRegClass[_R24Idx]
constexpr RegId	gem5::PowerISA::int_reg::R25 = intRegClass[_R25Idx]
constexpr RegId	gem5::PowerISA::int_reg::R26 = intRegClass[_R26Idx]
constexpr RegId	gem5::PowerISA::int_reg::R27 = intRegClass[_R27Idx]
constexpr RegId	gem5::PowerISA::int_reg::R28 = intRegClass[_R28Idx]
constexpr RegId	gem5::PowerISA::int_reg::R29 = intRegClass[_R29Idx]
constexpr RegId	gem5::PowerISA::int_reg::R30 = intRegClass[_R30Idx]
constexpr RegId	gem5::PowerISA::int_reg::R31 = intRegClass[_R31Idx]
constexpr RegId	gem5::PowerISA::int_reg::Cr = intRegClass[_CrIdx]
constexpr RegId	gem5::PowerISA::int_reg::Xer = intRegClass[_XerIdx]
constexpr RegId	gem5::PowerISA::int_reg::Lr = intRegClass[_LrIdx]
constexpr RegId	gem5::PowerISA::int_reg::Ctr = intRegClass[_CtrIdx]
constexpr RegId	gem5::PowerISA::int_reg::Tar = intRegClass[_TarIdx]
constexpr RegId	gem5::PowerISA::int_reg::Fpscr = intRegClass[_FpscrIdx]
constexpr RegId	gem5::PowerISA::int_reg::Msr = intRegClass[_MsrIdx]
constexpr RegId	gem5::PowerISA::int_reg::Rsv = intRegClass[_RsvIdx]
constexpr RegId	gem5::PowerISA::int_reg::RsvLen = intRegClass[_RsvLenIdx]
constexpr RegId	gem5::PowerISA::int_reg::RsvAddr = intRegClass[_RsvAddrIdx]
constexpr auto &	gem5::PowerISA::ReturnValueReg = int_reg::R3
constexpr auto &	gem5::PowerISA::ArgumentReg0 = int_reg::R3
constexpr auto &	gem5::PowerISA::ArgumentReg1 = int_reg::R4
constexpr auto &	gem5::PowerISA::ArgumentReg2 = int_reg::R5
constexpr auto &	gem5::PowerISA::ArgumentReg3 = int_reg::R6
constexpr auto &	gem5::PowerISA::ArgumentReg4 = int_reg::R7
constexpr auto &	gem5::PowerISA::ArgumentReg5 = int_reg::R8
constexpr auto &	gem5::PowerISA::StackPointerReg = int_reg::R1
constexpr auto &	gem5::PowerISA::TOCPointerReg = int_reg::R2
constexpr auto &	gem5::PowerISA::ThreadPointerReg = int_reg::R13