gem5 v24.0.0.0
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#include <list>
#include <utility>
#include "base/statistics.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/timebuf.hh"
#include "sim/probe/probe.hh"
Go to the source code of this file.
Classes | |
class | gem5::o3::Rename |
Rename handles both single threaded and SMT rename. More... | |
struct | gem5::o3::Rename::RenameHistory |
Holds the information for each destination register rename. More... | |
struct | gem5::o3::Rename::FreeEntries |
Structures whose free entries impact the amount of instructions that can be renamed. More... | |
struct | gem5::o3::Rename::Stalls |
Source of possible stalls. More... | |
struct | gem5::o3::Rename::RenameStats |
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved. | |
namespace | gem5::o3 |