rename.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012, 2017 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2004-2006 The Regents of The University of Michigan
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_O3_RENAME_HH__
#define __CPU_O3_RENAME_HH__
 
#include <list>
#include <utility>
 
#include "base/statistics.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/iew.hh"
#include "cpu/o3/limits.hh"
#include "cpu/timebuf.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class Rename
{
  public:
    // A deque is used to queue the instructions. Barrier insts must
    // be added to the front of the queue, which is the only reason for
    // using a deque instead of a queue. (Most other stages use a
    // queue)
    typedef std::deque<DynInstPtr> InstQueue;
 
  public:
    enum RenameStatus
    {
        Active,
        Inactive
    };
 
    enum ThreadStatus
    {
        Running,
        Idle,
        StartSquash,
        Squashing,
        Blocked,
        Unblocking,
        SerializeStall
    };
 
  private:
    RenameStatus _status;
 
    ThreadStatus renameStatus[MaxThreads];
 
    typedef std::pair<InstSeqNum, PhysRegIdPtr> SeqNumRegPair;
    ProbePointArg<DynInstPtr> *ppRename;
    ProbePointArg<SeqNumRegPair> *ppSquashInRename;
 
  public:
    Rename(CPU *_cpu, const BaseO3CPUParams &params);
 
    std::string name() const;
 
    void regProbePoints();
 
    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 
    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
 
    void setIEWStage(IEW *iew_stage) { iew_ptr = iew_stage; }
 
    void
    setCommitStage(Commit *commit_stage)
    {
        commit_ptr = commit_stage;
    }
 
  private:
    IEW *iew_ptr;
 
    Commit *commit_ptr;
 
  public:
    void startupStage();
 
    void clearStates(ThreadID tid);
 
    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
    void setRenameMap(UnifiedRenameMap rm_ptr[MaxThreads]);
 
    void setFreeList(UnifiedFreeList *fl_ptr);
 
    void setScoreboard(Scoreboard *_scoreboard);
 
    void drainSanityCheck() const;
 
    bool isDrained() const;
 
    void takeOverFrom();
 
    void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
 
    void tick();
 
    void dumpHistory();
 
  private:
    void resetStage();
 
    void rename(bool &status_change, ThreadID tid);
 
    void renameInsts(ThreadID tid);
 
    void skidInsert(ThreadID tid);
 
    void sortInsts();
 
    bool skidsEmpty();
 
    void updateStatus();
 
    bool block(ThreadID tid);
 
    bool unblock(ThreadID tid);
 
    void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
 
    void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
 
    void renameSrcRegs(const DynInstPtr &inst, ThreadID tid);
 
    void renameDestRegs(const DynInstPtr &inst, ThreadID tid);
 
    int calcFreeROBEntries(ThreadID tid);
 
    int calcFreeIQEntries(ThreadID tid);
 
    int calcFreeLQEntries(ThreadID tid);
 
    int calcFreeSQEntries(ThreadID tid);
 
    unsigned validInsts();
 
    void readStallSignals(ThreadID tid);
 
    bool checkStall(ThreadID tid);
 
    void readFreeEntries(ThreadID tid);
 
    bool checkSignalsAndUpdate(ThreadID tid);
 
    void serializeAfter(InstQueue &inst_list, ThreadID tid);
 
    struct RenameHistory
    {
        RenameHistory(InstSeqNum _instSeqNum, const RegId& _archReg,
                      PhysRegIdPtr _newPhysReg,
                      PhysRegIdPtr _prevPhysReg)
            : instSeqNum(_instSeqNum), archReg(_archReg),
              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
        {
        }
 
        InstSeqNum instSeqNum;
        RegId archReg;
        PhysRegIdPtr newPhysReg;
        PhysRegIdPtr prevPhysReg;
    };
 
    std::list<RenameHistory> historyBuffer[MaxThreads];
 
    CPU *cpu;
 
    TimeBuffer<TimeStruct> *timeBuffer;
 
    TimeBuffer<TimeStruct>::wire fromIEW;
 
    TimeBuffer<TimeStruct>::wire fromCommit;
 
    TimeBuffer<TimeStruct>::wire toDecode;
 
    TimeBuffer<RenameStruct> *renameQueue;
 
    TimeBuffer<RenameStruct>::wire toIEW;
 
    TimeBuffer<DecodeStruct> *decodeQueue;
 
    TimeBuffer<DecodeStruct>::wire fromDecode;
 
    InstQueue insts[MaxThreads];
 
    InstQueue skidBuffer[MaxThreads];
 
    UnifiedRenameMap *renameMap[MaxThreads];
 
    UnifiedFreeList *freeList;
 
    std::list<ThreadID> *activeThreads;
 
    Scoreboard *scoreboard;
 
    int instsInProgress[MaxThreads];
 
    int loadsInProgress[MaxThreads];
 
    int storesInProgress[MaxThreads];
 
    bool wroteToTimeBuffer;
 
    struct FreeEntries
    {
        unsigned iqEntries;
        unsigned robEntries;
        unsigned lqEntries;
        unsigned sqEntries;
    };
 
    FreeEntries freeEntries[MaxThreads];
 
    bool emptyROB[MaxThreads];
 
    struct Stalls
    {
        bool iew;
        bool commit;
    };
 
    Stalls stalls[MaxThreads];
 
    DynInstPtr serializeInst[MaxThreads];
 
    bool serializeOnNextInst[MaxThreads];
 
    int iewToRenameDelay;
 
    int decodeToRenameDelay;
 
    unsigned commitToRenameDelay;
 
    unsigned renameWidth;
 
    unsigned toIEWIndex;
 
    bool blockThisCycle;
 
    bool resumeSerialize;
 
    bool resumeUnblocking;
 
    ThreadID numThreads;
 
    unsigned skidBufferMax;
 
    enum FullSource
    {
        ROB,
        IQ,
        LQ,
        SQ,
        NONE
    };
 
    void incrFullStat(const FullSource &source);
 
    struct RenameStats : public statistics::Group
    {
        RenameStats(statistics::Group *parent);
 
        statistics::Scalar squashCycles;
        statistics::Scalar idleCycles;
        statistics::Scalar blockCycles;
        statistics::Scalar serializeStallCycles;
        statistics::Scalar runCycles;
        statistics::Scalar unblockCycles;
        statistics::Scalar renamedInsts;
        statistics::Scalar squashedInsts;
        statistics::Scalar ROBFullEvents;
        statistics::Scalar IQFullEvents;
        statistics::Scalar LQFullEvents;
        statistics::Scalar SQFullEvents;
        statistics::Scalar fullRegistersEvents;
        statistics::Scalar renamedOperands;
        statistics::Scalar lookups;
        statistics::Scalar intLookups;
        statistics::Scalar fpLookups;
        statistics::Scalar vecLookups;
        statistics::Scalar vecPredLookups;
        statistics::Scalar committedMaps;
        statistics::Scalar undoneMaps;
        statistics::Scalar serializing;
        statistics::Scalar tempSerializing;
        statistics::Scalar skidInsts;
    } stats;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_RENAME_HH__