iew.hh

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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * All rights reserved.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __CPU_O3_IEW_HH__
#define __CPU_O3_IEW_HH__
 
#include <queue>
#include <set>
 
#include "base/statistics.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
#include "sim/probe/probe.hh"
 
namespace gem5
{
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class FUPool;
 
class IEW
{
  public:
    enum Status
    {
        Active,
        Inactive
    };
 
    enum StageStatus
    {
        Running,
        Blocked,
        Idle,
        StartSquash,
        Squashing,
        Unblocking
    };
 
  private:
    Status _status;
    StageStatus dispatchStatus[MaxThreads];
    StageStatus exeStatus;
    StageStatus wbStatus;
 
    ProbePointArg<DynInstPtr> *ppMispredict;
    ProbePointArg<DynInstPtr> *ppDispatch;
    ProbePointArg<DynInstPtr> *ppExecute;
    ProbePointArg<DynInstPtr> *ppToCommit;
 
  public:
    IEW(CPU *_cpu, const BaseO3CPUParams &params);
 
    std::string name() const;
 
    void regProbePoints();
 
    void startupStage();
 
    void clearStates(ThreadID tid);
 
    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 
    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 
    void setActiveThreads(std::list<ThreadID> *at_ptr);
 
    void setScoreboard(Scoreboard *sb_ptr);
 
    void drainSanityCheck() const;
 
    bool isDrained() const;
 
    void takeOverFrom();
 
    void squash(ThreadID tid);
 
    void wakeDependents(const DynInstPtr &inst);
 
    void rescheduleMemInst(const DynInstPtr &inst);
 
    void replayMemInst(const DynInstPtr &inst);
 
    void blockMemInst(const DynInstPtr &inst);
 
    void cacheUnblocked();
 
    void instToCommit(const DynInstPtr &inst);
 
    void skidInsert(ThreadID tid);
 
    int skidCount();
 
    bool skidsEmpty();
 
    void updateStatus();
 
    void resetEntries();
 
    void wakeCPU();
 
    void activityThisCycle();
 
    void activateStage();
 
    void deactivateStage();
 
    bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 
    bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 
    void checkMisprediction(const DynInstPtr &inst);
 
    // hardware transactional memory
    // For debugging purposes, it is useful to keep track of the most recent
    // htmUid that has been committed (architecturally, not transactionally)
    // to ensure that the core and the memory subsystem are observing
    // correct ordering constraints.
    void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
    {
        ldstQueue.setLastRetiredHtmUid(tid, htmUid);
    }
 
  private:
    void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
 
    void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
 
    void block(ThreadID tid);
 
    void unblock(ThreadID tid);
 
    void dispatch(ThreadID tid);
 
    void dispatchInsts(ThreadID tid);
 
    void executeInsts();
 
    void writebackInsts();
 
    bool checkStall(ThreadID tid);
 
    void checkSignalsAndUpdate(ThreadID tid);
 
    void emptyRenameInsts(ThreadID tid);
 
    void sortInsts();
 
  public:
    void tick();
 
  private:
    void updateExeInstStats(const DynInstPtr &inst);
 
    TimeBuffer<TimeStruct> *timeBuffer;
 
    TimeBuffer<TimeStruct>::wire toFetch;
 
    TimeBuffer<TimeStruct>::wire fromCommit;
 
    TimeBuffer<TimeStruct>::wire toRename;
 
    TimeBuffer<RenameStruct> *renameQueue;
 
    TimeBuffer<RenameStruct>::wire fromRename;
 
    TimeBuffer<IssueStruct> issueToExecQueue;
 
    TimeBuffer<IssueStruct>::wire fromIssue;
 
    TimeBuffer<IEWStruct> *iewQueue;
 
    TimeBuffer<IEWStruct>::wire toCommit;
 
    std::queue<DynInstPtr> insts[MaxThreads];
 
    std::queue<DynInstPtr> skidBuffer[MaxThreads];
 
    Scoreboard* scoreboard;
 
  private:
    CPU *cpu;
 
    bool wroteToTimeBuffer;
 
    void printAvailableInsts();
 
  public:
    InstructionQueue instQueue;
 
    LSQ ldstQueue;
 
    FUPool *fuPool;
    bool updateLSQNextCycle;
 
  private:
    bool fetchRedirect[MaxThreads];
 
    bool updatedQueues;
 
    Cycles commitToIEWDelay;
 
    Cycles renameToIEWDelay;
 
    Cycles issueToExecuteDelay;
 
    unsigned dispatchWidth;
 
    unsigned issueWidth;
 
    unsigned wbNumInst;
 
    unsigned wbCycle;
 
    unsigned wbWidth;
 
    ThreadID numThreads;
 
    std::list<ThreadID> *activeThreads;
 
    unsigned skidBufferMax;
 
 
    struct IEWStats : public statistics::Group
    {
        IEWStats(CPU *cpu);
 
        statistics::Scalar idleCycles;
        statistics::Scalar squashCycles;
        statistics::Scalar blockCycles;
        statistics::Scalar unblockCycles;
        statistics::Scalar dispatchedInsts;
        statistics::Scalar dispSquashedInsts;
        statistics::Scalar dispLoadInsts;
        statistics::Scalar dispStoreInsts;
        statistics::Scalar dispNonSpecInsts;
        statistics::Scalar iqFullEvents;
        statistics::Scalar lsqFullEvents;
        statistics::Scalar memOrderViolationEvents;
        statistics::Scalar predictedTakenIncorrect;
        statistics::Scalar predictedNotTakenIncorrect;
        statistics::Formula branchMispredicts;
 
        struct ExecutedInstStats : public statistics::Group
        {
            ExecutedInstStats(CPU *cpu);
 
            statistics::Scalar numSquashedInsts;
            statistics::Vector numSwp;
        } executedInstStats;
 
        statistics::Vector instsToCommit;
        statistics::Vector writebackCount;
        statistics::Vector producerInst;
        statistics::Vector consumerInst;
        statistics::Formula wbRate;
        statistics::Formula wbFanout;
    } iewStats;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_IEW_HH__