gem5  v21.1.0.2
iew.hh
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40 
41 #ifndef __CPU_O3_IEW_HH__
42 #define __CPU_O3_IEW_HH__
43 
44 #include <queue>
45 #include <set>
46 
47 #include "base/statistics.hh"
48 #include "cpu/o3/comm.hh"
49 #include "cpu/o3/dyn_inst_ptr.hh"
50 #include "cpu/o3/inst_queue.hh"
51 #include "cpu/o3/limits.hh"
52 #include "cpu/o3/lsq.hh"
53 #include "cpu/o3/scoreboard.hh"
54 #include "cpu/timebuf.hh"
55 #include "debug/IEW.hh"
56 #include "sim/probe/probe.hh"
57 
58 namespace gem5
59 {
60 
61 struct O3CPUParams;
62 
63 namespace o3
64 {
65 
66 class FUPool;
67 
87 class IEW
88 {
89  public:
93  enum Status
94  {
97  };
98 
101  {
108  };
109 
110  private:
119 
127 
128  public:
130  IEW(CPU *_cpu, const O3CPUParams &params);
131 
133  std::string name() const;
134 
136  void regProbePoints();
137 
139  void startupStage();
140 
142  void clearStates(ThreadID tid);
143 
146 
149 
151  void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
152 
155 
157  void setScoreboard(Scoreboard *sb_ptr);
158 
160  void drainSanityCheck() const;
161 
163  bool isDrained() const;
164 
166  void takeOverFrom();
167 
169  void squash(ThreadID tid);
170 
172  void wakeDependents(const DynInstPtr &inst);
173 
177  void rescheduleMemInst(const DynInstPtr &inst);
178 
180  void replayMemInst(const DynInstPtr &inst);
181 
183  void blockMemInst(const DynInstPtr &inst);
184 
186  void cacheUnblocked();
187 
189  void instToCommit(const DynInstPtr &inst);
190 
192  void skidInsert(ThreadID tid);
193 
195  int skidCount();
196 
198  bool skidsEmpty();
199 
201  void updateStatus();
202 
204  void resetEntries();
205 
209  void wakeCPU();
210 
212  void activityThisCycle();
213 
215  void activateStage();
216 
218  void deactivateStage();
219 
221  bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
222 
224  bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
225 
227  void checkMisprediction(const DynInstPtr &inst);
228 
229  // hardware transactional memory
230  // For debugging purposes, it is useful to keep track of the most recent
231  // htmUid that has been committed (architecturally, not transactionally)
232  // to ensure that the core and the memory subsystem are observing
233  // correct ordering constraints.
234  void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
235  {
236  ldstQueue.setLastRetiredHtmUid(tid, htmUid);
237  }
238 
239  private:
243  void squashDueToBranch(const DynInstPtr &inst, ThreadID tid);
244 
248  void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid);
249 
251  void block(ThreadID tid);
252 
256  void unblock(ThreadID tid);
257 
259  void dispatch(ThreadID tid);
260 
262  void dispatchInsts(ThreadID tid);
263 
268  void executeInsts();
269 
275  void writebackInsts();
276 
278  bool checkStall(ThreadID tid);
279 
282 
284  void emptyRenameInsts(ThreadID tid);
285 
287  void sortInsts();
288 
289  public:
293  void tick();
294 
295  private:
297  void updateExeInstStats(const DynInstPtr &inst);
298 
301 
304 
307 
310 
313 
316 
319 
322 
328 
331 
333  std::queue<DynInstPtr> insts[MaxThreads];
334 
336  std::queue<DynInstPtr> skidBuffer[MaxThreads];
337 
340 
341  private:
344 
349 
351  void printAvailableInsts();
352 
353  public:
356 
359 
366 
367  private:
370 
375 
378 
381 
388 
390  unsigned dispatchWidth;
391 
393  unsigned issueWidth;
394 
396  unsigned wbNumInst;
397 
403  unsigned wbCycle;
404 
406  unsigned wbWidth;
407 
410 
413 
415  unsigned skidBufferMax;
416 
417 
418  struct IEWStats : public statistics::Group
419  {
420  IEWStats(CPU *cpu);
421 
453 
455  {
457 
478 
491  } iewStats;
492 };
493 
494 } // namespace o3
495 } // namespace gem5
496 
497 #endif // __CPU_O3_IEW_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::IEW::skidCount
int skidCount()
Returns the max of the number of entries in all of the skid buffers.
Definition: iew.cc:618
gem5::o3::IEW::IEWStats::unblockCycles
statistics::Scalar unblockCycles
Stat for total number of unblocking cycles.
Definition: iew.hh:429
gem5::o3::IEW::IEWStats::dispStoreInsts
statistics::Scalar dispStoreInsts
Stat for total number of dispatched store instructions.
Definition: iew.hh:437
gem5::o3::IEW::IEWStats::ExecutedInstStats
Definition: iew.hh:454
gem5::o3::IEW::setTimeBuffer
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets main time buffer used for backwards communication.
Definition: iew.cc:305
gem5::o3::IEW::toFetch
TimeBuffer< TimeStruct >::wire toFetch
Wire to write information heading to previous stages.
Definition: iew.hh:303
gem5::o3::IEW::insts
std::queue< DynInstPtr > insts[MaxThreads]
Queue of all instructions coming from rename this cycle.
Definition: iew.hh:333
gem5::o3::IEW::skidsEmpty
bool skidsEmpty()
Returns if all of the skid buffers are empty.
Definition: iew.cc:636
gem5::o3::IEW::IEWStats::executedInstStats
gem5::o3::IEW::IEWStats::ExecutedInstStats executedInstStats
gem5::o3::IEW::ppToCommit
ProbePointArg< DynInstPtr > * ppToCommit
To probe when instruction execution is complete.
Definition: iew.hh:126
gem5::o3::IEW::IEWStats::wbRate
statistics::Formula wbRate
Number of instructions per cycle written back.
Definition: iew.hh:488
gem5::o3::IEW::renameQueue
TimeBuffer< RenameStruct > * renameQueue
Rename instruction queue interface.
Definition: iew.hh:312
gem5::o3::IEW::IEWStats::blockCycles
statistics::Scalar blockCycles
Stat for total number of blocking cycles.
Definition: iew.hh:427
gem5::o3::IEW::IEWStats
Definition: iew.hh:418
gem5::o3::IEW::IEWStats::producerInst
statistics::Vector producerInst
Number of instructions that wake consumers.
Definition: iew.hh:484
gem5::o3::IEW::checkSignalsAndUpdate
void checkSignalsAndUpdate(ThreadID tid)
Processes inputs and changes state accordingly.
Definition: iew.cc:708
gem5::o3::IEW::updateExeInstStats
void updateExeInstStats(const DynInstPtr &inst)
Updates execution stats based on the instruction.
Definition: iew.cc:1562
gem5::o3::IEW::dispatchStatus
StageStatus dispatchStatus[MaxThreads]
Dispatch status.
Definition: iew.hh:114
gem5::o3::InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:98
gem5::o3::IEW::updateStatus
void updateStatus()
Updates overall IEW status based on all of the stages' statuses.
Definition: iew.cc:652
gem5::o3::IEW::replayMemInst
void replayMemInst(const DynInstPtr &inst)
Re-executes all rescheduled memory instructions.
Definition: iew.cc:551
gem5::o3::IEW::IEWStats::ExecutedInstStats::numStoreInsts
statistics::Formula numStoreInsts
Number of executed store instructions.
Definition: iew.hh:474
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRefs
statistics::Vector numRefs
Number of executed meomory references.
Definition: iew.hh:470
gem5::o3::IEW::ppMispredict
ProbePointArg< DynInstPtr > * ppMispredict
Probe points.
Definition: iew.hh:121
gem5::o3::IEW::Active
@ Active
Definition: iew.hh:95
gem5::o3::IEW::Unblocking
@ Unblocking
Definition: iew.hh:107
gem5::o3::IEW::IEWStats::predictedNotTakenIncorrect
statistics::Scalar predictedNotTakenIncorrect
Stat for total number of incorrect predicted not taken branches.
Definition: iew.hh:449
gem5::o3::IEW::Status
Status
Overall IEW stage status.
Definition: iew.hh:93
gem5::o3::IEW::takeOverFrom
void takeOverFrom()
Takes over from another CPU's thread.
Definition: iew.cc:392
gem5::o3::IEW::checkMisprediction
void checkMisprediction(const DynInstPtr &inst)
Check misprediction
Definition: iew.cc:1593
gem5::o3::IEW::fromRename
TimeBuffer< RenameStruct >::wire fromRename
Wire to get rename's output from rename queue.
Definition: iew.hh:315
gem5::o3::IEW::iewStats
gem5::o3::IEW::IEWStats iewStats
gem5::o3::IEW::clearStates
void clearStates(ThreadID tid)
Clear all thread-specific states.
Definition: iew.cc:293
gem5::o3::IEW::wakeDependents
void wakeDependents(const DynInstPtr &inst)
Wakes all dependents of a completed instruction.
Definition: iew.cc:539
gem5::o3::IEW::commitToIEWDelay
Cycles commitToIEWDelay
Commit to IEW delay.
Definition: iew.hh:377
gem5::o3::LSQ
Definition: lsq.hh:75
gem5::o3::IEW::IEWStats::iqFullEvents
statistics::Scalar iqFullEvents
Stat for number of times the IQ becomes full.
Definition: iew.hh:441
gem5::o3::IEW::issueToExecQueue
TimeBuffer< IssueStruct > issueToExecQueue
Issue stage queue.
Definition: iew.hh:318
gem5::o3::IEW::IEWStats::wbFanout
statistics::Formula wbFanout
Average number of woken instructions per writeback.
Definition: iew.hh:490
gem5::o3::Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:53
gem5::o3::IEW::skidInsert
void skidInsert(ThreadID tid)
Inserts unused instructions of a thread into the skid buffer.
Definition: iew.cc:597
gem5::o3::IEW::writebackInsts
void writebackInsts()
Writebacks instructions.
Definition: iew.cc:1383
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::o3::IEW::emptyRenameInsts
void emptyRenameInsts(ThreadID tid)
Removes instructions from rename from a thread's instruction list.
Definition: iew.cc:784
gem5::o3::IEW::activeThreads
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Definition: iew.hh:412
gem5::o3::IEW::exeStatus
StageStatus exeStatus
Execute status.
Definition: iew.hh:116
gem5::o3::IEW::toCommit
TimeBuffer< IEWStruct >::wire toCommit
Wire to write infromation heading to commit.
Definition: iew.hh:330
gem5::o3::IEW::dispatchInsts
void dispatchInsts(ThreadID tid)
Dispatches instructions to IQ and LSQ.
Definition: iew.cc:879
gem5::o3::IEW::sortInsts
void sortInsts()
Sorts instructions coming from rename into lists separated by thread.
Definition: iew.cc:771
gem5::o3::IEW::checkStall
bool checkStall(ThreadID tid)
Checks if any of the stall conditions are currently true.
Definition: iew.cc:692
gem5::o3::IEW::toRename
TimeBuffer< TimeStruct >::wire toRename
Wire to write information heading to previous stages.
Definition: iew.hh:309
gem5::o3::IEW::squash
void squash(ThreadID tid)
Squashes instructions in IEW for a specific thread.
Definition: iew.cc:419
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSquashedInsts
statistics::Scalar numSquashedInsts
Stat for total number of squashed instructions skipped at execute.
Definition: iew.hh:464
gem5::o3::IEW::IEWStats::writebackCount
statistics::Vector writebackCount
Number of instructions that writeback.
Definition: iew.hh:482
gem5::o3::IEW::Inactive
@ Inactive
Definition: iew.hh:96
gem5::o3::IEW::resetEntries
void resetEntries()
Resets entries of the IQ and the LSQ.
gem5::o3::IEW::wakeCPU
void wakeCPU()
Tells the CPU to wakeup if it has descheduled itself due to no activity.
Definition: iew.cc:805
gem5::o3::IEW::Blocked
@ Blocked
Definition: iew.hh:103
gem5::o3::IEW::startupStage
void startupStage()
Initializes stage; sends back the number of free IQ and LSQ entries.
Definition: iew.cc:270
gem5::RefCountingPtr< DynInst >
gem5::o3::IEW::rescheduleMemInst
void rescheduleMemInst(const DynInstPtr &inst)
Tells memory dependence unit that a memory instruction needs to be rescheduled.
Definition: iew.cc:545
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::IEW::Squashing
@ Squashing
Definition: iew.hh:106
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::IEW::wroteToTimeBuffer
bool wroteToTimeBuffer
Records if IEW has written to the time buffer this cycle, so that the CPU can deschedule itself if th...
Definition: iew.hh:348
gem5::o3::IEW::fromCommit
TimeBuffer< TimeStruct >::wire fromCommit
Wire to get commit's output from backwards time buffer.
Definition: iew.hh:306
timebuf.hh
gem5::o3::IEW::IEWStats::ExecutedInstStats::numLoadInsts
statistics::Vector numLoadInsts
Stat for total number of executed load instructions.
Definition: iew.hh:461
gem5::o3::IEW::instQueue
InstructionQueue instQueue
Instruction queue.
Definition: iew.hh:355
comm.hh
gem5::o3::IEW::IEWStats::consumerInst
statistics::Vector consumerInst
Number of instructions that wake up from producers.
Definition: iew.hh:486
gem5::o3::IEW::block
void block(ThreadID tid)
Sets Dispatch to blocked, and signals back to other stages to block.
Definition: iew.cc:505
gem5::o3::IEW::IEWStats::dispSquashedInsts
statistics::Scalar dispSquashedInsts
Stat for total number of squashed instructions dispatch skips.
Definition: iew.hh:433
gem5::o3::IEW::_status
Status _status
Overall stage status.
Definition: iew.hh:112
gem5::o3::IEW::IEWStats::instsToCommit
statistics::Vector instsToCommit
Number of instructions sent to commit.
Definition: iew.hh:480
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::IEW::isDrained
bool isDrained() const
Has the stage drained?
Definition: iew.cc:355
gem5::o3::IEW::StartSquash
@ StartSquash
Definition: iew.hh:105
gem5::o3::IEW::squashDueToBranch
void squashDueToBranch(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a branch mispredict.
Definition: iew.cc:454
gem5::o3::IEW::IEW
IEW(CPU *_cpu, const O3CPUParams &params)
Constructs a IEW with the given parameters.
Definition: iew.cc:68
statistics.hh
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::IEW::StageStatus
StageStatus
Status for Issue, Execute, and Writeback stages.
Definition: iew.hh:100
gem5::o3::IEW::skidBuffer
std::queue< DynInstPtr > skidBuffer[MaxThreads]
Skid buffer between rename and IEW.
Definition: iew.hh:336
gem5::o3::IEW::fuPool
FUPool * fuPool
Pointer to the functional unit pool.
Definition: iew.hh:361
gem5::o3::IEW::IEWStats::ExecutedInstStats::numInsts
statistics::Scalar numInsts
Stat for total number of executed instructions.
Definition: iew.hh:459
gem5::o3::IEW::wbStatus
StageStatus wbStatus
Writeback status.
Definition: iew.hh:118
gem5::o3::IEW::activityThisCycle
void activityThisCycle()
Reports to the CPU that there is activity this cycle.
Definition: iew.cc:811
gem5::o3::IEW::renameToIEWDelay
Cycles renameToIEWDelay
Rename to IEW delay.
Definition: iew.hh:380
gem5::o3::IEW::iewQueue
TimeBuffer< IEWStruct > * iewQueue
IEW stage time buffer.
Definition: iew.hh:327
gem5::o3::IEW::IEWStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of idle cycles.
Definition: iew.hh:423
gem5::o3::IEW::IEWStats::branchMispredicts
statistics::Formula branchMispredicts
Stat for total number of mispredicted branches detected at execute.
Definition: iew.hh:452
gem5::o3::IEW::dispatchWidth
unsigned dispatchWidth
Width of dispatch, in instructions.
Definition: iew.hh:390
gem5::o3::IEW::Running
@ Running
Definition: iew.hh:102
gem5::o3::IEW::IEWStats::memOrderViolationEvents
statistics::Scalar memOrderViolationEvents
Stat for total number of memory ordering violation events.
Definition: iew.hh:445
gem5::o3::LSQ::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: lsq.cc:385
gem5::o3::IEW::tick
void tick()
Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and Writeback to run for one cycle.
Definition: iew.cc:1433
dyn_inst_ptr.hh
gem5::o3::IEW::IEWStats::dispatchedInsts
statistics::Scalar dispatchedInsts
Stat for total number of instructions dispatched.
Definition: iew.hh:431
gem5::o3::IEW::printAvailableInsts
void printAvailableInsts()
Debug function to print instructions that are issued this cycle.
Definition: iew.cc:1115
gem5::o3::IEW::IEWStats::ExecutedInstStats::ExecutedInstStats
ExecutedInstStats(CPU *cpu)
Definition: iew.cc:219
gem5::o3::IEW::IEWStats::ExecutedInstStats::numNop
statistics::Vector numNop
Number of executed nops.
Definition: iew.hh:468
gem5::o3::IEW::cpu
CPU * cpu
CPU pointer.
Definition: iew.hh:343
gem5::o3::IEW::wbWidth
unsigned wbWidth
Writeback width.
Definition: iew.hh:406
gem5::o3::IEW::timeBuffer
TimeBuffer< TimeStruct > * timeBuffer
Pointer to main time buffer used for backwards communication.
Definition: iew.hh:300
gem5::o3::IEW::IEWStats::predictedTakenIncorrect
statistics::Scalar predictedTakenIncorrect
Stat for total number of incorrect predicted taken branches.
Definition: iew.hh:447
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::IEW::fetchRedirect
bool fetchRedirect[MaxThreads]
Records if there is a fetch redirect on this cycle for each thread.
Definition: iew.hh:369
gem5::o3::IEW::IEWStats::squashCycles
statistics::Scalar squashCycles
Stat for total number of squashing cycles.
Definition: iew.hh:425
gem5::o3::IEW::IEWStats::dispLoadInsts
statistics::Scalar dispLoadInsts
Stat for total number of dispatched load instructions.
Definition: iew.hh:435
gem5::o3::IEW::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: iew.hh:234
gem5::o3::IEW::fromIssue
TimeBuffer< IssueStruct >::wire fromIssue
Wire to read information from the issue stage time queue.
Definition: iew.hh:321
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::IEW::unblock
void unblock(ThreadID tid)
Unblocks Dispatch if the skid buffer is empty, and signals back to other stages to unblock.
Definition: iew.cc:523
gem5::o3::IEW::issueWidth
unsigned issueWidth
Width of issue, in instructions.
Definition: iew.hh:393
gem5::o3::IEW::instToCommit
void instToCommit(const DynInstPtr &inst)
Sends an instruction to commit through the time buffer.
Definition: iew.cc:569
gem5::o3::IEW::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: iew.cc:383
gem5::o3::IEW::ppExecute
ProbePointArg< DynInstPtr > * ppExecute
To probe when instruction execution begins.
Definition: iew.hh:124
gem5::o3::IEW::IEWStats::dispNonSpecInsts
statistics::Scalar dispNonSpecInsts
Stat for total number of dispatched non speculative insts.
Definition: iew.hh:439
gem5::o3::IEW::blockMemInst
void blockMemInst(const DynInstPtr &inst)
Moves memory instruction onto the list of cache blocked instructions.
Definition: iew.cc:557
gem5::o3::LSQ::hasStoresToWB
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq.cc:705
gem5::o3::IEW::wbCycle
unsigned wbCycle
Cycle number within the queue of instructions being written back.
Definition: iew.hh:403
gem5::o3::IEW::cacheUnblocked
void cacheUnblocked()
Notifies that the cache has become unblocked.
Definition: iew.cc:563
gem5::o3::IEW::IEWStats::lsqFullEvents
statistics::Scalar lsqFullEvents
Stat for number of times the LSQ becomes full.
Definition: iew.hh:443
gem5::o3::IEW::hasStoresToWB
bool hasStoresToWB(ThreadID tid)
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:224
gem5::o3::IEW::wbNumInst
unsigned wbNumInst
Index into queue of instructions being written back.
Definition: iew.hh:396
gem5::o3::IEW::skidBufferMax
unsigned skidBufferMax
Maximum size of the skid buffer.
Definition: iew.hh:415
gem5::o3::IEW::deactivateStage
void deactivateStage()
Tells CPU that the IEW stage is inactive and idle.
Definition: iew.cc:825
gem5::o3::IEW::scoreboard
Scoreboard * scoreboard
Scoreboard pointer.
Definition: iew.hh:339
gem5::o3::IEW::ppDispatch
ProbePointArg< DynInstPtr > * ppDispatch
Definition: iew.hh:122
gem5::o3::IEW::setRenameQueue
void setRenameQueue(TimeBuffer< RenameStruct > *rq_ptr)
Sets time buffer for getting instructions coming from rename.
Definition: iew.cc:322
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::IEW::updateLSQNextCycle
bool updateLSQNextCycle
Records if the LSQ needs to be updated on the next cycle, so that IEW knows if there will be activity...
Definition: iew.hh:365
gem5::o3::IEW::numThreads
ThreadID numThreads
Number of active threads.
Definition: iew.hh:409
inst_queue.hh
gem5::o3::IEW::IEWStats::ExecutedInstStats::numSwp
statistics::Vector numSwp
Number of executed software prefetches.
Definition: iew.hh:466
gem5::o3::IEW::IEWStats::IEWStats
IEWStats(CPU *cpu)
Definition: iew.cc:145
gem5::o3::IEW::squashDueToMemOrder
void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid)
Sends commit proper information for a squash due to a memory order violation.
Definition: iew.cc:479
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
std::list< ThreadID >
probe.hh
gem5::o3::IEW::hasStoresToWB
bool hasStoresToWB()
Returns if the LSQ has any stores to writeback.
Definition: iew.hh:221
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
lsq.hh
gem5::o3::IEW::setIEWQueue
void setIEWQueue(TimeBuffer< IEWStruct > *iq_ptr)
Sets time buffer to pass on instructions to commit.
Definition: iew.cc:331
limits.hh
gem5::o3::IEW::dispatch
void dispatch(ThreadID tid)
Determines proper actions to take given Dispatch's status.
Definition: iew.cc:832
gem5::o3::IEW::updatedQueues
bool updatedQueues
Records if the queues have been changed (inserted or issued insts), so that IEW knows to broadcast th...
Definition: iew.hh:374
scoreboard.hh
gem5::o3::FUPool
Pool of FU's, specific to the new CPU model.
Definition: fu_pool.hh:75
gem5::o3::IEW::issueToExecuteDelay
Cycles issueToExecuteDelay
Issue to execute delay.
Definition: iew.hh:387
gem5::o3::IEW::Idle
@ Idle
Definition: iew.hh:104
gem5::o3::IEW::IEWStats::ExecutedInstStats::numBranches
statistics::Vector numBranches
Number of executed branches.
Definition: iew.hh:472
gem5::o3::IEW::activateStage
void activateStage()
Tells CPU that the IEW stage is active and running.
Definition: iew.cc:818
gem5::o3::IEW::IEWStats::ExecutedInstStats::numRate
statistics::Formula numRate
Number of instructions executed per cycle.
Definition: iew.hh:476
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::TimeBuffer::wire
Definition: timebuf.hh:59
gem5::o3::IEW::name
std::string name() const
Returns the name of the IEW stage.
Definition: iew.cc:119
gem5::o3::IEW::setScoreboard
void setScoreboard(Scoreboard *sb_ptr)
Sets pointer to the scoreboard.
Definition: iew.cc:349
gem5::o3::IEW::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets pointer to list of active threads.
Definition: iew.cc:340
gem5::o3::IEW::executeInsts
void executeInsts()
Executes instructions.
Definition: iew.cc:1137
gem5::o3::IEW::regProbePoints
void regProbePoints()
Registers probes.
Definition: iew.cc:125

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