pagetable.hh File Reference

#include "base/bitunion.hh"
#include "base/logging.hh"
#include "base/trie.hh"
#include "base/types.hh"
#include "sim/serialize.hh"

Go to the source code of this file.

Classes
struct	gem5::RiscvISA::TlbEntry

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::RiscvISA

Typedefs
typedef Trie< Addr, TlbEntry >	gem5::RiscvISA::TlbEntryTrie

Functions
	gem5::RiscvISA::BitUnion64 (SATP) Bitfield< 63
	gem5::RiscvISA::EndBitUnion (SATP) enum AddrXlateMode
	gem5::RiscvISA::BitUnion64 (PTESv39) Bitfield< 53
	gem5::RiscvISA::EndBitUnion (PTESv39) struct TlbEntry

Variables
	gem5::RiscvISA::mode
Bitfield< 59, 44 >	gem5::RiscvISA::asid
Bitfield< 43, 0 >	gem5::RiscvISA::ppn
const Addr	gem5::RiscvISA::VADDR_BITS = 39
const Addr	gem5::RiscvISA::LEVEL_BITS = 9
const Addr	gem5::RiscvISA::LEVEL_MASK = (1 << LEVEL_BITS) - 1
Bitfield< 53, 28 >	gem5::RiscvISA::ppn2
Bitfield< 27, 19 >	gem5::RiscvISA::ppn1
Bitfield< 18, 10 >	gem5::RiscvISA::ppn0
Bitfield< 7 >	gem5::RiscvISA::d
Bitfield< 6 >	gem5::RiscvISA::a
Bitfield< 5 >	gem5::RiscvISA::g
Bitfield< 4 >	gem5::RiscvISA::u
Bitfield< 3, 1 >	gem5::RiscvISA::perm
Bitfield< 3 >	gem5::RiscvISA::x
Bitfield< 2 >	gem5::RiscvISA::w
Bitfield< 1 >	gem5::RiscvISA::r
Bitfield< 0 >	gem5::RiscvISA::v