semihosting.hh File Reference

#include "arch/generic/semihosting.hh"
#include "arch/riscv/isa.hh"
#include "arch/riscv/regs/int.hh"
#include "cpu/thread_context.hh"
#include "sim/guest_abi.hh"
#include "sim/sim_object.hh"

Go to the source code of this file.

Classes
class	gem5::RiscvSemihosting
	Semihosting for RV32 and RV64. More...
struct	gem5::RiscvSemihosting::RiscvSemihostingAbi< ArgType >
class	gem5::RiscvSemihosting::RiscvSemihostingAbi< ArgType >::State
struct	gem5::RiscvSemihosting::Abi64
struct	gem5::RiscvSemihosting::Abi32
struct	gem5::guest_abi::Argument< RiscvSemihosting::Abi64, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > >
struct	gem5::guest_abi::Argument< RiscvSemihosting::Abi32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > > >
struct	gem5::guest_abi::Argument< Abi, RiscvSemihosting::InPlaceArg, typename std::enable_if_t< std::is_base_of_v< RiscvSemihosting::AbiBase, Abi > > >
struct	gem5::guest_abi::Result< Abi, RiscvSemihosting::RetErrno >

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::guest_abi