gem5  v22.0.0.2
static_inst.hh
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41 
42 #ifndef __CPU_STATIC_INST_HH__
43 #define __CPU_STATIC_INST_HH__
44 
45 #include <array>
46 #include <bitset>
47 #include <cstdint>
48 #include <memory>
49 #include <string>
50 
51 #include "arch/generic/pcstate.hh"
52 #include "base/logging.hh"
53 #include "base/refcnt.hh"
54 #include "cpu/op_class.hh"
55 #include "cpu/reg_class.hh"
56 #include "cpu/static_inst_fwd.hh"
57 #include "enums/StaticInstFlags.hh"
58 #include "sim/byteswap.hh"
59 
60 namespace gem5
61 {
62 
63 // forward declarations
64 class Packet;
65 
66 class ExecContext;
67 class ThreadContext;
68 
69 GEM5_DEPRECATED_NAMESPACE(Loader, loader);
70 namespace loader
71 {
72 class SymbolTable;
73 } // namespace loader
74 
75 namespace Trace
76 {
77 class InstRecord;
78 } // namespace Trace
79 
88 class StaticInst : public RefCounted, public StaticInstFlags
89 {
90  public:
91  using RegIdArrayPtr = RegId (StaticInst:: *)[];
92 
93  private:
96 
99 
100  protected:
101 
103  std::bitset<Num_Flags> flags;
104 
106  OpClass _opClass;
107 
109  uint8_t _numSrcRegs = 0;
110 
112  uint8_t _numDestRegs = 0;
113 
114  std::array<uint8_t, MiscRegClass + 1> _numTypedDestRegs = {};
115 
116  public:
117 
121 
122  uint8_t numSrcRegs() const { return _numSrcRegs; }
125  uint8_t numDestRegs() const { return _numDestRegs; }
127  uint8_t
129  {
130  return _numTypedDestRegs[type];
131  }
133 
138 
139 
140  bool isNop() const { return flags[IsNop]; }
141 
142  bool
143  isMemRef() const
144  {
145  return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
146  }
147  bool isLoad() const { return flags[IsLoad]; }
148  bool isStore() const { return flags[IsStore]; }
149  bool isAtomic() const { return flags[IsAtomic]; }
150  bool isStoreConditional() const { return flags[IsStoreConditional]; }
151  bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
152  bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
153  bool isPrefetch() const { return isInstPrefetch() ||
154  isDataPrefetch(); }
155 
156  bool isInteger() const { return flags[IsInteger]; }
157  bool isFloating() const { return flags[IsFloating]; }
158  bool isVector() const { return flags[IsVector]; }
159 
160  bool isControl() const { return flags[IsControl]; }
161  bool isCall() const { return flags[IsCall]; }
162  bool isReturn() const { return flags[IsReturn]; }
163  bool isDirectCtrl() const { return flags[IsDirectControl]; }
164  bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
165  bool isCondCtrl() const { return flags[IsCondControl]; }
166  bool isUncondCtrl() const { return flags[IsUncondControl]; }
167 
168  bool isSerializing() const { return flags[IsSerializing] ||
169  flags[IsSerializeBefore] ||
170  flags[IsSerializeAfter]; }
171  bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
172  bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
173  bool isSquashAfter() const { return flags[IsSquashAfter]; }
174  bool
176  {
177  return flags[IsReadBarrier] && flags[IsWriteBarrier];
178  }
179  bool isReadBarrier() const { return flags[IsReadBarrier]; }
180  bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
181  bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
182  bool isQuiesce() const { return flags[IsQuiesce]; }
183  bool isUnverifiable() const { return flags[IsUnverifiable]; }
184  bool isSyscall() const { return flags[IsSyscall]; }
185  bool isMacroop() const { return flags[IsMacroop]; }
186  bool isMicroop() const { return flags[IsMicroop]; }
187  bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
188  bool isLastMicroop() const { return flags[IsLastMicroop]; }
189  bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
190  // hardware transactional memory
191  // HtmCmds must be identified as such in order
192  // to provide them with necessary memory ordering semantics.
193  bool isHtmStart() const { return flags[IsHtmStart]; }
194  bool isHtmStop() const { return flags[IsHtmStop]; }
195  bool isHtmCancel() const { return flags[IsHtmCancel]; }
196 
197  bool
198  isHtmCmd() const
199  {
200  return isHtmStart() || isHtmStop() || isHtmCancel();
201  }
203 
204  void setFirstMicroop() { flags[IsFirstMicroop] = true; }
205  void setLastMicroop() { flags[IsLastMicroop] = true; }
206  void setDelayedCommit() { flags[IsDelayedCommit] = true; }
207  void setFlag(Flags f) { flags[f] = true; }
208 
210  OpClass opClass() const { return _opClass; }
211 
212 
215  const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
216 
217  void
218  setDestRegIdx(int i, const RegId &val)
219  {
220  (this->*_destRegIdxPtr)[i] = val;
221  }
222 
225  const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
226 
227  void
228  setSrcRegIdx(int i, const RegId &val)
229  {
230  (this->*_srcRegIdxPtr)[i] = val;
231  }
232 
235 
236  virtual uint64_t getEMI() const { return 0; }
237 
238  protected:
239 
246  void
248  {
249  _srcRegIdxPtr = src;
250  _destRegIdxPtr = dest;
251  }
252 
259  const char *mnemonic;
260 
265  mutable std::unique_ptr<std::string> cachedDisassembly;
266 
270  virtual std::string generateDisassembly(
271  Addr pc, const loader::SymbolTable *symtab) const = 0;
272 
278  StaticInst(const char *_mnemonic, OpClass op_class)
279  : _opClass(op_class), mnemonic(_mnemonic)
280  {}
281 
282  public:
283  virtual ~StaticInst() {};
284 
285  virtual Fault execute(ExecContext *xc,
286  Trace::InstRecord *traceData) const = 0;
287 
288  virtual Fault
290  {
291  panic("initiateAcc not defined!");
292  }
293 
294  virtual Fault
296  Trace::InstRecord *trace_data) const
297  {
298  panic("completeAcc not defined!");
299  }
300 
301  virtual void advancePC(PCStateBase &pc_state) const = 0;
302  virtual void advancePC(ThreadContext *tc) const;
303 
304  virtual std::unique_ptr<PCStateBase>
305  buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const
306  {
307  panic("buildRetPC not defined!");
308  }
309 
314  virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
315 
321  virtual std::unique_ptr<PCStateBase> branchTarget(
322  const PCStateBase &pc) const;
323 
331  virtual std::unique_ptr<PCStateBase> branchTarget(
332  ThreadContext *tc) const;
333 
341  virtual const std::string &disassemble(Addr pc,
342  const loader::SymbolTable *symtab=nullptr) const;
343 
348  void printFlags(std::ostream &outs, const std::string &separator) const;
349 
351  std::string getName() { return mnemonic; }
352 
353  protected:
354  template<typename T>
355  size_t
356  simpleAsBytes(void *buf, size_t max_size, const T &t)
357  {
358  size_t size = sizeof(T);
359  if (size <= max_size)
360  *reinterpret_cast<T *>(buf) = htole<T>(t);
361  return size;
362  }
363 
364  public:
376  virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
377 };
378 
379 } // namespace gem5
380 
381 #endif // __CPU_STATIC_INST_HH__
refcnt.hh
gem5::VegaISA::f
Bitfield< 56 > f
Definition: pagetable.hh:53
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:186
gem5::StaticInst::isWriteBarrier
bool isWriteBarrier() const
Definition: static_inst.hh:180
gem5::StaticInst::isSerializeBefore
bool isSerializeBefore() const
Definition: static_inst.hh:171
op_class.hh
gem5::StaticInst::isNonSpeculative
bool isNonSpeculative() const
Definition: static_inst.hh:181
gem5::StaticInst::isQuiesce
bool isQuiesce() const
Definition: static_inst.hh:182
gem5::StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:164
gem5::StaticInst::isUnverifiable
bool isUnverifiable() const
Definition: static_inst.hh:183
gem5::StaticInst::isNop
bool isNop() const
Definition: static_inst.hh:140
gem5::StaticInst::buildRetPC
virtual std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const
Definition: static_inst.hh:305
gem5::StaticInst::RegIdArrayPtr
RegId(StaticInst::*)[] RegIdArrayPtr
Definition: static_inst.hh:91
gem5::StaticInst::asBytes
virtual size_t asBytes(void *buf, size_t max_size)
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:376
gem5::StaticInst::isSerializeAfter
bool isSerializeAfter() const
Definition: static_inst.hh:172
gem5::StaticInst::numDestRegs
uint8_t numDestRegs(RegClassType type) const
Number of destination registers of a particular type.
Definition: static_inst.hh:128
gem5::StaticInst::~StaticInst
virtual ~StaticInst()
Definition: static_inst.hh:283
gem5::StaticInst::setSrcRegIdx
void setSrcRegIdx(int i, const RegId &val)
Definition: static_inst.hh:228
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:160
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:356
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:165
gem5::StaticInst::_numSrcRegs
uint8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::StaticInst
StaticInst(const char *_mnemonic, OpClass op_class)
Constructor.
Definition: static_inst.hh:278
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:187
gem5::StaticInst::setDestRegIdx
void setDestRegIdx(int i, const RegId &val)
Definition: static_inst.hh:218
gem5::StaticInst::_numTypedDestRegs
std::array< uint8_t, MiscRegClass+1 > _numTypedDestRegs
Definition: static_inst.hh:114
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:189
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:215
gem5::StaticInst::_opClass
OpClass _opClass
See opClass().
Definition: static_inst.hh:106
gem5::StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:210
gem5::StaticInst::isHtmCancel
bool isHtmCancel() const
Definition: static_inst.hh:195
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:157
gem5::StaticInst::isHtmCmd
bool isHtmCmd() const
Definition: static_inst.hh:198
gem5::Flags
Wrapper that groups a few flag bits under the same undelying container.
Definition: flags.hh:44
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:162
gem5::StaticInst::isHtmStart
bool isHtmStart() const
Definition: static_inst.hh:193
gem5::StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:152
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:88
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
gem5::StaticInst::isPrefetch
bool isPrefetch() const
Definition: static_inst.hh:153
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:225
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:149
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::StaticInst::isHtmStop
bool isHtmStop() const
Definition: static_inst.hh:194
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::StaticInst::getName
std::string getName()
Return name of machine instruction.
Definition: static_inst.hh:351
gem5::StaticInst::_numDestRegs
uint8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:112
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:147
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:148
gem5::StaticInst::_destRegIdxPtr
RegIdArrayPtr _destRegIdxPtr
See destRegIdx().
Definition: static_inst.hh:98
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:163
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:158
gem5::StaticInst::_srcRegIdxPtr
RegIdArrayPtr _srcRegIdxPtr
See srcRegIdx().
Definition: static_inst.hh:95
gem5::StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
gem5::StaticInst::setRegIdxArrays
void setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
Set the pointers which point to the arrays of source and destination register indices.
Definition: static_inst.hh:247
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:188
gem5::StaticInst::setLastMicroop
void setLastMicroop()
Definition: static_inst.hh:205
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:143
gem5::StaticInst::setDelayedCommit
void setDelayedCommit()
Definition: static_inst.hh:206
pcstate.hh
gem5::StaticInst::isReadBarrier
bool isReadBarrier() const
Definition: static_inst.hh:179
gem5::RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:60
gem5::StaticInst::getEMI
virtual uint64_t getEMI() const
Definition: static_inst.hh:236
gem5::StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:151
gem5::StaticInst::completeAcc
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
Definition: static_inst.hh:295
gem5::StaticInst::nullStaticInstPtr
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
Definition: static_inst.hh:234
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:56
gem5::StaticInst::initiateAcc
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:289
gem5::StaticInst::setFirstMicroop
void setFirstMicroop()
Definition: static_inst.hh:204
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:185
static_inst_fwd.hh
gem5::StaticInst::isSquashAfter
bool isSquashAfter() const
Definition: static_inst.hh:173
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::StaticInst::numDestRegs
uint8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:125
reg_class.hh
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:265
gem5::StaticInst::isSerializing
bool isSerializing() const
Definition: static_inst.hh:168
logging.hh
gem5::StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:156
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:161
gem5::StaticInst::branchTarget
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
gem5::StaticInst::numSrcRegs
uint8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:123
gem5::StaticInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: static_inst.hh:175
gem5::StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:166
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:184
gem5::StaticInst::isStoreConditional
bool isStoreConditional() const
Definition: static_inst.hh:150
gem5::StaticInst::setFlag
void setFlag(Flags f)
Definition: static_inst.hh:207
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:259
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:71
byteswap.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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