gem5  v21.2.1.1
static_inst.hh
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41 
42 #ifndef __CPU_STATIC_INST_HH__
43 #define __CPU_STATIC_INST_HH__
44 
45 #include <bitset>
46 #include <cstdint>
47 #include <memory>
48 #include <string>
49 
50 #include "arch/generic/pcstate.hh"
51 #include "base/logging.hh"
52 #include "base/refcnt.hh"
53 #include "cpu/op_class.hh"
54 #include "cpu/reg_class.hh"
55 #include "cpu/static_inst_fwd.hh"
56 #include "enums/StaticInstFlags.hh"
57 #include "sim/byteswap.hh"
58 
59 namespace gem5
60 {
61 
62 // forward declarations
63 class Packet;
64 
65 class ExecContext;
66 class ThreadContext;
67 
68 GEM5_DEPRECATED_NAMESPACE(Loader, loader);
69 namespace loader
70 {
71 class SymbolTable;
72 } // namespace loader
73 
74 namespace Trace
75 {
76 class InstRecord;
77 } // namespace Trace
78 
87 class StaticInst : public RefCounted, public StaticInstFlags
88 {
89  public:
90  using RegIdArrayPtr = RegId (StaticInst:: *)[];
91 
92  private:
95 
98 
99  protected:
100 
102  std::bitset<Num_Flags> flags;
103 
105  OpClass _opClass;
106 
108  int8_t _numSrcRegs = 0;
109 
111  int8_t _numDestRegs = 0;
112 
115 
116  int8_t _numFPDestRegs = 0;
117  int8_t _numIntDestRegs = 0;
118  int8_t _numCCDestRegs = 0;
120 
123  int8_t _numVecDestRegs = 0;
128  public:
129 
136 
137  int8_t numSrcRegs() const { return _numSrcRegs; }
140  int8_t numDestRegs() const { return _numDestRegs; }
142  int8_t numFPDestRegs() const { return _numFPDestRegs; }
144  int8_t numIntDestRegs() const { return _numIntDestRegs; }
146  int8_t numVecDestRegs() const { return _numVecDestRegs; }
148  int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
150  int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
152  int8_t numCCDestRegs() const { return _numCCDestRegs; }
154 
159 
160 
161  bool isNop() const { return flags[IsNop]; }
162 
163  bool
164  isMemRef() const
165  {
166  return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
167  }
168  bool isLoad() const { return flags[IsLoad]; }
169  bool isStore() const { return flags[IsStore]; }
170  bool isAtomic() const { return flags[IsAtomic]; }
171  bool isStoreConditional() const { return flags[IsStoreConditional]; }
172  bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
173  bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
174  bool isPrefetch() const { return isInstPrefetch() ||
175  isDataPrefetch(); }
176 
177  bool isInteger() const { return flags[IsInteger]; }
178  bool isFloating() const { return flags[IsFloating]; }
179  bool isVector() const { return flags[IsVector]; }
180 
181  bool isControl() const { return flags[IsControl]; }
182  bool isCall() const { return flags[IsCall]; }
183  bool isReturn() const { return flags[IsReturn]; }
184  bool isDirectCtrl() const { return flags[IsDirectControl]; }
185  bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
186  bool isCondCtrl() const { return flags[IsCondControl]; }
187  bool isUncondCtrl() const { return flags[IsUncondControl]; }
188 
189  bool isSerializing() const { return flags[IsSerializing] ||
190  flags[IsSerializeBefore] ||
191  flags[IsSerializeAfter]; }
192  bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
193  bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
194  bool isSquashAfter() const { return flags[IsSquashAfter]; }
195  bool
197  {
198  return flags[IsReadBarrier] && flags[IsWriteBarrier];
199  }
200  bool isReadBarrier() const { return flags[IsReadBarrier]; }
201  bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
202  bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
203  bool isQuiesce() const { return flags[IsQuiesce]; }
204  bool isUnverifiable() const { return flags[IsUnverifiable]; }
205  bool isSyscall() const { return flags[IsSyscall]; }
206  bool isMacroop() const { return flags[IsMacroop]; }
207  bool isMicroop() const { return flags[IsMicroop]; }
208  bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
209  bool isLastMicroop() const { return flags[IsLastMicroop]; }
210  bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
211  // hardware transactional memory
212  // HtmCmds must be identified as such in order
213  // to provide them with necessary memory ordering semantics.
214  bool isHtmStart() const { return flags[IsHtmStart]; }
215  bool isHtmStop() const { return flags[IsHtmStop]; }
216  bool isHtmCancel() const { return flags[IsHtmCancel]; }
217 
218  bool
219  isHtmCmd() const
220  {
221  return isHtmStart() || isHtmStop() || isHtmCancel();
222  }
224 
225  void setFirstMicroop() { flags[IsFirstMicroop] = true; }
226  void setLastMicroop() { flags[IsLastMicroop] = true; }
227  void setDelayedCommit() { flags[IsDelayedCommit] = true; }
228  void setFlag(Flags f) { flags[f] = true; }
229 
231  OpClass opClass() const { return _opClass; }
232 
233 
236  const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
237 
238  void
239  setDestRegIdx(int i, const RegId &val)
240  {
241  (this->*_destRegIdxPtr)[i] = val;
242  }
243 
246  const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
247 
248  void
249  setSrcRegIdx(int i, const RegId &val)
250  {
251  (this->*_srcRegIdxPtr)[i] = val;
252  }
253 
256 
257  virtual uint64_t getEMI() const { return 0; }
258 
259  protected:
260 
267  void
269  {
270  _srcRegIdxPtr = src;
271  _destRegIdxPtr = dest;
272  }
273 
280  const char *mnemonic;
281 
286  mutable std::unique_ptr<std::string> cachedDisassembly;
287 
291  virtual std::string generateDisassembly(
292  Addr pc, const loader::SymbolTable *symtab) const = 0;
293 
299  StaticInst(const char *_mnemonic, OpClass op_class)
300  : _opClass(op_class), mnemonic(_mnemonic)
301  {}
302 
303  public:
304  virtual ~StaticInst() {};
305 
306  virtual Fault execute(ExecContext *xc,
307  Trace::InstRecord *traceData) const = 0;
308 
309  virtual Fault
311  {
312  panic("initiateAcc not defined!");
313  }
314 
315  virtual Fault
317  Trace::InstRecord *trace_data) const
318  {
319  panic("completeAcc not defined!");
320  }
321 
322  virtual void advancePC(PCStateBase &pc_state) const = 0;
323  virtual void advancePC(ThreadContext *tc) const;
324 
325  virtual std::unique_ptr<PCStateBase>
326  buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const
327  {
328  panic("buildRetPC not defined!");
329  }
330 
335  virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
336 
342  virtual std::unique_ptr<PCStateBase> branchTarget(
343  const PCStateBase &pc) const;
344 
352  virtual std::unique_ptr<PCStateBase> branchTarget(
353  ThreadContext *tc) const;
354 
362  virtual const std::string &disassemble(Addr pc,
363  const loader::SymbolTable *symtab=nullptr) const;
364 
369  void printFlags(std::ostream &outs, const std::string &separator) const;
370 
372  std::string getName() { return mnemonic; }
373 
374  protected:
375  template<typename T>
376  size_t
377  simpleAsBytes(void *buf, size_t max_size, const T &t)
378  {
379  size_t size = sizeof(T);
380  if (size <= max_size)
381  *reinterpret_cast<T *>(buf) = htole<T>(t);
382  return size;
383  }
384 
385  public:
397  virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
398 };
399 
400 } // namespace gem5
401 
402 #endif // __CPU_STATIC_INST_HH__
refcnt.hh
gem5::StaticInst::isMicroop
bool isMicroop() const
Definition: static_inst.hh:207
gem5::StaticInst::isWriteBarrier
bool isWriteBarrier() const
Definition: static_inst.hh:201
gem5::StaticInst::isSerializeBefore
bool isSerializeBefore() const
Definition: static_inst.hh:192
op_class.hh
gem5::StaticInst::isNonSpeculative
bool isNonSpeculative() const
Definition: static_inst.hh:202
gem5::StaticInst::isQuiesce
bool isQuiesce() const
Definition: static_inst.hh:203
gem5::StaticInst::numCCDestRegs
int8_t numCCDestRegs() const
Number of coprocesor destination regs.
Definition: static_inst.hh:152
gem5::StaticInst::isIndirectCtrl
bool isIndirectCtrl() const
Definition: static_inst.hh:185
gem5::StaticInst::isUnverifiable
bool isUnverifiable() const
Definition: static_inst.hh:204
gem5::StaticInst::isNop
bool isNop() const
Definition: static_inst.hh:161
gem5::StaticInst::buildRetPC
virtual std::unique_ptr< PCStateBase > buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const
Definition: static_inst.hh:326
gem5::StaticInst::RegIdArrayPtr
RegId(StaticInst::*)[] RegIdArrayPtr
Definition: static_inst.hh:90
gem5::StaticInst::asBytes
virtual size_t asBytes(void *buf, size_t max_size)
Instruction classes can override this function to return a a representation of themselves as a blob o...
Definition: static_inst.hh:397
gem5::StaticInst::isSerializeAfter
bool isSerializeAfter() const
Definition: static_inst.hh:193
gem5::StaticInst::~StaticInst
virtual ~StaticInst()
Definition: static_inst.hh:304
gem5::StaticInst::setSrcRegIdx
void setSrcRegIdx(int i, const RegId &val)
Definition: static_inst.hh:249
gem5::StaticInst::isControl
bool isControl() const
Definition: static_inst.hh:181
gem5::StaticInst::_numFPDestRegs
int8_t _numFPDestRegs
The following are used to track physical register usage for machines with separate int & FP reg files...
Definition: static_inst.hh:116
gem5::ArmISA::f
Bitfield< 6 > f
Definition: misc_types.hh:68
gem5::StaticInst::_numIntDestRegs
int8_t _numIntDestRegs
Definition: static_inst.hh:117
gem5::StaticInst::simpleAsBytes
size_t simpleAsBytes(void *buf, size_t max_size, const T &t)
Definition: static_inst.hh:377
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::StaticInst::isCondCtrl
bool isCondCtrl() const
Definition: static_inst.hh:186
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::StaticInst
StaticInst(const char *_mnemonic, OpClass op_class)
Constructor.
Definition: static_inst.hh:299
gem5::StaticInst::numSrcRegs
int8_t numSrcRegs() const
Number of source registers.
Definition: static_inst.hh:138
gem5::StaticInst::isDelayedCommit
bool isDelayedCommit() const
Definition: static_inst.hh:208
gem5::StaticInst::numVecDestRegs
int8_t numVecDestRegs() const
Number of vector destination regs.
Definition: static_inst.hh:146
gem5::StaticInst::setDestRegIdx
void setDestRegIdx(int i, const RegId &val)
Definition: static_inst.hh:239
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::StaticInst::isFirstMicroop
bool isFirstMicroop() const
Definition: static_inst.hh:210
gem5::StaticInst::_numCCDestRegs
int8_t _numCCDestRegs
Definition: static_inst.hh:118
gem5::StaticInst::advancePC
virtual void advancePC(PCStateBase &pc_state) const =0
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:236
gem5::StaticInst::_opClass
OpClass _opClass
See opClass().
Definition: static_inst.hh:105
gem5::StaticInst::execute
virtual Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const =0
gem5::RefCountingPtr< StaticInst >
gem5::StaticInst::numVecPredDestRegs
int8_t numVecPredDestRegs() const
Number of predicate destination regs.
Definition: static_inst.hh:150
gem5::StaticInst::fetchMicroop
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
Definition: static_inst.cc:39
gem5::StaticInst::numVecElemDestRegs
int8_t numVecElemDestRegs() const
Number of vector element destination regs.
Definition: static_inst.hh:148
gem5::StaticInst::numFPDestRegs
int8_t numFPDestRegs() const
Number of floating-point destination regs.
Definition: static_inst.hh:142
gem5::StaticInst::opClass
OpClass opClass() const
Operation class. Used to select appropriate function unit in issue.
Definition: static_inst.hh:231
gem5::StaticInst::isHtmCancel
bool isHtmCancel() const
Definition: static_inst.hh:216
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::StaticInst::isFloating
bool isFloating() const
Definition: static_inst.hh:178
gem5::StaticInst::isHtmCmd
bool isHtmCmd() const
Definition: static_inst.hh:219
gem5::Flags
Wrapper that groups a few flag bits under the same undelying container.
Definition: flags.hh:44
gem5::StaticInst::isReturn
bool isReturn() const
Definition: static_inst.hh:183
gem5::StaticInst::isHtmStart
bool isHtmStart() const
Definition: static_inst.hh:214
gem5::StaticInst::isDataPrefetch
bool isDataPrefetch() const
Definition: static_inst.hh:173
gem5::StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:87
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::StaticInst::isPrefetch
bool isPrefetch() const
Definition: static_inst.hh:174
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:246
gem5::StaticInst::isAtomic
bool isAtomic() const
Definition: static_inst.hh:170
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::StaticInst::isHtmStop
bool isHtmStop() const
Definition: static_inst.hh:215
gem5::StaticInst::_numVecElemDestRegs
int8_t _numVecElemDestRegs
Definition: static_inst.hh:124
gem5::StaticInst::getName
std::string getName()
Return name of machine instruction.
Definition: static_inst.hh:372
gem5::StaticInst::isLoad
bool isLoad() const
Definition: static_inst.hh:168
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:102
gem5::StaticInst::isStore
bool isStore() const
Definition: static_inst.hh:169
gem5::StaticInst::_destRegIdxPtr
RegIdArrayPtr _destRegIdxPtr
See destRegIdx().
Definition: static_inst.hh:97
gem5::StaticInst::isDirectCtrl
bool isDirectCtrl() const
Definition: static_inst.hh:184
gem5::StaticInst::isVector
bool isVector() const
Definition: static_inst.hh:179
gem5::StaticInst::_srcRegIdxPtr
RegIdArrayPtr _srcRegIdxPtr
See srcRegIdx().
Definition: static_inst.hh:94
gem5::StaticInst::generateDisassembly
virtual std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const =0
Internal function to generate disassembly string.
gem5::StaticInst::setRegIdxArrays
void setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
Set the pointers which point to the arrays of source and destination register indices.
Definition: static_inst.hh:268
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
gem5::StaticInst::numIntDestRegs
int8_t numIntDestRegs() const
Number of integer destination regs.
Definition: static_inst.hh:144
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::StaticInst::isLastMicroop
bool isLastMicroop() const
Definition: static_inst.hh:209
gem5::StaticInst::setLastMicroop
void setLastMicroop()
Definition: static_inst.hh:226
gem5::StaticInst::isMemRef
bool isMemRef() const
Definition: static_inst.hh:164
gem5::StaticInst::setDelayedCommit
void setDelayedCommit()
Definition: static_inst.hh:227
pcstate.hh
gem5::StaticInst::isReadBarrier
bool isReadBarrier() const
Definition: static_inst.hh:200
gem5::RefCounted
Derive from RefCounted if you want to enable reference counting of this class.
Definition: refcnt.hh:60
gem5::StaticInst::getEMI
virtual uint64_t getEMI() const
Definition: static_inst.hh:257
gem5::StaticInst::isInstPrefetch
bool isInstPrefetch() const
Definition: static_inst.hh:172
gem5::StaticInst::completeAcc
virtual Fault completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) const
Definition: static_inst.hh:316
gem5::StaticInst::nullStaticInstPtr
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
Definition: static_inst.hh:255
gem5::StaticInst::disassemble
virtual const std::string & disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const
Return string representation of disassembled instruction.
Definition: static_inst.cc:60
gem5::StaticInst::initiateAcc
virtual Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
Definition: static_inst.hh:310
gem5::StaticInst::setFirstMicroop
void setFirstMicroop()
Definition: static_inst.hh:225
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:111
gem5::StaticInst::isMacroop
bool isMacroop() const
Definition: static_inst.hh:206
static_inst_fwd.hh
gem5::StaticInst::isSquashAfter
bool isSquashAfter() const
Definition: static_inst.hh:194
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
reg_class.hh
gem5::StaticInst::cachedDisassembly
std::unique_ptr< std::string > cachedDisassembly
String representation of disassembly (lazily evaluated via disassemble()).
Definition: static_inst.hh:286
gem5::StaticInst::isSerializing
bool isSerializing() const
Definition: static_inst.hh:189
gem5::StaticInst::numDestRegs
int8_t numDestRegs() const
Number of destination registers.
Definition: static_inst.hh:140
logging.hh
gem5::StaticInst::isInteger
bool isInteger() const
Definition: static_inst.hh:177
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::StaticInst::isCall
bool isCall() const
Definition: static_inst.hh:182
gem5::StaticInst::branchTarget
virtual std::unique_ptr< PCStateBase > branchTarget(const PCStateBase &pc) const
Return the target address for a PC-relative branch.
Definition: static_inst.cc:46
gem5::StaticInst::isFullMemBarrier
bool isFullMemBarrier() const
Definition: static_inst.hh:196
gem5::StaticInst::isUncondCtrl
bool isUncondCtrl() const
Definition: static_inst.hh:187
gem5::Trace::InstRecord
Definition: insttracer.hh:61
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::StaticInst::isSyscall
bool isSyscall() const
Definition: static_inst.hh:205
gem5::StaticInst::isStoreConditional
bool isStoreConditional() const
Definition: static_inst.hh:171
gem5::StaticInst::setFlag
void setFlag(Flags f)
Definition: static_inst.hh:228
gem5::StaticInst::_numVecPredDestRegs
int8_t _numVecPredDestRegs
Definition: static_inst.hh:125
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:108
gem5::StaticInst::printFlags
void printFlags(std::ostream &outs, const std::string &separator) const
Print a separator separated list of this instruction's set flag names on the given stream.
Definition: static_inst.cc:71
gem5::StaticInst::_numVecDestRegs
int8_t _numVecDestRegs
To use in architectures with vector register file.
Definition: static_inst.hh:123
byteswap.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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