gem5  v22.1.0.0
x86_traits.hh
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37 
38 #ifndef __ARCH_X86_X86TRAITS_HH__
39 #define __ARCH_X86_X86TRAITS_HH__
40 
41 #include <cassert>
42 
43 #include "base/types.hh"
44 
45 namespace gem5
46 {
47 
48 namespace X86ISA
49 {
50  const int NumMicroIntRegs = 16;
51 
52  const int NumMMXRegs = 8;
53  const int NumXMMRegs = 16;
54  const int NumMicroFpRegs = 8;
55 
56  const int NumCRegs = 16;
57  const int NumDRegs = 8;
58 
59  const int NumSegments = 6;
60  const int NumSysSegments = 4;
61 
62  const Addr IntAddrPrefixMask = 0xffffffff00000000ULL;
63  const Addr IntAddrPrefixCPUID = 0x100000000ULL;
64  const Addr IntAddrPrefixMSR = 0x200000000ULL;
65  const Addr IntAddrPrefixIO = 0x300000000ULL;
66 
67  const Addr PhysAddrPrefixIO = 0x8000000000000000ULL;
68  const Addr PhysAddrPrefixPciConfig = 0xC000000000000000ULL;
69  const Addr PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL;
70  const Addr PhysAddrPrefixInterrupts = 0xA000000000000000ULL;
71  // Each APIC gets two pages. One page is used for local apics to field
72  // accesses from the CPU, and the other is for all APICs to communicate.
73  const Addr PhysAddrAPICRangeSize = 1 << 12;
74 
75  // Put this in an unused part of the 16 bit IO port address space.
76  const Addr PhysAddrIntA = 0x8000000100000000ULL;
77 
78  static inline Addr
79  x86IOAddress(const uint32_t port)
80  {
81  return PhysAddrPrefixIO | port;
82  }
83 
84  static inline Addr
85  x86PciConfigAddress(const uint32_t addr)
86  {
88  }
89 
90  static inline Addr
91  x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
92  {
93  assert(addr < (1 << 12));
94  return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr;
95  }
96 
97  static inline Addr
98  x86InterruptAddress(const uint8_t id, const uint16_t addr)
99  {
100  assert(addr < PhysAddrAPICRangeSize);
102  }
103 
104 } // namespace X86ISA
105 } // namespace gem5
106 
107 #endif //__ARCH_X86_X86TRAITS_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
const Addr PhysAddrPrefixInterrupts
Definition: x86_traits.hh:70
const Addr PhysAddrPrefixPciConfig
Definition: x86_traits.hh:68
const int NumCRegs
Definition: x86_traits.hh:56
const Addr IntAddrPrefixIO
Definition: x86_traits.hh:65
const int NumXMMRegs
Definition: x86_traits.hh:53
const Addr PhysAddrAPICRangeSize
Definition: x86_traits.hh:73
Bitfield< 3 > addr
Definition: types.hh:84
static Addr x86IOAddress(const uint32_t port)
Definition: x86_traits.hh:79
const int NumSegments
Definition: x86_traits.hh:59
const int NumMicroIntRegs
Definition: x86_traits.hh:50
const Addr PhysAddrPrefixIO
Definition: x86_traits.hh:67
const Addr IntAddrPrefixCPUID
Definition: x86_traits.hh:63
const Addr IntAddrPrefixMSR
Definition: x86_traits.hh:64
const int NumDRegs
Definition: x86_traits.hh:57
const Addr IntAddrPrefixMask
Definition: x86_traits.hh:62
const Addr PhysAddrIntA
Definition: x86_traits.hh:76
const int NumMMXRegs
Definition: x86_traits.hh:52
const int NumMicroFpRegs
Definition: x86_traits.hh:54
const Addr PhysAddrPrefixLocalAPIC
Definition: x86_traits.hh:69
static Addr x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
Definition: x86_traits.hh:91
const int NumSysSegments
Definition: x86_traits.hh:60
static Addr x86PciConfigAddress(const uint32_t addr)
Definition: x86_traits.hh:85
static Addr x86InterruptAddress(const uint8_t id, const uint16_t addr)
Definition: x86_traits.hh:98
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

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