gem5  v21.1.0.2
x86_traits.hh
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37 
38 #ifndef __ARCH_X86_X86TRAITS_HH__
39 #define __ARCH_X86_X86TRAITS_HH__
40 
41 #include <cassert>
42 
43 #include "base/types.hh"
44 
45 namespace gem5
46 {
47 
48 namespace X86ISA
49 {
50  const int NumMicroIntRegs = 16;
51 
52  const int NumMMXRegs = 8;
53  const int NumXMMRegs = 16;
54  const int NumMicroFpRegs = 8;
55 
56  const int NumCRegs = 16;
57  const int NumDRegs = 8;
58 
59  const int NumSegments = 6;
60  const int NumSysSegments = 4;
61 
62  const Addr IntAddrPrefixMask = 0xffffffff00000000ULL;
63  const Addr IntAddrPrefixCPUID = 0x100000000ULL;
64  const Addr IntAddrPrefixMSR = 0x200000000ULL;
65  const Addr IntAddrPrefixIO = 0x300000000ULL;
66 
67  const Addr PhysAddrPrefixIO = 0x8000000000000000ULL;
68  const Addr PhysAddrPrefixPciConfig = 0xC000000000000000ULL;
69  const Addr PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL;
70  const Addr PhysAddrPrefixInterrupts = 0xA000000000000000ULL;
71  // Each APIC gets two pages. One page is used for local apics to field
72  // accesses from the CPU, and the other is for all APICs to communicate.
73  const Addr PhysAddrAPICRangeSize = 1 << 12;
74 
75  static inline Addr
76  x86IOAddress(const uint32_t port)
77  {
78  return PhysAddrPrefixIO | port;
79  }
80 
81  static inline Addr
82  x86PciConfigAddress(const uint32_t addr)
83  {
85  }
86 
87  static inline Addr
88  x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
89  {
90  assert(addr < (1 << 12));
91  return PhysAddrPrefixLocalAPIC | (id * (1 << 12)) | addr;
92  }
93 
94  static inline Addr
95  x86InterruptAddress(const uint8_t id, const uint16_t addr)
96  {
97  assert(addr < PhysAddrAPICRangeSize);
99  }
100 
101 } // namespace X86ISA
102 } // namespace gem5
103 
104 #endif //__ARCH_X86_X86TRAITS_HH__
gem5::X86ISA::x86LocalAPICAddress
static Addr x86LocalAPICAddress(const uint8_t id, const uint16_t addr)
Definition: x86_traits.hh:88
gem5::X86ISA::IntAddrPrefixMSR
const Addr IntAddrPrefixMSR
Definition: x86_traits.hh:64
gem5::X86ISA::NumSegments
const int NumSegments
Definition: x86_traits.hh:59
gem5::X86ISA::NumDRegs
const int NumDRegs
Definition: x86_traits.hh:57
gem5::X86ISA::x86PciConfigAddress
static Addr x86PciConfigAddress(const uint32_t addr)
Definition: x86_traits.hh:82
gem5::X86ISA::PhysAddrPrefixInterrupts
const Addr PhysAddrPrefixInterrupts
Definition: x86_traits.hh:70
gem5::X86ISA::NumSysSegments
const int NumSysSegments
Definition: x86_traits.hh:60
gem5::X86ISA::NumCRegs
const int NumCRegs
Definition: x86_traits.hh:56
gem5::X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:53
gem5::X86ISA::IntAddrPrefixMask
const Addr IntAddrPrefixMask
Definition: x86_traits.hh:62
gem5::X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:52
gem5::X86ISA::IntAddrPrefixCPUID
const Addr IntAddrPrefixCPUID
Definition: x86_traits.hh:63
gem5::X86ISA::PhysAddrPrefixPciConfig
const Addr PhysAddrPrefixPciConfig
Definition: x86_traits.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::PhysAddrAPICRangeSize
const Addr PhysAddrAPICRangeSize
Definition: x86_traits.hh:73
gem5::X86ISA::x86InterruptAddress
static Addr x86InterruptAddress(const uint8_t id, const uint16_t addr)
Definition: x86_traits.hh:95
types.hh
gem5::X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:50
gem5::X86ISA::IntAddrPrefixIO
const Addr IntAddrPrefixIO
Definition: x86_traits.hh:65
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::PhysAddrPrefixLocalAPIC
const Addr PhysAddrPrefixLocalAPIC
Definition: x86_traits.hh:69
gem5::X86ISA::x86IOAddress
static Addr x86IOAddress(const uint32_t port)
Definition: x86_traits.hh:76
gem5::X86ISA::PhysAddrPrefixIO
const Addr PhysAddrPrefixIO
Definition: x86_traits.hh:67
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:54

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