- c -

• Cache() : Cache
• cacheAvail() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheBlk() : CacheBlk
• CacheBlkPrintWrapper() : CacheBlkPrintWrapper
• cacheBlocked() : LSQ< Impl >
• cacheBlockSize() : DmaDevice
• CacheCmdStats() : BaseCache::CacheCmdStats
• cacheLineSize() : BaseCPU , ComputeUnit , LSQUnit< Impl > , System
• CacheMasterPort() : BaseCache::CacheMasterPort
• CacheMemory() : CacheMemory
• cachePortAvailable() : LSQ< Impl >
• cachePortBusy() : LSQ< Impl >
• cacheProbe() : CacheMemory , PerfectCacheMemory< ENTRY >
• CacheRecorder() : CacheRecorder
• CacheReqPacketQueue() : BaseCache::CacheReqPacketQueue
• cacheResponding() : Packet
• CacheSlavePort() : BaseCache::CacheSlavePort
• CacheStats() : BaseCache::CacheStats
• CacheTracking() : FALRU::CacheTracking
• cacheUnblocked() : DefaultIEW< Impl > , InstructionQueue< Impl >
• calc_indices() : sc_dt::scfx_rep
• calcAddr() : HsailISA::Call
• calcConf() : LoopPredictor , MPP_LoopPredictor , TAGE_SC_L_LoopPredictor
• calcDep() : TAGE_SC_L_TAGE
• calcFreeIQEntries() : DefaultRename< Impl >
• calcFreeLQEntries() : DefaultRename< Impl >
• calcFreeROBEntries() : DefaultRename< Impl >
• calcFreeSQEntries() : DefaultRename< Impl >
• calcIndex() : StoreSet
• calcLane() : AddrOperandBase , NoRegAddrOperand , RegAddrOperand< RegOperandType >
• calcLocHistIdx() : TournamentBP
• calcPacketTiming() : BaseXBar
• calcPciConfigAddr() : Malta , T1000
• calcPciIOAddr() : Malta , T1000
• calcPciMemAddr() : Malta , T1000
• calcReceiveTick() : DistIface::RecvScheduler
• calcResolution() : BaseKvmTimer , PerfKvmTimer , PosixKvmTimer
• calcSaturation() : SatCounter
• calcSSID() : StoreSet
• calcStackDist() : StackDistCalc
• calcStackDistAndUpdate() : StackDistCalc
• calcTickShift() : ArmSemihosting
• calculateAccessLatency() : BaseCache
• calculateIndicesAndTags() : TAGE_SC_L_TAGE , TAGEBase
• calculateLookaheadConfidence() : SignaturePathPrefetcher , SignaturePathPrefetcherV2
• calculateParameters() : MPP_TAGE , TAGE_SC_L_TAGE , TAGEBase
• calculatePrefetch() : AccessMapPatternMatching , AMPMPrefetcher , BOPPrefetcher , DCPTPrefetcher , DeltaCorrelatingPredictionTables , IndirectMemoryPrefetcher , IrregularStreamBufferPrefetcher , PIFPrefetcher , QueuedPrefetcher , SBOOEPrefetcher , SignaturePathPrefetcher , SlimAMPMPrefetcher , STeMSPrefetcher , StridePrefetcher , TaggedPrefetcher
• calculatePrefetchConfidence() : SignaturePathPrefetcher , SignaturePathPrefetcherV2
• calculateTagOnlyLatency() : BaseCache
• calculateVC() : NetworkInterface
• calculateVectorIndex() : TimeBuffer< T >
• calcUniform() : NoRegAddrOperand , RegAddrOperand< RegOperandType >
• calcUniformBase() : AddrOperandBase
• calcVector() : AddrOperandBase , NoRegAddrOperand , RegAddrOperand< RegOperandType >
• Call() : HsailISA::Call
• call() : Iris::ThreadContext , m5::Coroutine< Arg, Ret > , sc_gem5::ProcessFuncWrapper , sc_gem5::ProcessMemberFuncWrapper< T > , sc_gem5::ProcessObjFuncWrapper< T > , sc_gem5::ProcessObjRetFuncWrapper< T, R >
• call32() : ArmSemihosting
• call64() : ArmSemihosting
• CallArgMem() : CallArgMem
• Callback() : MemBackdoor::Callback
• callback_binder_bw() : tlm_utils::callback_binder_bw< TYPES >
• callback_binder_fw() : tlm_utils::callback_binder_fw< TYPES >
• called() : sc_gem5::ScMainFiber
• CallerType() : m5::Coroutine< Arg, Ret >::CallerType
• callpal() : AlphaISA::Kernel::Statistics
• callSemihosting32() : ArmSystem
• callSemihosting64() : ArmSystem
• canAccept() : DRAMSim2Wrapper
• canAllocate() : PoolManager , SimplePoolManager
• canBeSelectedFor1toNInterrupt() : Gicv3Redistributor
• cancel() : DmaReadFifo::DmaDoneEvent , sc_core::sc_event , sc_gem5::Event
• cancel_all() : sc_core::sc_event_queue , sc_core::sc_event_queue_if , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES > , tlm_utils::peq_with_get< PAYLOAD >
• canceled() : DmaReadFifo::DmaDoneEvent
• cancelTimeout() : sc_gem5::Process
• canCoalesce() : TLBCoalescer
• canCoAllocate() : SuperBlk
• canCommit() : ROB< Impl >
• canForwardDataToLoad() : Minor::LSQ::StoreBuffer
• canInsert() : Minor::FUPipeline , Minor::LSQ::StoreBuffer
• canInstIssue() : Minor::Scoreboard
• canPrefetch() : MSHRQueue
• canPushIntoStoreBuffer() : Minor::LSQ
• canRename() : UnifiedRenameMap
• canRequest() : Minor::LSQ
• canReserve() : LdsState , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable
• canSendToMemorySystem() : Minor::LSQ
• canWB() : LSQUnit< Impl >::SQEntry
• capabilities() : FuncUnit
• capacity() : CircularQueue< T > , Fifo< T >
• capCoalescedMMIO() : Kvm
• capDebugRegs() : Kvm
• capExtendedCPUID() : Kvm
• capIRQChip() : Kvm
• capNumMemSlots() : Kvm
• capOneReg() : Kvm
• capSetTSSAddress() : Kvm
• captureFrameBuffer() : VncInput
• capUserMemory() : Kvm
• capUserNMI() : Kvm
• capVCPUEvents() : Kvm
• capXCRs() : Kvm
• capXSave() : Kvm
• cast() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_rep
• cast_switch() : sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::scfx_params
• category() : sc_gem5::DynamicSensitivity , sc_gem5::Sensitivity , sc_gem5::StaticSensitivity
• cbegin() : sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , SimpleRenameMap
• CbrDirectInst() : HsailISA::CbrDirectInst
• CbrIndirectInst() : HsailISA::CbrIndirectInst
• CbrInstBase() : HsailISA::CbrInstBase< TargetType >
• cc() : Net::TcpOpt
• cedeSIMD() : ComputeUnit
• cend() : sc_core::sc_vector< T > , sc_core::sc_vector_assembly< T, MT > , SimpleRenameMap
• chainRead() : VirtDescriptor
• chainSize() : VirtDescriptor
• chainWrite() : VirtDescriptor
• changeAddress() : Check
• changeConfig() : Sinic::Device
• changeDirectionPrediction() : IndirectPredictor , SimpleIndirectPredictor
• changedROBEntries() : DefaultCommit< Impl >
• changeMode() : AlphaISA::Kernel::Statistics
• changePermission() : AbstractCacheEntry , PerfectCacheMemory< ENTRY >
• changeStamp() : sc_gem5::Scheduler
• changeStream() : Minor::Fetch1
• Channel() : PixelConverter::Channel , sc_gem5::Channel
• ChannelAddr() : ChannelAddr
• ChannelAddrRange() : ChannelAddrRange
• channelRead() : CopyEngine::CopyEngineChannel
• channelWrite() : CopyEngine::CopyEngineChannel
• Check() : Check
• check() : FALRU::CacheTracking , PacketFifo , sc_gem5::TraceVal< T, Base > , sc_gem5::TraceVal<::sc_core::sc_event, Base > , sc_gem5::TraceVal<::sc_core::sc_signal_in_if< T >, Base > , sc_gem5::TraceValBase , sc_gem5::TraceValFxnumBase< T, Base > , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , Stats::VectorBase< Derived, Stor > , Stats::VectorDistBase< Derived, Stor > , Trace::ArmNativeTrace , Trace::NativeTrace , Trace::SparcNativeTrace , Trace::X86NativeTrace
• check_bounds() : sc_dt::sc_proxy< X > , sc_dt::sc_subref_r< X >
• check_export_binding() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL >
• check_for_wakeup() : SwitchAllocator
• check_if_outside() : sc_dt::sc_signed , sc_dt::sc_unsigned
• check_index() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• check_length() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• check_range() : sc_dt::sc_int_base , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• check_value() : sc_dt::sc_int_base , sc_dt::sc_uint_base
• check_wbounds() : sc_dt::sc_proxy< X >
• check_writer() : sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > >
• checkAccessMatchOnActiveEntries() : IndirectMemoryPrefetcher
• checkAddrSizeFaultAArch64() : ArmISA::TableWalker
• checkAdvSIMDOrFPEnabled32() : ArmISA::ArmStaticInst
• checkAndIssue() : TraceCPU::ElasticDataGen
• checkAndSchedExitEvent() : TraceCPU
• checkBpLen() : BaseRemoteGDB , RiscvISA::RemoteGDB , X86ISA::RemoteGDB
• checkCacheability() : AlphaISA::TLB , MipsISA::TLB , PowerISA::TLB , RiscvISA::TLB
• checkCandidate() : AccessMapPatternMatching
• checkClear() : StoreSet
• checkCoherence() : GPUCoalescer , Sequencer
• checkCommandQueue() : Gicv3Its
• checkCondition() : X86ISA::X86MicroopBase
• checkConflict() : PacketQueue
• checkConflictingSnoop() : BaseCache::CacheReqPacketQueue
• checkDrain() : FlashDevice , IGbE , UFSHostDevice
• checkDrainDone() : DRAMCtrl::Rank
• checkEL1Trap() : MiscRegOp64
• checkEL2Trap() : MiscRegOp64
• checkEL3Trap() : MiscRegOp64
• checkELMatch() : ArmISA::TlbEntry
• Checker() : Checker< Impl >
• CheckerCPU() : CheckerCPU
• CheckerThreadContext() : CheckerThreadContext< TC >
• checkExpected() : SwitchingFiber
• checkExtension() : Kvm
• checkFlags() : CheckerCPU
• checkForActiveGenerationsEnd() : STeMSPrefetcher
• checkForDeadlock() : RubyDirectedTester , RubyTester
• checkForInterrupts() : BaseSimpleCPU
• checkForStdio() : OutputDirectory
• checkForWFxTrap32() : ArmISA::ArmStaticInst
• checkForWFxTrap64() : ArmISA::ArmStaticInst
• checkFPAdvSIMDEnabled64() : ArmISA::ArmStaticInst
• checkFPAdvSIMDTrap64() : ArmISA::ArmStaticInst
• checkIndex() : sc_core::sc_vector_base
• checkInst() : StoreSet
• checkInterrupt() : DefaultFetch< Impl > , RiscvISA::Interrupts
• checkInterrupts() : AlphaISA::Interrupts , ArmISA::Interrupts , BaseCPU , BaseInterrupts , Minor::Execute , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• checkInterruptsRaw() : X86ISA::Interrupts
• checkLimit() : sc_gem5::ReportSevInfo
• checkLimits() : sc_gem5::ReportMsgInfo
• checkLockedAddrList() : AbstractMemory
• checkMask() : WaiterState
• checkMisprediction() : DefaultIEW< Impl >
• checkName() : Label
• checkNetworkAllocation() : Network
• checkPAN() : ArmISA::TLB
• checkPathRedirect() : Process
• checkPcEventQueue() : BaseSimpleCPU
• checkPermissions() : ArmISA::TLB
• checkPermissions64() : ArmISA::TLB
• CheckpointIn() : CheckpointIn
• checkpointReschedule() : EventQueue
• checkPort() : sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS > , sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
• checkProtocolVersion() : VncServer
• checkR11Reg() : Trace::X86NativeTrace
• checkRaw() : ArmISA::Interrupts
• checkRcxReg() : Trace::X86NativeTrace
• checkReg() : Trace::NativeTrace
• checkReschedule() : NetworkInterface
• checkResourceAvailable() : CacheMemory
• checkSanity() : SimpleAddressMap
• checkSecurity() : VncServer
• checkSETENDEnabled() : ArmISA::ArmStaticInst
• checkSignalsAndUpdate() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkSnoop() : LSQUnit< Impl >
• checkSoftInt() : SparcISA::ISA
• checkStall() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• checkStallQueue() : NetworkInterface
• checkSveEnabled() : ArmISA::ArmStaticInst
• checkSveTrap() : ArmISA::ArmStaticInst
• CheckTable() : CheckTable
• checkTransaction() : sc_gem5::TlmToGem5Bridge< BITWIDTH >
• checkViolations() : LSQUnit< Impl >
• checkWfiWake() : ArmISA::Interrupts
• checkWrite() : CacheBlk
• checkWriter() : sc_gem5::WriteChecker< sc_core::SC_MANY_WRITERS > , sc_gem5::WriteChecker< sc_core::SC_ONE_WRITER >
• checkXMM() : Trace::X86NativeTrace
• chkInterrupt() : IGbE
• choose() : ArmISA::Crypto
• chooseNext() : DRAMCtrl
• chooseNextFRFCFS() : DRAMCtrl
• chooseWave() : __SchedulingPolicy< Policy > , Scheduler , SchedulingPolicy
• chunkComplete() : DmaCallback
• ChunkGenerator() : ChunkGenerator
• CircleBuf() : CircleBuf< T >
• circular_buffer() : tlm::circular_buffer< T >
• CircularQueue() : CircularQueue< T >
• cksum() : Net::TcpOpt
• claim() : SimpleATInitiator1::SimplePool , SimpleATInitiator2::SimplePool
• ClassInst() : HsailISA::ClassInst< DataType >
• className() : RegId
• classValue() : RegId
• ClDriver() : ClDriver
• clean_tail() : sc_dt::sc_bitref< X > , sc_dt::sc_bv_base , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_lv_base , sc_dt::sc_subref_r< X >
• cleanEvictBlk() : Cache
• cleanup() : ListenSocket , X86ISA::GpuTLB
• cleanupRefs() : BaseTags
• cleanupRefsVisitor() : BaseTags
• cleanUpRemovedInsts() : FullO3CPU< Impl >
• clear() : AddrRangeMap< V, max_cache_size > , AlphaISA::Interrupts , AlphaISA::ISA , AlphaISA::StackTrace , ArmInterruptPin , ArmISA::Interrupts , ArmISA::ISA , ArmISA::StackTrace , ArmPPI , ArmSPI , BaseInterrupts , BloomFilter::Base , BloomFilter::Multi , BloomFilter::Perfect , CallbackQueue , Compressed , cp::Format , DataBlock , EtherSwitch::Interface::PortFifo , Flags< T > , FrameBuffer , FunctionProfile , Histogram , IntrControl , ItsCommand , LSQUnit< Impl >::LSQEntry , LSQUnit< Impl >::SQEntry , MessageBuffer , MipsISA::Interrupts , MipsISA::ISA , MipsISA::StackTrace , NetDest , PacketFifo , PacketFifoEntry , PowerISA::Interrupts , PowerISA::ISA , PowerISA::StackTrace , ProfileNode , RiscvISA::Interrupts , RiscvISA::ISA , RiscvISA::StackTrace , sc_core::sc_vector< T > , sc_dt::sc_signed , sc_dt::sc_unsigned , sc_dt::scfx_mant , sc_dt::scfx_rep , sc_dt::scfx_string , sc_gem5::Scheduler , sc_gem5::Sensitivity , sc_gem5::SensitivityEvent , sc_gem5::SensitivityEvents , Set , SparcISA::Interrupts , SparcISA::ISA , SparcISA::PageTableEntry , SparcISA::TlbMap , StoreSet , SymbolTable , Time , tlm::circular_buffer< T > , TraceCPU::FixedRetryGen::TraceElement , TraceGen::TraceElement , Trie< Key, Value > , Trie< Key, Value >::Node , WriteMask , X86ISA::Interrupts , X86ISA::ISA , X86ISA::StackTrace
• clear32() : ArmISA::ISA
• clear64() : ArmISA::ISA
• clear_cached_report() : sc_core::sc_report_handler
• clear_extension() : tlm::tlm_generic_payload , tlm_utils::instance_specific_extensions_per_accessor
• clear_request_vector() : SwitchAllocator
• clearAll() : AlphaISA::Interrupts , ArmISA::Interrupts , BaseInterrupts , MipsISA::Interrupts , PowerISA::Interrupts , RiscvISA::Interrupts , SparcISA::Interrupts , X86ISA::Interrupts
• clearArchRegs() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• clearBankedDistRange() : MuxingKvmGic
• clearBlockCached() : Packet
• clearBlocked() : BaseCache::CacheSlavePort , BaseCache
• clearCanCommit() : BaseDynInst< Impl >
• clearCanIssue() : BaseDynInst< Impl >
• clearConsoleInt() : Malta , Pc , Platform , RealView , T1000 , Tsunami
• clearDistRange() : MuxingKvmGic
• clearDownstreamPending() : MSHR , MSHR::TargetList
• clearDRIR() : TsunamiCChip
• clearDynamic() : sc_gem5::Process
• clearFlags() : Event
• clearFromParent() : TimingSimpleCPU::SplitFragmentSenderState
• clearId() : Iris::ThreadContext::BpInfo
• clearInIQ() : BaseDynInst< Impl >
• clearInROB() : BaseDynInst< Impl >
• clearInst() : DependencyGraph< DynInstPtr >
• clearInstDests() : Minor::Scoreboard
• clearInt() : BaseGic , FastModel::GIC , GenericPciHost , GicV2 , Gicv3 , MuxingKvmGic , PciHost , PciHost::DeviceInterface , Sp805
• clearInterrupt() : ArmISA::PMU , BaseCPU , UFSHostDevice
• clearInterrupts() : BaseCPU , Pl011
• clearIntr() : MaltaCChip , MaltaIO
• clearIPI() : MaltaCChip , TsunamiCChip
• clearIrqCpuInterface() : Gicv3Distributor
• clearIssued() : BaseDynInst< Impl >
• clearITI() : MaltaCChip , TsunamiCChip
• clearLoadLocks() : CacheBlk
• clearLocked() : AbstractCacheEntry , CacheMemory
• clearMemBarrier() : Minor::LSQ
• clearNonunitEntry() : Prefetcher
• clearParent() : sc_gem5::Event
• clearPciInt() : Malta , Pc , Platform , RealView , T1000 , Tsunami
• clearPIC() : TsunamiIO
• clearPPI() : KvmKernelGicV2
• clearPPInt() : BaseGic , FastModel::GIC , GicV2 , Gicv3 , MuxingKvmGic
• clearReadSignal() : UFSHostDevice::UFSSCSIDevice
• clearRegArrayBit() : X86ISA::Interrupts
• clearRegDep() : TraceCPU::ElasticDataGen::GraphNode
• clearReservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• clearRobDep() : TraceCPU::ElasticDataGen::GraphNode
• clearSerializeAfter() : BaseDynInst< Impl >
• clearSerializeBefore() : BaseDynInst< Impl >
• clearSignal() : UFSHostDevice::UFSSCSIDevice
• clearSingleStep() : BaseRemoteGDB
• clearSPI() : KvmKernelGicV2
• clearStates() : DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl >
• clearStats() : AddressProfiler , MessageBuffer , PerfectSwitch , RubyDirectedTester , RubyTester , Throttle
• clearSummary() : StoreTrace
• clearTempBreakpoint() : BaseRemoteGDB
• clearTempStoreUntil() : ElasticTrace
• clearUnknownPages() : FlashDevice
• clearUsedBits() : SparcISA::TLB
• clearWriteThrough() : Packet
• clkPeriodAtPerfLevel() : DVFSHandler , SrcClockDomain
• clockChangeHandler() : FastModel::ScxEvsCortexA76< Types >
• ClockDomain() : ClockDomain
• ClockDomainStats() : ClockDomain::ClockDomainStats
• Clocked() : Clocked
• clockEdge() : Clocked
• ClockedObject() : ClockedObject
• ClockedObjectStats() : ClockedObject::ClockedObjectStats
• clockPeriod() : ClockDomain , Clocked , DRAMSim2Wrapper , RealViewOsc , SrcClockDomain , X86ISA::Interrupts
• clockPeriodUpdated() : Clocked , FastModel::CortexA76 , Iris::BaseCPU
• ClockRateControlInitiatorSocket() : ClockRateControlInitiatorSocket
• ClockRateControlSlaveBase() : ClockRateControlSlaveBase
• clocksLeft() : Intel8254Timer::Counter::CounterEvent
• ClockTick() : sc_gem5::ClockTick
• clone() : AtomicGeneric2Op< T > , AtomicGeneric3Op< T > , AtomicGenericPair3Op< T > , AtomicOpAdd< T > , AtomicOpAnd< T > , AtomicOpCAS< T > , AtomicOpDec< T > , AtomicOpExch< T > , AtomicOpFunctor , AtomicOpInc< T > , AtomicOpMax< T > , AtomicOpMin< T > , AtomicOpOr< T > , AtomicOpSub< T > , AtomicOpXor< T > , DeviceFDEntry , FDEntry , FileFDEntry , Gem5SystemC::Gem5Extension , HBFDEntry , Message , my_extension , PipeFDEntry , Process , RiscvISA::AtomicGenericOp< T > , RubyRequest , sc_dt::sc_bitref< X > , sc_dt::sc_bitref_r< T > , sc_dt::sc_concref< X, Y > , sc_dt::sc_concref_r< X, Y > , sc_dt::sc_subref< X > , sc_dt::sc_subref_r< X > , SocketFDEntry , tlm::tlm_endian_context , tlm::tlm_extension< T > , tlm::tlm_extension_base , tlm_utils::instance_specific_extension_carrier , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , TypedAtomicOpFunctor< T > , X86ISA::I386LinuxProcess , X86ISA::I386Process , X86ISA::X86_64LinuxProcess , X86ISA::X86_64Process , X86ISA::X86Process
• close() : ArmSemihosting::File , ArmSemihosting::FileBase , OutputDirectory , RawDiskImage
• closeFDEntry() : FDArray
• closeStreams() : MemTraceProbe , Trace::InstPBTrace
• cmd_async_cont() : BaseRemoteGDB
• cmd_async_step() : BaseRemoteGDB
• cmd_clr_hw_bkpt() : BaseRemoteGDB
• cmd_cont() : BaseRemoteGDB
• cmd_detach() : BaseRemoteGDB
• cmd_mem_r() : BaseRemoteGDB
• cmd_mem_w() : BaseRemoteGDB
• cmd_query_var() : BaseRemoteGDB
• cmd_reg_r() : BaseRemoteGDB
• cmd_reg_w() : BaseRemoteGDB
• cmd_set_hw_bkpt() : BaseRemoteGDB
• cmd_set_thread() : BaseRemoteGDB
• cmd_signal() : BaseRemoteGDB
• cmd_step() : BaseRemoteGDB
• cmd_unsupported() : BaseRemoteGDB
• cmdDisable() : HDLcd
• cmdEnable() : HDLcd
• cmdline() : AtagCmdline
• cmdStats() : BaseCache::CacheStats
• cmdString() : Packet
• cmdToIndex() : Packet
• Cmos() : X86ISA::Cmos
• CmovInst() : HsailISA::CmovInst< DataType >
• cmpAndSwap() : BaseCache
• CmpInst() : HsailISA::CmpInst< DestDataType, SrcDataType >
• CmpInstBase() : HsailISA::CmpInstBase< DestOperandType, SrcOperandType >
• cmpMask() : WriteMask
• cnt() : LinearEquation
• coalesce() : BaseCache , WriteAllocator
• coalesceMMIO() : KvmVM
• code() : MipsISA::AddressErrorFault , MipsISA::MipsFault< T > , MipsISA::MipsFaultBase , MipsISA::TlbFault< T > , MipsISA::TlbModifiedFault
• codeOffToKernelName() : ClDriver
• Coeff8() : Coeff8
• Coeff8x8() : Coeff8x8
• CoherentXBar() : CoherentXBar
• CoherentXBarMasterPort() : CoherentXBar::CoherentXBarMasterPort
• CoherentXBarSlavePort() : CoherentXBar::CoherentXBarSlavePort
• collateStats() : AbstractController , AddressProfiler , GarnetNetwork , GPUCoalescer , Network , PerfectSwitch , Profiler , Router , RubySystem , Sequencer , SimpleNetwork , Switch , Throttle
• collectionOutOfRange() : Gicv3Its , ItsCommand
• collectStatistics() : ExecStage , ScoreboardCheckStage
• combineTranslations() : SMMUTranslationProcess
• Command() : DRAMCtrl::Command
• command() : Sinic::Device
• commandHandler() : UFSHostDevice
• CommandLine() : LinuxAlphaSystem , LinuxMipsSystem
• commandName() : ItsCommand
• commit() : DefaultCommit< Impl > , IndirectPredictor , InstructionQueue< Impl > , Minor::Execute , SimpleIndirectPredictor
• commitDrained() : FullO3CPU< Impl >
• commitHead() : DefaultCommit< Impl >
• commitInst() : Minor::Execute
• commitInsts() : DefaultCommit< Impl >
• commitLoad() : LSQUnit< Impl >
• commitLoads() : LSQ< Impl > , LSQUnit< Impl >
• commitStores() : LSQ< Impl > , LSQUnit< Impl >
• committed() : LSQUnit< Impl >::SQEntry
• CommMonitor() : CommMonitor
• CommMonitorSenderState() : CommMonitor::CommMonitorSenderState
• CommonInstBase() : HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands >
• CompactorEntry() : PIFPrefetcher::CompactorEntry
• compare() : ThreadContext
• compareValue() : ArchTimer
• CompatAddrSpaceMod() : X86ISA::IntelMP::CompatAddrSpaceMod
• CompData() : DictionaryCompressor< T >::CompData , PerfectCompressor::CompData
• compDelayPhysRegDep() : ElasticTrace
• compDelayRob() : ElasticTrace
• complete() : ChunkGenerator , LSQ< Impl >::LSQRequest , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LQSenderState , LSQUnit< Impl >::SQSenderState
• completeAcc() : BaseO3DynInst< Impl > , GPUDynInst , GPUStaticInst , HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > , HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > , HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > , RiscvISA::RiscvMacroInst , SparcISA::SparcMacroInst , StaticInst
• completeBarrier() : MemDepUnit< MemDepPred, Impl >
• completed() : LSQUnit< Impl >::SQEntry , MemDepUnit< MemDepPred, Impl >
• completeDataAccess() : LSQ< Impl > , LSQUnit< Impl > , TimingSimpleCPU
• completeDisabledMemAccess() : Minor::LSQ::LSQRequest
• completeDrain() : ArmISA::TableWalker
• completeHitCallback() : GPUCoalescer
• completeIfetch() : TimingSimpleCPU
• completeIPI() : X86ISA::Interrupts
• completeIssue() : GPUCoalescer
• completeMemAccess() : TraceCPU::ElasticDataGen
• completeMemBarrierInst() : Minor::LSQ
• completeMemInst() : InstructionQueue< Impl >
• completePrefetch() : SMMUTranslationProcess
• completeRead() : MemChecker::ByteTracker , MemChecker
• completeRequest() : GarnetSyntheticTraffic , GlobalMemPipeline , MemTest
• completeStore() : LSQUnit< Impl >
• completeTimeSlot() : sc_gem5::Scheduler
• completeTransaction() : SMMUTranslationProcess
• completeWrite() : MemChecker::ByteTracker , MemChecker , MemChecker::WriteCluster
• completionWriteback() : IGbE::TxDescCache
• CompoundFlag() : Debug::CompoundFlag
• compress() : BaseCacheCompressor , BaseDelta< BaseType, DeltaSizeBits > , CPack , DictionaryCompressor< T > , FPCD , MultiCompressor , PerfectCompressor , RepeatedQwordsCompressor , ZeroCompressor
• Compressed() : Compressed
• compressed() : RiscvISA::Decoder , RiscvISA::PCState
• CompressedTags() : CompressedTags
• CompressionBlk() : CompressionBlk
• CompressionData() : BaseCacheCompressor::CompressionData
• compressValue() : DictionaryCompressor< T >
• compute_local_quantum() : tlm::tlm_global_quantum , tlm_utils::tlm_quantumkeeper
• computeActualWgSz() : Wavefront
• computeBits() : MultiperspectivePerceptron
• computeOutput() : MultiperspectivePerceptron
• computePartialSum() : MultiperspectivePerceptronTAGE
• computeRegClass() : X86ISA::InstRegIndex
• computeStats() : BaseTags , ClockedObject , DRAMCtrl::Rank
• computeStatsVisitor() : BaseTags
• ComputeUnit() : ComputeUnit
• computeUnit() : GPUExecContext
• concat_clear_data() : sc_dt::sc_concatref , sc_dt::sc_value_base
• concat_get_ctrl() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_get_data() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_get_uint64() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_length() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_concat_bool , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref_r , sc_dt::sc_int_subref_r , sc_dt::sc_signed , sc_dt::sc_signed_bitref_r , sc_dt::sc_signed_subref_r , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref_r , sc_dt::sc_uint_subref_r , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref_r , sc_dt::sc_unsigned_subref_r , sc_dt::sc_value_base
• concat_set() : sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_int_sigref , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signed_sigref , sc_core::sc_uint_sigref , sc_core::sc_unsigned_sigref , sc_dt::sc_concatref , sc_dt::sc_int_base , sc_dt::sc_int_bitref , sc_dt::sc_int_subref , sc_dt::sc_signed , sc_dt::sc_signed_bitref , sc_dt::sc_signed_subref , sc_dt::sc_uint_base , sc_dt::sc_uint_bitref , sc_dt::sc_uint_subref , sc_dt::sc_unsigned , sc_dt::sc_unsigned_bitref , sc_dt::sc_unsigned_subref , sc_dt::sc_value_base
• condBranchUpdate() : LoopPredictor , MPP_StatisticalCorrector , StatisticalCorrector , TAGEBase
• conditionalSquash() : O3ThreadContext< Impl >
• ConditionRegisterState() : ConditionRegisterState
• CondLogicOp() : PowerISA::CondLogicOp
• CondMoveOp() : PowerISA::CondMoveOp
• condOk() : PowerISA::BranchCond
• ConfigCache() : ConfigCache
• configCacheLookup() : SMMUTranslationProcess
• configCacheUpdate() : SMMUTranslationProcess
• configCP() : MipsISA::ISA
• ConfigTable() : X86ISA::IntelMP::ConfigTable
• conflictAddr() : MSHR , QueueEntry , WriteQueueEntry
• connect() : BaseRemoteGDB , TCPIface
• connectBasicBlocks() : ControlFlowInfo
• connectMemPorts() : CheckerThreadContext< TC >
• connectSocket() : VirtIO9PSocket
• connectWrapper() : BaseRemoteGDB
• console_in() : Terminal
• ConstNode() : Stats::ConstNode< T >
• construct() : ExtensionPool< T > , sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer
• ConstVectorNode() : Stats::ConstVectorNode< T >
• consume() : FunctionProfile
• consumeByte() : X86ISA::Decoder
• consumeBytes() : ArmISA::Decoder , X86ISA::Decoder
• consumeDescriptor() : VirtQueue
• consumeLink() : NetworkLink
• Consumer() : Consumer
• ContainerPrint() : m5::stl_helpers::ContainerPrint< T >
• contains() : AddrRange , AddrRangeMap< V, max_cache_size > , ChannelAddrRange , MemoryImage
• containsAddrRangeOf() : Minor::LSQ::LSQRequest
• context() : AlphaISA::Kernel::Statistics , BaseRemoteGDB
• Context() : sc_gem5::Thread::Context
• contextId() : BaseDynInst< Impl > , CheckerThreadContext< TC > , Iris::ThreadContext , LSQ< Impl >::LSQSenderState , Minor::ExecContext , O3ThreadContext< Impl > , Request , SimpleThread , ThreadContext , ThreadState
• contextIdToVCpuId() : KvmVM
• contextToThread() : BaseCPU
• contiguousHint() : ArmISA::TableWalker::LongDescriptor
• continueProcessing() : CopyEngine::CopyEngineChannel
• control() : ArchTimer
• ControlFlowInfo() : ControlFlowInfo
• convenience_socket_cb_holder() : tlm_utils::convenience_socket_cb_holder
• convert_2C_to_SM() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convert_SM_to_2C() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convert_SM_to_2C_to_SM() : sc_dt::sc_signed , sc_dt::sc_unsigned
• convertLlToRead() : Packet
• convertScToWrite() : Packet
• CoprocessorUnusableFault() : MipsISA::CoprocessorUnusableFault
• copy() : PollQueue , RefCountingPtr< T >
• copy_digits() : sc_dt::sc_signed , sc_dt::sc_unsigned
• copy_from() : Gem5SystemC::Gem5Extension , my_extension , tlm::tlm_endian_context , tlm::tlm_extension< T > , tlm::tlm_extension_base , tlm_utils::instance_specific_extension_carrier , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >::fw_process::mm_end_event_ext
• copyArchRegs() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• copyBankedDistRange() : MuxingKvmGic
• copyCpuRegister() : MuxingKvmGic
• copyDistRange() : MuxingKvmGic
• copyDistRegister() : MuxingKvmGic
• CopyEngine() : CopyEngine
• CopyEngineChannel() : CopyEngine::CopyEngineChannel
• copyError() : Packet
• copyGicState() : MuxingKvmGic
• copyIn() : BaseBufferArg , FrameBuffer
• copyOut() : AtagHeader , BaseBufferArg , FrameBuffer
• copyout() : PacketFifo
• copyPartial() : DataBlock
• copyResponderFlags() : Packet
• copyResult() : Checker< Impl >
• copyState() : SimpleThread
• copyTo() : VecRegContainer< Sz >
• CoreDecouplingLTInitiator() : CoreDecouplingLTInitiator
• coreId() : Sequencer
• CoreSpecific() : MipsISA::CoreSpecific
• CoreTimers() : GenericTimer::CoreTimers
• Coroutine() : m5::Coroutine< Arg, Ret >
• CortexA76() : FastModel::CortexA76
• CortexA76Cluster() : FastModel::CortexA76Cluster
• CortexA76TC() : FastModel::CortexA76TC
• count() : NetDest , Set
• countBankConflicts() : LdsState
• countCycles() : Ticked
• CountedExitEvent() : CountedExitEvent
• Counter() : Intel8254Timer::Counter
• counterAtCmpVal() : A9GlobalTimer::Timer
• counterAtZero() : Sp804::Timer
• CounterEvent() : Intel8254Timer::Counter::CounterEvent
• counterInterrupt() : Intel8254Timer , X86ISA::I8254 , X86ISA::I8254::X86Intel8254Timer
• counterLimitReached() : ArchTimer
• counterMatch() : PL031
• CounterState() : ArmISA::PMU::CounterState
• countInst() : BaseSimpleCPU
• countInsts() : InstructionQueue< Impl > , ROB< Impl >
• countIssuedStore() : Minor::LSQ::StoreBuffer
• countPacketsAfter() : PacketFifo
• countPacketsBefore() : PacketFifo
• countReadStarvingForAddress() : PersistentTable
• countStarvingForAddress() : PersistentTable
• countStat() : AlphaISA::AlignmentFault , AlphaISA::AlphaFault , AlphaISA::ArithmeticFault , AlphaISA::DtbAcvFault , AlphaISA::DtbAlignmentFault , AlphaISA::DtbFault , AlphaISA::DtbPageFault , AlphaISA::FloatEnableFault , AlphaISA::IntegerOverflowFault , AlphaISA::InterruptFault , AlphaISA::ItbAcvFault , AlphaISA::ItbFault , AlphaISA::ItbPageFault , AlphaISA::MachineCheckFault , AlphaISA::NDtbMissFault , AlphaISA::PalFault , AlphaISA::PDtbMissFault , AlphaISA::ResetFault , AlphaISA::UnimplementedOpcodeFault , AlphaISA::VectorEnableFault , ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , SparcISA::SparcFault< T > , SparcISA::SparcFaultBase
• countUnbound() : FastModel::SCGIC::Terminator
• CowDiskCallback() : CowDiskCallback
• CowDiskImage() : CowDiskImage
• cp() : SparcISA::PageTableEntry
• cpa() : CPA
• CPack() : CPack
• cpsrWriteByInstr() : ArmISA::ArmStaticInst
• CPU() : Iris::CPU< TC >
• cpuClearInt() : IGbE
• cpuEnabled() : GicV2
• CpuEvent() : CpuEvent
• CpuEventWrapper() : CpuEventWrapper< T, F >
• cpuId() : BaseCPU , BaseDynInst< Impl > , CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• CpuidResult() : X86ISA::CpuidResult
• cpuInterrupt() : NSGigE , Sinic::Base
• cpuIntrAck() : NSGigE , Sinic::Base
• cpuIntrClear() : NSGigE , Sinic::Base
• cpuIntrPending() : NSGigE , Sinic::Base
• cpuIntrPost() : NSGigE , Sinic::Base
• CpuLocalTimer() : CpuLocalTimer
• cpuOnline() : Linux
• CpuPort() : GarnetSyntheticTraffic::CpuPort , MemTest::CpuPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort
• cpuPostInt() : IGbE
• CPUProgressEvent() : CPUProgressEvent
• CpuSidePort() : BaseCache::CpuSidePort
• CPUSidePort() : SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort
• CpuSidePort() : TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• cpuStartup() : KvmVM
• create() : ArmSemihosting::FileBase , Kvm , OutputDirectory , QoS::QueuePolicy , StreamGen , tlm_utils::instance_specific_extension_container , tlm_utils::instance_specific_extension_container_pool
• create_element() : sc_core::sc_vector< T >
• createBackingStore() : PhysicalMemory
• createBasicBlocks() : ControlFlowInfo
• createContext() : Fiber
• createDevice() : KvmVM
• createDmaEngine() : HDLcd
• createDram() : BaseTrafficGen
• createDramRot() : BaseTrafficGen
• createExit() : BaseTrafficGen
• createHsaObject() : HsaObject
• createIdle() : BaseTrafficGen
• createIRQChip() : KvmVM
• createLinear() : BaseTrafficGen
• createLinks() : Topology
• createMemReqEvent() : ComputeUnit::DataPort
• createMemRespEvent() : ComputeUnit::DataPort
• createMissPacket() : BaseCache , Cache , NoncoherentCache
• createPkt() : QueuedPrefetcher::DeferredPacket
• createPrefetchRequest() : QueuedPrefetcher
• createProcess() : sc_gem5::ClockTick
• createRandom() : BaseTrafficGen
• createRead() : Packet
• createSpecs() : MultiperspectivePerceptron64KB , MultiperspectivePerceptron8KB , MultiperspectivePerceptron , MultiperspectivePerceptronTAGE64KB , MultiperspectivePerceptronTAGE8KB
• createStreams() : ProtoInputStream
• createSubdirectory() : OutputDirectory
• createTimers() : GenericTimer
• createTrace() : BaseTrafficGen
• createTraceFile() : Trace::InstPBTrace
• createVCPU() : KvmVM
• createVM() : Kvm
• createWrite() : Packet
• Credit() : Credit
• CreditLink() : CreditLink
• CrossbarSwitch() : CrossbarSwitch
• CSROp() : RiscvISA::CSROp
• cSwap() : ArmISA::ArmStaticInst
• CThread() : sc_gem5::CThread
• ctrlRead() : GenericTimerMem
• ctrlWrite() : GenericTimerMem
• ctrOk() : PowerISA::BranchCond
• ctrUpdate() : StatisticalCorrector , TAGEBase
• CUExitCallback() : ComputeUnit::CUExitCallback
• curCycle() : Clocked , Shader , TLBCoalescer , X86ISA::GpuTLB
• curPrefix() : Packet::PrintReqState
• currEL() : Gicv3CPUInterface
• current() : sc_gem5::Scheduler
• currentCount() : Intel8254Timer::Counter
• currentFiber() : Fiber
• currentSection() : Serializable
• currentTemperature() : ThermalDomain
• curTaskInfo() : Linux::ThreadInfo
• curTaskMm() : Linux::ThreadInfo
• curTaskMmFromTaskStruct() : Linux::ThreadInfo
• curTaskName() : Linux::ThreadInfo
• curTaskNameFromTaskStruct() : Linux::ThreadInfo
• curTaskPID() : Linux::ThreadInfo
• curTaskPIDFromTaskStruct() : Linux::ThreadInfo
• curTaskStart() : Linux::ThreadInfo
• curTaskStartFromTaskStruct() : Linux::ThreadInfo
• curTaskTGID() : Linux::ThreadInfo
• curTaskTGIDFromTaskStruct() : Linux::ThreadInfo
• curThreadInfo() : Linux::ThreadInfo
• CuSidePort() : LdsState::CuSidePort
• CustomNoMaliGpu() : CustomNoMaliGpu
• cv() : SparcISA::PageTableEntry
• CvtInst() : HsailISA::CvtInst< DestDataType, SrcDataType >
• CxxConfigFileBase() : CxxConfigFileBase
• CxxConfigManager() : CxxConfigManager
• CxxConfigParams() : CxxConfigParams
• CxxIniFile() : CxxIniFile
• Cycles() : Cycles
• cyclesBeforeInsert() : Minor::FUPipeline
• cyclesPerFrame() : DisplayTimings
• cyclesPerLine() : DisplayTimings
• cyclesSinceLastStopped() : Ticked
• cyclesToTicks() : Clocked