#include <timing.hh>

Inheritance diagram for TimingSimpleCPU:

Classes
class	DcachePort

class	FetchTranslation

class	IcachePort

struct	IprEvent

class	SplitFragmentSenderState

class	SplitMainSenderState

class	TimingCPUPort
	A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle. More...

Public Member Functions
	TimingSimpleCPU (TimingSimpleCPUParams *params)

virtual	~TimingSimpleCPU ()

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

DrainState	drain () override
	Notify an object that it needs to drain its state. More...

void	drainResume () override
	Resume execution after a successful drain. More...

void	switchOut () override
	Prepare for another CPU to take over execution. More...

void	takeOverFrom (BaseCPU *oldCPU) override
	Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in. More...

void	verifyMemoryMode () const override
	Verify that the system is in a memory mode supported by the CPU. More...

void	activateContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now active. More...

void	suspendContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now suspended. More...

Fault	initiateMemRead (Addr addr, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	writeMem (uint8_t data, unsigned size, Addr addr, Request::Flags flags, uint64_t res, const std::vector< bool > &byte_enable=std::vector< bool >()) override

Fault	initiateMemAMO (Addr addr, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op) override

void	fetch ()

void	sendFetch (const Fault &fault, const RequestPtr &req, ThreadContext *tc)

void	completeIfetch (PacketPtr)

void	completeDataAccess (PacketPtr pkt)

void	advanceInst (const Fault &fault)

bool	isSquashed () const
	This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed. More...

void	printAddr (Addr a)
	Print state of address in memory system via PrintReq (for debugging). More...

void	finishTranslation (WholeTranslationState *state)
	Finish a DTB translation. More...

Public Member Functions inherited from BaseSimpleCPU
	BaseSimpleCPU (BaseSimpleCPUParams *params)

virtual	~BaseSimpleCPU ()

void	wakeup (ThreadID tid) override

Addr	dbg_vtophys (Addr addr)

void	checkForInterrupts ()

void	setupFetchRequest (const RequestPtr &req)

void	preExecute ()

void	postExecute ()

void	advancePC (const Fault &fault)

void	haltContext (ThreadID thread_num) override
	Notify the CPU that the indicated context is now halted. More...

void	regStats () override
	Callback to set stat parameters. More...

void	resetStats () override
	Callback to reset stats. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

virtual Fault	readMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, const std::vector< bool > &byte_enable=std::vector< bool >())

virtual Fault	amoMem (Addr addr, uint8_t *data, unsigned size, Request::Flags flags, AtomicOpFunctorPtr amo_op)

void	countInst ()

Counter	totalInsts () const override

Counter	totalOps () const override

void	serializeThread (CheckpointOut &cp, ThreadID tid) const override
	Serialize a single thread. More...

void	unserializeThread (CheckpointIn &cp, ThreadID tid) override
	Unserialize one thread. More...

Public Member Functions inherited from BaseCPU
virtual PortProxy::SendFunctionalFunc	getSendFunctional ()
	Returns a sendFunctional delegate for use with port proxies. More...

int	cpuId () const
	Reads this CPU's ID. More...

uint32_t	socketId () const
	Reads this CPU's Socket ID. More...

MasterID	dataMasterId () const
	Reads this CPU's unique data requestor ID. More...

MasterID	instMasterId () const
	Reads this CPU's unique instruction requestor ID. More...

Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port on this CPU. More...

uint32_t	taskId () const
	Get cpu task id. More...

void	taskId (uint32_t id)
	Set cpu task id. More...

uint32_t	getPid () const

void	setPid (uint32_t pid)

void	workItemBegin ()

void	workItemEnd ()

Tick	instCount ()

BaseInterrupts *	getInterruptController (ThreadID tid)

void	postInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupt (ThreadID tid, int int_num, int index)

void	clearInterrupts (ThreadID tid)

bool	checkInterrupts (ThreadContext *tc) const

void	processProfileEvent ()

Trace::InstTracer *	getTracer ()
	Provide access to the tracer pointer. More...

int	findContext (ThreadContext *tc)
	Given a Thread Context pointer return the thread num. More...

virtual ThreadContext *	getContext (int tn)
	Given a thread num get tho thread context for it. More...

unsigned	numContexts ()
	Get the number of thread contexts available. More...

ThreadID	contextToThread (ContextID cid)
	Convert ContextID to threadID. More...

const Params *	params () const

	BaseCPU (Params *params, bool is_checker=false)

virtual	~BaseCPU ()

void	regProbePoints () override
	Register probe points for this object. More...

void	registerThreadContexts ()

void	deschedulePowerGatingEvent ()

void	schedulePowerGatingEvent ()

void	flushTLBs ()
	Flush all TLBs in the CPU. More...

bool	switchedOut () const
	Determine if the CPU is switched out. More...

unsigned int	cacheLineSize () const
	Get the cache line size of the system. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

void	scheduleInstStop (ThreadID tid, Counter insts, const char *cause)
	Schedule an event that exits the simulation loops after a predefined number of instructions. More...

uint64_t	getCurrentInstCount (ThreadID tid)
	Get the number of instructions executed by the specified thread on this CPU. More...

void	traceFunctions (Addr pc)

void	armMonitor (ThreadID tid, Addr address)

bool	mwait (ThreadID tid, PacketPtr pkt)

void	mwaitAtomic (ThreadID tid, ThreadContext tc, BaseTLB dtb)

AddressMonitor *	getCpuAddrMonitor (ThreadID tid)

bool	waitForRemoteGDB () const

virtual void	probeInstCommit (const StaticInstPtr &inst, Addr pc)
	Helper method to trigger PMU probes for a committed instruction. More...

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Enums::PwrState	pwrState () const

std::string	pwrStateName () const

std::vector< double >	pwrStateWeights () const
	Returns the percentage residency for each power state. More...

void	computeStats ()
	Record stats values like state residency by computing the time difference from previous update. More...

void	pwrState (Enums::PwrState)

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
Port &	getDataPort () override
	Return a reference to the data port. More...

Port &	getInstPort () override
	Return a reference to the instruction port. More...

Protected Member Functions inherited from BaseSimpleCPU
void	checkPcEventQueue ()

void	swapActiveThread ()

Protected Member Functions inherited from BaseCPU
void	updateCycleCounters (CPUState state)
	base method keeping track of cycle progression More...

void	enterPwrGating ()

ProbePoints::PMUUPtr	pmuProbePoint (const char *name)
	Helper method to instantiate probe points belonging to this object. More...

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Private Member Functions
void	threadSnoop (PacketPtr pkt, ThreadID sender)

void	sendData (const RequestPtr &req, uint8_t data, uint64_t res, bool read)

void	sendSplitData (const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

void	translationFault (const Fault &fault)

PacketPtr	buildPacket (const RequestPtr &req, bool read)

void	buildSplitPacket (PacketPtr &pkt1, PacketPtr &pkt2, const RequestPtr &req1, const RequestPtr &req2, const RequestPtr &req, uint8_t *data, bool read)

bool	handleReadPacket (PacketPtr pkt)

bool	handleWritePacket ()

void	updateCycleCounts ()

bool	isCpuDrained () const
	Check if a system is in a drained state. More...

bool	tryCompleteDrain ()
	Try to complete a drain request. More...

Private Attributes
FetchTranslation	fetchTranslation

IcachePort	icachePort

DcachePort	dcachePort

PacketPtr	ifetch_pkt

PacketPtr	dcache_pkt

Cycles	previousCycle

EventFunctionWrapper	fetchEvent

Additional Inherited Members
Public Types inherited from BaseCPU
typedef BaseCPUParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from BaseCPU
static int	numSimulatedInsts ()

static int	numSimulatedOps ()

static void	wakeup (ThreadID tid)

static int	numSimulatedCPUs ()

static Counter	numSimulatedInsts ()

static Counter	numSimulatedOps ()

Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Public Attributes inherited from BaseSimpleCPU
Trace::InstRecord *	traceData

CheckerCPU *	checker

std::vector< SimpleExecContext * >	threadInfo

std::list< ThreadID >	activeThreads

TheISA::MachInst	inst
	Current instruction. More...

StaticInstPtr	curStaticInst

StaticInstPtr	curMacroStaticInst

Public Attributes inherited from BaseCPU
TheISA::MicrocodeRom	microcodeRom

EventFunctionWrapper *	profileEvent

ThreadID	numThreads
	Number of threads we're actually simulating (<= SMT_MAX_THREADS). More...

System *	system

Stats::Scalar	numCycles

Stats::Scalar	numWorkItemsStarted

Stats::Scalar	numWorkItemsCompleted

Cycles	syscallRetryLatency

Static Public Attributes inherited from BaseCPU
static const uint32_t	invldPid = std::numeric_limits<uint32_t>::max()
	Invalid or unknown Pid. More...

static const Addr	PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Protected Types inherited from BaseSimpleCPU
enum	Status { Idle, Running, Faulting, ITBWaitResponse, IcacheRetry, IcacheWaitResponse, IcacheWaitSwitch, DTBWaitResponse, DcacheRetry, DcacheWaitResponse, DcacheWaitSwitch }

Protected Types inherited from BaseCPU
enum	CPUState { CPU_STATE_ON, CPU_STATE_SLEEP, CPU_STATE_WAKEUP }

Protected Attributes inherited from BaseSimpleCPU
ThreadID	curThread

BPredUnit *	branchPred

Status	_status

Protected Attributes inherited from BaseCPU
Tick	instCnt
	Instruction count used for SPARC misc register. More...

int	_cpuId

const uint32_t	_socketId
	Each cpu will have a socket ID that corresponds to its physical location in the system. More...

MasterID	_instMasterId
	instruction side request id that must be placed in all requests More...

MasterID	_dataMasterId
	data side request id that must be placed in all requests More...

uint32_t	_taskId
	An intrenal representation of a task identifier within gem5. More...

uint32_t	_pid
	The current OS process ID that is executing on this processor. More...

bool	_switchedOut
	Is the CPU switched out or active? More...

const unsigned int	_cacheLineSize
	Cache the cache line size that we get from the system. More...

std::vector< BaseInterrupts * >	interrupts

std::vector< ThreadContext * >	threadContexts

Trace::InstTracer *	tracer

Cycles	previousCycle

CPUState	previousState

const Cycles	pwrGatingLatency

const bool	powerGatingOnIdle

EventFunctionWrapper	enterPwrGatingEvent

ProbePoints::PMUUPtr	ppRetiredInsts
	Instruction commit probe point. More...

ProbePoints::PMUUPtr	ppRetiredInstsPC

ProbePoints::PMUUPtr	ppRetiredLoads
	Retired load instructions. More...

ProbePoints::PMUUPtr	ppRetiredStores
	Retired store instructions. More...

ProbePoints::PMUUPtr	ppRetiredBranches
	Retired branches (any type) More...

ProbePoints::PMUUPtr	ppAllCycles
	CPU cycle counter even if any thread Context is suspended. More...

ProbePoints::PMUUPtr	ppActiveCycles
	CPU cycle counter, only counts if any thread contexts is active. More...

ProbePointArg< bool > *	ppSleeping
	ProbePoint that signals transitions of threadContexts sets. More...

Protected Attributes inherited from ClockedObject
Enums::PwrState	_currPwrState
	To keep track of the current power state. More...

Tick	prvEvalTick

ClockedObject::ClockedObjectStats	stats

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Detailed Description

Definition at line 51 of file timing.hh.

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

TimingSimpleCPU::TimingSimpleCPU ( TimingSimpleCPUParams * params )

Definition at line 79 of file timing.cc.

References BaseSimpleCPU::_status, fetch(), BaseSimpleCPU::Idle, and SimObject::name().

Referenced by printAddr().

◆ ~TimingSimpleCPU()

TimingSimpleCPU::~TimingSimpleCPU ( )

virtual

Definition at line 89 of file timing.cc.

Member Function Documentation

◆ activateContext()

void TimingSimpleCPU::activateContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now active.

Reimplemented from BaseCPU.

Definition at line 209 of file timing.cc.

References BaseSimpleCPU::_status, BaseCPU::activateContext(), BaseSimpleCPU::activeThreads, Clocked::clockEdge(), DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, EventManager::schedule(), Event::scheduled(), and BaseSimpleCPU::threadInfo.

Referenced by getInstPort().

◆ advanceInst()

void TimingSimpleCPU::advanceInst ( const Fault & fault )

Definition at line 729 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::advancePC(), Clocked::clockEdge(), BaseSimpleCPU::curThread, DPRINTF, BaseSimpleCPU::Faulting, fetch(), fetchEvent, BaseSimpleCPU::Idle, NoFault, EventManager::reschedule(), BaseSimpleCPU::Running, SimpleExecContext::stayAtPC, BaseCPU::syscallRetryLatency, BaseSimpleCPU::threadInfo, and tryCompleteDrain().

Referenced by completeDataAccess(), completeIfetch(), getInstPort(), sendFetch(), and translationFault().

◆ buildPacket()

PacketPtr TimingSimpleCPU::buildPacket	(	const RequestPtr &	req,
		bool	read
	)

private

Definition at line 381 of file timing.cc.

References Packet::createRead(), and Packet::createWrite().

Referenced by buildSplitPacket(), and sendData().

◆ buildSplitPacket()

void TimingSimpleCPU::buildSplitPacket	(	PacketPtr &	pkt1,
		PacketPtr &	pkt2,
		const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read
	)

private

Definition at line 387 of file timing.cc.

References buildPacket(), Packet::cmd, data, Packet::dataDynamic(), Packet::dataStatic(), Request::NO_ACCESS, MemCmd::responseCommand(), and Packet::senderState.

Referenced by sendSplitData().

◆ completeDataAccess()

void TimingSimpleCPU::completeDataAccess ( PacketPtr pkt )

◆ completeIfetch()

void TimingSimpleCPU::completeIfetch ( PacketPtr pkt )

◆ drain()

DrainState TimingSimpleCPU::drain ( )

overridevirtual

Notify an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements Drainable.

Definition at line 94 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, Clocked::clockEdge(), BaseCPU::deschedulePowerGatingEvent(), DPRINTF, Drained, Draining, fetchEvent, BaseSimpleCPU::Idle, isCpuDrained(), BaseSimpleCPU::Running, EventManager::schedule(), Event::scheduled(), and BaseCPU::switchedOut().

Referenced by getInstPort().

◆ drainResume()

void TimingSimpleCPU::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from Drainable.

Definition at line 121 of file timing.cc.

References BaseSimpleCPU::_status, ThreadContext::Active, BaseSimpleCPU::activeThreads, DPRINTF, fetchEvent, BaseSimpleCPU::Idle, Clocked::nextCycle(), BaseCPU::numThreads, BaseSimpleCPU::Running, EventManager::schedule(), Event::scheduled(), BaseCPU::schedulePowerGatingEvent(), BaseCPU::switchedOut(), BaseCPU::system, BaseCPU::threadContexts, BaseSimpleCPU::threadInfo, System::totalNumInsts, and verifyMemoryMode().

Referenced by getInstPort().

◆ fetch()

void TimingSimpleCPU::fetch ( )

Definition at line 654 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::checkForInterrupts(), BaseSimpleCPU::checkPcEventQueue(), completeIfetch(), SimpleThread::contextId(), BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curMacroStaticInst, BaseSimpleCPU::curStaticInst, BaseSimpleCPU::curThread, DPRINTF, BaseTLB::Execute, fetchTranslation, SimpleThread::getTC(), BaseSimpleCPU::IcacheWaitResponse, BaseSimpleCPU::Idle, StaticInst::isDelayedCommit(), isRomMicroPC(), SimpleThread::itb, SimpleThread::pcState(), BaseSimpleCPU::Running, BaseSimpleCPU::setupFetchRequest(), BaseSimpleCPU::swapActiveThread(), BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseTLB::translateTiming(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by advanceInst(), getInstPort(), and TimingSimpleCPU().

◆ finishTranslation()

void TimingSimpleCPU::finishTranslation ( WholeTranslationState * state )

Finish a DTB translation.

Parameters

state The DTB translation state.

Definition at line 628 of file timing.cc.

References BaseSimpleCPU::_status, WholeTranslationState::data, WholeTranslationState::deleteReqs(), WholeTranslationState::getFault(), WholeTranslationState::isPrefetch(), WholeTranslationState::isSplit, WholeTranslationState::mainReq, WholeTranslationState::mode, NoFault, BaseTLB::Read, WholeTranslationState::res, BaseSimpleCPU::Running, sendData(), sendSplitData(), WholeTranslationState::setNoFault(), WholeTranslationState::sreqHigh, WholeTranslationState::sreqLow, and translationFault().

Referenced by isSquashed().

◆ getDataPort()

Port& TimingSimpleCPU::getDataPort ( )

inlineoverrideprotectedvirtual

Return a reference to the data port.

Implements BaseCPU.

Definition at line 267 of file timing.hh.

References dcachePort.

◆ getInstPort()

Port& TimingSimpleCPU::getInstPort ( )

inlineoverrideprotectedvirtual

Return a reference to the instruction port.

Implements BaseCPU.

Definition at line 270 of file timing.hh.

References activateContext(), addr, advanceInst(), completeDataAccess(), completeIfetch(), data, drain(), drainResume(), fetch(), icachePort, initiateMemAMO(), initiateMemRead(), sendFetch(), suspendContext(), switchOut(), takeOverFrom(), verifyMemoryMode(), and writeMem().

◆ handleReadPacket()

bool TimingSimpleCPU::handleReadPacket ( PacketPtr pkt )

private

Definition at line 259 of file timing.cc.

References BaseSimpleCPU::_status, Clocked::clockEdge(), BaseSimpleCPU::curThread, dcache_pkt, dcachePort, BaseSimpleCPU::DcacheRetry, BaseSimpleCPU::DcacheWaitResponse, SimpleThread::getTC(), AlphaISA::handleIprRead(), TheISA::handleLockedRead(), Packet::isRead(), Packet::req, MasterPort::sendTimingReq(), SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by sendData(), and sendSplitData().

◆ handleWritePacket()

bool TimingSimpleCPU::handleWritePacket ( )

private

Definition at line 475 of file timing.cc.

References BaseSimpleCPU::_status, Clocked::clockEdge(), BaseSimpleCPU::curThread, dcache_pkt, dcachePort, BaseSimpleCPU::DcacheRetry, BaseSimpleCPU::DcacheWaitResponse, SimpleThread::getTC(), AlphaISA::handleIprWrite(), Packet::req, MasterPort::sendTimingReq(), SimpleExecContext::thread, and BaseSimpleCPU::threadInfo.

Referenced by sendData(), and sendSplitData().

◆ init()

void TimingSimpleCPU::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from BaseSimpleCPU.

Definition at line 67 of file timing.cc.

References BaseSimpleCPU::init().

◆ initiateMemAMO()

Fault TimingSimpleCPU::initiateMemAMO	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		AtomicOpFunctorPtr	amo_op
	)

overridevirtual

Reimplemented from BaseSimpleCPU.

Definition at line 565 of file timing.cc.

References BaseSimpleCPU::_status, addr, ArmISA::asid, BaseCPU::cacheLineSize(), SimpleThread::contextId(), BaseSimpleCPU::curThread, BaseCPU::dataMasterId(), SimpleThread::dtb, BaseSimpleCPU::DTBWaitResponse, SimpleThread::getTC(), SimpleThread::instAddr(), ArmISA::mode, NoFault, panic, MipsISA::pc, roundDown(), Trace::InstRecord::setMem(), BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, BaseTLB::translateTiming(), and BaseTLB::Write.

Referenced by getInstPort().

◆ initiateMemRead()

Fault TimingSimpleCPU::initiateMemRead	(	Addr	addr,
		unsigned	size,
		Request::Flags	flags,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

Reimplemented from BaseSimpleCPU.

Definition at line 419 of file timing.cc.

References BaseSimpleCPU::_status, addr, ArmISA::asid, BaseCPU::cacheLineSize(), SimpleThread::contextId(), BaseSimpleCPU::curThread, BaseCPU::dataMasterId(), SimpleThread::dtb, BaseSimpleCPU::DTBWaitResponse, SimpleThread::getTC(), SimpleThread::instAddr(), ArmISA::mode, NoFault, MipsISA::pc, BaseTLB::Read, roundDown(), Trace::InstRecord::setMem(), BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, and BaseTLB::translateTiming().

Referenced by getInstPort().

◆ isCpuDrained()

bool TimingSimpleCPU::isCpuDrained ( ) const

inlineprivate

Check if a system is in a drained state.

We need to drain if:

We are in the middle of a microcode sequence as some CPUs (e.g., HW accelerated CPUs) can't be started in the middle of a gem5 microcode sequence.
Stay at PC is true.
A fetch event is scheduled. Normally this would never be the case with microPC() == 0, but right after a context is activated it can happen.

Definition at line 353 of file timing.hh.

References BaseSimpleCPU::curThread, SimpleThread::microPC(), Event::scheduled(), SimpleExecContext::stayAtPC, SimpleExecContext::thread, BaseSimpleCPU::threadInfo, and tryCompleteDrain().

Referenced by drain(), and tryCompleteDrain().

◆ isSquashed()

bool TimingSimpleCPU::isSquashed ( ) const

inline

This function is used by the page table walker to determine if it could translate the a pending request or if the underlying request has been squashed.

This always returns false for the simple timing CPU as it never executes any instructions speculatively. @ return Is the current instruction squashed?

Definition at line 311 of file timing.hh.

References ArmISA::a, finishTranslation(), and printAddr().

◆ printAddr()

void TimingSimpleCPU::printAddr ( Addr a )

Print state of address in memory system via PrintReq (for debugging).

Definition at line 1068 of file timing.cc.

References dcachePort, MasterPort::printAddr(), and TimingSimpleCPU().

Referenced by isSquashed().

◆ sendData()

void TimingSimpleCPU::sendData	(	const RequestPtr &	req,
		uint8_t *	data,
		uint64_t *	res,
		bool	read
	)

private

◆ sendFetch()

void TimingSimpleCPU::sendFetch	(	const Fault &	fault,
		const RequestPtr &	req,
		ThreadContext *	tc
	)

Definition at line 697 of file timing.cc.

References BaseSimpleCPU::_status, advanceInst(), BaseCPU::CPU_STATE_ON, DPRINTF, icachePort, BaseSimpleCPU::IcacheRetry, BaseSimpleCPU::IcacheWaitResponse, ifetch_pkt, BaseSimpleCPU::inst, NoFault, MemCmd::ReadReq, BaseSimpleCPU::Running, MasterPort::sendTimingReq(), BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by TimingSimpleCPU::FetchTranslation::finish(), and getInstPort().

◆ sendSplitData()

void TimingSimpleCPU::sendSplitData	(	const RequestPtr &	req1,
		const RequestPtr &	req2,
		const RequestPtr &	req,
		uint8_t *	data,
		bool	read
	)

private

Definition at line 325 of file timing.cc.

References buildSplitPacket(), TimingSimpleCPU::SplitFragmentSenderState::clearFromParent(), completeDataAccess(), dcache_pkt, handleReadPacket(), handleWritePacket(), Packet::makeResponse(), Request::NO_ACCESS, and Packet::senderState.

Referenced by finishTranslation().

◆ suspendContext()

void TimingSimpleCPU::suspendContext ( ThreadID thread_num )

overridevirtual

Notify the CPU that the indicated context is now suspended.

Check if possible to enter a lower power state

Reimplemented from BaseCPU.

Definition at line 233 of file timing.cc.

References BaseSimpleCPU::_status, BaseSimpleCPU::activeThreads, EventManager::deschedule(), DPRINTF, fetchEvent, BaseSimpleCPU::Idle, BaseCPU::numThreads, BaseSimpleCPU::Running, Event::scheduled(), BaseCPU::suspendContext(), and BaseSimpleCPU::threadInfo.

Referenced by getInstPort().

◆ switchOut()

void TimingSimpleCPU::switchOut ( )

overridevirtual

Prepare for another CPU to take over execution.

When this method exits, all internal state should have been flushed. After the method returns, the simulator calls takeOverFrom() on the new CPU with this CPU as its parameter.

Reimplemented from BaseCPU.

Definition at line 174 of file timing.cc.

References BaseSimpleCPU::_status, BaseCPU::CPU_STATE_ON, BaseSimpleCPU::curThread, fetchEvent, BaseSimpleCPU::Idle, M5_VAR_USED, BaseSimpleCPU::Running, Event::scheduled(), SimpleExecContext::stayAtPC, BaseCPU::switchOut(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by getInstPort().

◆ takeOverFrom()

void TimingSimpleCPU::takeOverFrom ( BaseCPU * cpu )

overridevirtual

Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be switched in.

A CPU model implementing this method is expected to initialize its state from the old CPU and connect its memory (unless they are already connected) to the memories connected to the old CPU.

Parameters

cpu	CPU to initialize read state from.

Reimplemented from BaseCPU.

Definition at line 192 of file timing.cc.

References Clocked::curCycle(), previousCycle, and BaseCPU::takeOverFrom().

Referenced by getInstPort().

◆ threadSnoop()

void TimingSimpleCPU::threadSnoop	(	PacketPtr	pkt,
		ThreadID	sender
	)

private

Definition at line 614 of file timing.cc.

References TimingSimpleCPU::DcachePort::cacheBlockMask, dcachePort, BaseCPU::getCpuAddrMonitor(), TheISA::handleLockedSnoop(), BaseCPU::numThreads, BaseSimpleCPU::threadInfo, and BaseSimpleCPU::wakeup().

Referenced by sendData().

◆ translationFault()

void TimingSimpleCPU::translationFault ( const Fault & fault )

private

Definition at line 362 of file timing.cc.

References advanceInst(), BaseCPU::CPU_STATE_ON, BaseSimpleCPU::postExecute(), BaseSimpleCPU::traceData, BaseCPU::updateCycleCounters(), and updateCycleCounts().

Referenced by finishTranslation().

◆ tryCompleteDrain()

bool TimingSimpleCPU::tryCompleteDrain ( )

private

Try to complete a drain request.

Returns: true if the CPU is drained, false otherwise.

Definition at line 158 of file timing.cc.

References DPRINTF, Draining, Drainable::drainState(), isCpuDrained(), and Drainable::signalDrainDone().

Referenced by advanceInst(), and isCpuDrained().

◆ updateCycleCounts()

void TimingSimpleCPU::updateCycleCounts ( )

private

Definition at line 937 of file timing.cc.

References Clocked::curCycle(), BaseCPU::numCycles, and previousCycle.

Referenced by completeDataAccess(), completeIfetch(), fetch(), sendFetch(), switchOut(), and translationFault().

◆ verifyMemoryMode()

void TimingSimpleCPU::verifyMemoryMode ( ) const

overridevirtual

Verify that the system is in a memory mode supported by the CPU.

Implementations are expected to query the system for the current memory mode and ensure that it is what the CPU model expects. If the check fails, the implementation should terminate the simulation using fatal().

Reimplemented from BaseCPU.

Definition at line 200 of file timing.cc.

References fatal, System::isTimingMode(), and BaseCPU::system.

Referenced by drainResume(), and getInstPort().

◆ writeMem()

Fault TimingSimpleCPU::writeMem	(	uint8_t *	data,
		unsigned	size,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res,
		const std::vector< bool > &	byte_enable = `std::vector<bool>()`
	)

overridevirtual

Reimplemented from BaseSimpleCPU.

Definition at line 497 of file timing.cc.

References BaseSimpleCPU::_status, addr, ArmISA::asid, BaseCPU::cacheLineSize(), SimpleThread::contextId(), BaseSimpleCPU::curThread, BaseCPU::dataMasterId(), SimpleThread::dtb, BaseSimpleCPU::DTBWaitResponse, SimpleThread::getTC(), SimpleThread::instAddr(), ArmISA::mode, NoFault, MipsISA::pc, roundDown(), Trace::InstRecord::setMem(), Request::STORE_NO_DATA, BaseCPU::taskId(), SimpleExecContext::thread, BaseSimpleCPU::threadInfo, BaseSimpleCPU::traceData, BaseTLB::translateTiming(), and BaseTLB::Write.

Referenced by getInstPort().

Member Data Documentation

◆ dcache_pkt

PacketPtr TimingSimpleCPU::dcache_pkt

private

Definition at line 260 of file timing.hh.

Referenced by handleReadPacket(), handleWritePacket(), sendData(), and sendSplitData().

◆ dcachePort

DcachePort TimingSimpleCPU::dcachePort

private

Definition at line 257 of file timing.hh.

Referenced by getDataPort(), handleReadPacket(), handleWritePacket(), printAddr(), sendData(), and threadSnoop().

◆ fetchEvent

EventFunctionWrapper TimingSimpleCPU::fetchEvent

private

Definition at line 327 of file timing.hh.

Referenced by activateContext(), advanceInst(), drain(), drainResume(), suspendContext(), and switchOut().

◆ fetchTranslation

FetchTranslation TimingSimpleCPU::fetchTranslation

private

Definition at line 133 of file timing.hh.

Referenced by fetch().

◆ icachePort

IcachePort TimingSimpleCPU::icachePort

private

Definition at line 256 of file timing.hh.

Referenced by getInstPort(), and sendFetch().

◆ ifetch_pkt

PacketPtr TimingSimpleCPU::ifetch_pkt

private

Definition at line 259 of file timing.hh.

Referenced by sendFetch().

◆ previousCycle

Cycles TimingSimpleCPU::previousCycle

private

Definition at line 262 of file timing.hh.

Referenced by takeOverFrom(), and updateCycleCounts().

The documentation for this class was generated from the following files:

cpu/simple/timing.hh
cpu/simple/timing.cc

Classes

Public Member Functions

Protected Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ TimingSimpleCPU()

◆ ~TimingSimpleCPU()

Member Function Documentation

◆ activateContext()

◆ advanceInst()

◆ buildPacket()

◆ buildSplitPacket()

◆ completeDataAccess()

◆ completeIfetch()

◆ drain()

◆ drainResume()

◆ fetch()

◆ finishTranslation()

◆ getDataPort()

◆ getInstPort()

◆ handleReadPacket()

◆ handleWritePacket()

◆ init()

◆ initiateMemAMO()

◆ initiateMemRead()

◆ isCpuDrained()

◆ isSquashed()

◆ printAddr()

◆ sendData()

◆ sendFetch()

◆ sendSplitData()

◆ suspendContext()

◆ switchOut()

◆ takeOverFrom()

◆ threadSnoop()

◆ translationFault()

◆ tryCompleteDrain()

◆ updateCycleCounts()

◆ verifyMemoryMode()

◆ writeMem()

Member Data Documentation

◆ dcache_pkt

◆ dcachePort

◆ fetchEvent

◆ fetchTranslation

◆ icachePort

◆ ifetch_pkt

◆ previousCycle