gem5  v19.0.0.0
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
Public Member Functions | Static Protected Attributes | List of all members
FastModel::CortexA76TC Class Reference

#include <thread_context.hh>

Inheritance diagram for FastModel::CortexA76TC:
Iris::ThreadContext ThreadContext PCEventScope

Public Member Functions

 CortexA76TC (::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
 
bool translateAddress (Addr &paddr, Addr vaddr) override
 
void initFromIrisInstance (const ResourceMap &resources) override
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, RegVal val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
iris::MemorySpaceId getBpSpaceId (Addr pc) const override
 
- Public Member Functions inherited from Iris::ThreadContext
 ThreadContext (::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
 
virtual ~ThreadContext ()
 
bool schedule (PCEvent *e) override
 
bool remove (PCEvent *e) override
 
void scheduleInstCountEvent (Event *event, Tick count) override
 
void descheduleInstCountEvent (Event *event) override
 
Tick getCurrentInstCount () override
 
::BaseCPU * getCpuPtr () override
 
int cpuId () const override
 
uint32_t socketId () const override
 
int threadId () const override
 
void setThreadId (int id) override
 
int contextId () const override
 
void setContextId (int id) override
 
BaseTLB * getITBPtr () override
 
BaseTLB * getDTBPtr () override
 
CheckerCPU * getCheckerCpuPtr () override
 
ArmISA::Decoder * getDecoderPtr () override
 
System * getSystemPtr () override
 
BaseISA * getIsaPtr () override
 
Kernel::Statistics * getKernelStats () override
 
PortProxy & getPhysProxy () override
 
PortProxy & getVirtProxy () override
 
void initMemProxies (::ThreadContext *tc) override
 
Process * getProcessPtr () override
 
void setProcessPtr (Process *p) override
 
Status status () const override
 
void setStatus (Status new_status) override
 
void activate () override
 Set the status to Active. More...
 
void suspend () override
 Set the status to Suspended. More...
 
void halt () override
 Set the status to Halted. More...
 
void dumpFuncProfile () override
 
void takeOverFrom (::ThreadContext *old_context) override
 
void regStats (const std::string &name) override
 
EndQuiesceEvent * getQuiesceEvent () override
 
Tick readLastActivate () override
 
Tick readLastSuspend () override
 
void profileClear () override
 
void profileSample () override
 
void copyArchRegs (::ThreadContext *tc) override
 
void clearArchRegs () override
 
RegVal readIntReg (RegIndex reg_idx) const override
 
RegVal readFloatReg (RegIndex reg_idx) const override
 
const VecRegContainer & readVecReg (const RegId &reg) const override
 
VecRegContainer & getWritableVecReg (const RegId &reg) override
 
const VecElem & readVecElem (const RegId &reg) const override
 
const VecPredRegContainer & readVecPredReg (const RegId &reg) const override
 
VecPredRegContainer & getWritableVecPredReg (const RegId &reg) override
 
RegVal readCCReg (RegIndex reg_idx) const override
 
void setIntReg (RegIndex reg_idx, RegVal val) override
 
void setFloatReg (RegIndex reg_idx, RegVal val) override
 
void setVecReg (const RegId &reg, const VecRegContainer &val) override
 
void setVecElem (const RegId &reg, const VecElem &val) override
 
void setVecPredReg (const RegId &reg, const VecPredRegContainer &val) override
 
void setCCReg (RegIndex reg_idx, RegVal val) override
 
void pcStateNoRecord (const ArmISA::PCState &val) override
 
MicroPC microPC () const override
 
ArmISA::PCState pcState () const override
 
void pcState (const ArmISA::PCState &val) override
 
Addr instAddr () const override
 
Addr nextInstAddr () const override
 
RegVal readMiscRegNoEffect (RegIndex misc_reg) const override
 
RegVal readMiscReg (RegIndex misc_reg) override
 
void setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override
 
void setMiscReg (RegIndex misc_reg, const RegVal val) override
 
RegId flattenRegId (const RegId &regId) const override
 
unsigned readStCondFailures () const override
 
void setStCondFailures (unsigned sc_failures) override
 
Counter readFuncExeInst () const override
 
void syscall (Fault *fault) override
 
ConstVecLane8 readVec8BitLaneReg (const RegId &reg) const override
 Vector Register Lane Interfaces. More...
 
ConstVecLane16 readVec16BitLaneReg (const RegId &reg) const override
 Reads source vector 16bit operand. More...
 
ConstVecLane32 readVec32BitLaneReg (const RegId &reg) const override
 Reads source vector 32bit operand. More...
 
ConstVecLane64 readVec64BitLaneReg (const RegId &reg) const override
 Reads source vector 64bit operand. More...
 
void setVecLane (const RegId &reg, const LaneData< LaneSize::Byte > &val) override
 Write a lane of the destination vector register. More...
 
void setVecLane (const RegId &reg, const LaneData< LaneSize::TwoByte > &val) override
 
void setVecLane (const RegId &reg, const LaneData< LaneSize::FourByte > &val) override
 
void setVecLane (const RegId &reg, const LaneData< LaneSize::EightByte > &val) override
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, uint64_t val) override
 
RegVal readFloatRegFlat (RegIndex idx) const override
 
void setFloatRegFlat (RegIndex idx, RegVal val) override
 
const VecRegContainer & readVecRegFlat (RegIndex idx) const override
 
VecRegContainer & getWritableVecRegFlat (RegIndex idx) override
 
void setVecRegFlat (RegIndex idx, const VecRegContainer &val) override
 
const VecElem & readVecElemFlat (RegIndex idx, const ElemIndex &elemIdx) const override
 
void setVecElemFlat (RegIndex idx, const ElemIndex &elemIdx, const VecElem &val) override
 
const VecPredRegContainer & readVecPredRegFlat (RegIndex idx) const override
 
VecPredRegContainer & getWritableVecPredRegFlat (RegIndex idx) override
 
void setVecPredRegFlat (RegIndex idx, const VecPredRegContainer &val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
- Public Member Functions inherited from ThreadContext
virtual void initMemProxies (ThreadContext *tc)=0
 Initialise the physical and virtual port proxies and tie them to the data port of the CPU. More...
 
virtual void setStatus (Status new_status)=0
 
void quiesce ()
 Quiesce thread context. More...
 
void quiesceTick (Tick resume)
 Quiesce, suspend, and schedule activate at resume. More...
 
virtual void takeOverFrom (ThreadContext *old_context)=0
 
virtual void copyArchRegs (ThreadContext *tc)=0
 
virtual void pcState (const TheISA::PCState &val)=0
 
void setNPC (Addr val)
 
virtual void pcStateNoRecord (const TheISA::PCState &val)=0
 
virtual int exit ()
 

Static Protected Attributes

static IdxNameMap miscRegIdxNameMap
 
static IdxNameMap intReg32IdxNameMap
 
static IdxNameMap intReg64IdxNameMap
 
static IdxNameMap flattenedIntIdxNameMap
 
static IdxNameMap ccRegIdxNameMap
 
static IdxNameMap vecRegIdxNameMap
 
static iris::MemorySpaceId bpSpaceId = iris::IRIS_UINT64_MAX
 

Additional Inherited Members

- Public Types inherited from Iris::ThreadContext
typedef std::map< std::string, iris::ResourceInfo > ResourceMap
 
typedef std::vector< iris::ResourceId > ResourceIds
 
typedef std::map< int, std::string > IdxNameMap
 
- Public Types inherited from ThreadContext
enum  Status { Active, Suspended, Halting, Halted }
 
- Static Public Member Functions inherited from ThreadContext
static void compare (ThreadContext *one, ThreadContext *two)
 function to compare two thread contexts (for debugging) More...
 
- Public Attributes inherited from ThreadContext
int intResult = DefaultIntResult
 
double floatResult = DefaultFloatResult
 
int intOffset = 0
 
- Static Public Attributes inherited from ThreadContext
static const int ints []
 
static const double floats []
 
static const int DefaultIntResult = 0
 
static const double DefaultFloatResult = 0.0
 
- Protected Types inherited from Iris::ThreadContext
using BpId = uint64_t
 
using BpInfoPtr = std::unique_ptr< BpInfo >
 
using BpInfoMap = std::map< Addr, BpInfoPtr >
 
using BpInfoIt = BpInfoMap::iterator
 
- Protected Types inherited from ThreadContext
typedef TheISA::MachInst MachInst
 
using VecRegContainer = TheISA::VecRegContainer
 
using VecElem = TheISA::VecElem
 
using VecPredRegContainer = TheISA::VecPredRegContainer
 
- Protected Member Functions inherited from Iris::ThreadContext
iris::ResourceId extractResourceId (const ResourceMap &resources, const std::string &name)
 
void extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
 
void maintainStepping ()
 
BpInfoIt getOrAllocBp (Addr pc)
 
void installBp (BpInfoIt it)
 
void uninstallBp (BpInfoIt it)
 
void delBp (BpInfoIt it)
 
iris::IrisErrorCode instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisCppAdapter & call () const
 
iris::IrisCppAdapter & noThrow () const
 
bool translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
 
- Protected Attributes inherited from Iris::ThreadContext
::BaseCPU * _cpu
 
int _threadId
 
ContextID _contextId
 
System * _system
 
::BaseTLB * _dtb
 
::BaseTLB * _itb
 
std::string _irisPath
 
iris::InstanceId _instId = iris::IRIS_UINT64_MAX
 
std::vector< ArmISA::VecRegContainer > vecRegs
 
std::vector< ArmISA::VecPredRegContainer > vecPredRegs
 
Status _status = Active
 
ResourceIds miscRegIds
 
ResourceIds intReg32Ids
 
ResourceIds intReg64Ids
 
ResourceIds flattenedIntIds
 
ResourceIds ccRegIds
 
iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX
 
iris::ResourceId icountRscId
 
ResourceIds vecRegIds
 
ResourceIds vecPredRegIds
 
std::vector< iris::MemorySpaceInfo > memorySpaces
 
std::vector< iris::MemorySupportedAddressTranslationResult > translations
 
std::unique_ptr< PortProxy > virtProxy = nullptr
 
std::unique_ptr< PortProxy > physProxy = nullptr
 
EventQueue comInstEventQueue
 
BpInfoMap bps
 
iris::EventStreamId regEventStreamId
 
iris::EventStreamId initEventStreamId
 
iris::EventStreamId timeEventStreamId
 
iris::EventStreamId breakpointEventStreamId
 
iris::IrisInstance client
 

Detailed Description

Definition at line 40 of file thread_context.hh.

Constructor & Destructor Documentation

◆ CortexA76TC()

FastModel::CortexA76TC::CortexA76TC ( ::BaseCPU *  cpu,
int  id,
System *  system,
::BaseTLB *  dtb,
::BaseTLB *  itb,
iris::IrisConnectionInterface *  iris_if,
const std::string &  iris_path 
)

Definition at line 40 of file thread_context.cc.

Member Function Documentation

◆ getBpSpaceId()

iris::MemorySpaceId FastModel::CortexA76TC::getBpSpaceId ( Addr  pc) const
overridevirtual

Implements Iris::ThreadContext.

Definition at line 186 of file thread_context.cc.

References bpSpaceId, ArmISA::CCREG_C, ArmISA::CCREG_FP, ArmISA::CCREG_GE, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ccRegIdxNameMap, Iris::CurrentMsn, flattenedIntIdxNameMap, intReg32IdxNameMap, intReg64IdxNameMap, ArmISA::INTREG_R0, ArmISA::INTREG_R1, ArmISA::INTREG_R10, ArmISA::INTREG_R10_FIQ, ArmISA::INTREG_R11, ArmISA::INTREG_R11_FIQ, ArmISA::INTREG_R12, ArmISA::INTREG_R12_FIQ, ArmISA::INTREG_R13, ArmISA::INTREG_R13_ABT, ArmISA::INTREG_R13_FIQ, ArmISA::INTREG_R13_HYP, ArmISA::INTREG_R13_IRQ, ArmISA::INTREG_R13_MON, ArmISA::INTREG_R13_SVC, ArmISA::INTREG_R13_UND, ArmISA::INTREG_R14, ArmISA::INTREG_R14_ABT, ArmISA::INTREG_R14_FIQ, ArmISA::INTREG_R14_IRQ, ArmISA::INTREG_R14_MON, ArmISA::INTREG_R14_SVC, ArmISA::INTREG_R14_UND, ArmISA::INTREG_R15, ArmISA::INTREG_R2, ArmISA::INTREG_R3, ArmISA::INTREG_R4, ArmISA::INTREG_R5, ArmISA::INTREG_R6, ArmISA::INTREG_R7, ArmISA::INTREG_R8, ArmISA::INTREG_R8_FIQ, ArmISA::INTREG_R9, ArmISA::INTREG_R9_FIQ, ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::INTREG_SP3, ArmISA::INTREG_SPX, ArmISA::INTREG_X0, ArmISA::INTREG_X1, ArmISA::INTREG_X10, ArmISA::INTREG_X11, ArmISA::INTREG_X12, ArmISA::INTREG_X13, ArmISA::INTREG_X14, ArmISA::INTREG_X15, ArmISA::INTREG_X16, ArmISA::INTREG_X17, ArmISA::INTREG_X18, ArmISA::INTREG_X19, ArmISA::INTREG_X2, ArmISA::INTREG_X20, ArmISA::INTREG_X21, ArmISA::INTREG_X22, ArmISA::INTREG_X23, ArmISA::INTREG_X24, ArmISA::INTREG_X25, ArmISA::INTREG_X26, ArmISA::INTREG_X27, ArmISA::INTREG_X28, ArmISA::INTREG_X29, ArmISA::INTREG_X3, ArmISA::INTREG_X30, ArmISA::INTREG_X4, ArmISA::INTREG_X5, ArmISA::INTREG_X6, ArmISA::INTREG_X7, ArmISA::INTREG_X8, ArmISA::INTREG_X9, Iris::ThreadContext::memorySpaces, ArmISA::MISCREG_ACTLR_EL1, ArmISA::MISCREG_ACTLR_EL2, ArmISA::MISCREG_ACTLR_EL3, ArmISA::MISCREG_ADFSR, ArmISA::MISCREG_AFSR0_EL1, ArmISA::MISCREG_AFSR0_EL2, ArmISA::MISCREG_AFSR0_EL3, ArmISA::MISCREG_AFSR1_EL1, ArmISA::MISCREG_AFSR1_EL2, ArmISA::MISCREG_AFSR1_EL3, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_AIDR_EL1, ArmISA::MISCREG_AIFSR, ArmISA::MISCREG_AMAIR0_NS, ArmISA::MISCREG_AMAIR1_NS, ArmISA::MISCREG_AMAIR_EL1, ArmISA::MISCREG_AMAIR_EL2, ArmISA::MISCREG_AMAIR_EL3, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CCSIDR_EL1, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CLIDR_EL1, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTFRQ_EL0, ArmISA::MISCREG_CNTHCTL, ArmISA::MISCREG_CNTHCTL_EL2, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CTL_EL2, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTHP_CVAL_EL2, ArmISA::MISCREG_CNTHP_TVAL, ArmISA::MISCREG_CNTHP_TVAL_EL2, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTKCTL, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTP_CTL, ArmISA::MISCREG_CNTP_CTL_EL0, ArmISA::MISCREG_CNTP_CVAL, ArmISA::MISCREG_CNTP_CVAL_EL0, ArmISA::MISCREG_CNTP_TVAL, ArmISA::MISCREG_CNTP_TVAL_EL0, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPCT_EL0, ArmISA::MISCREG_CNTPS_CTL_EL1, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTPS_TVAL_EL1, ArmISA::MISCREG_CNTV_CTL, ArmISA::MISCREG_CNTV_CTL_EL0, ArmISA::MISCREG_CNTV_CVAL, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTV_TVAL, ArmISA::MISCREG_CNTV_TVAL_EL0, ArmISA::MISCREG_CNTVCT, ArmISA::MISCREG_CNTVCT_EL0, ArmISA::MISCREG_CNTVOFF, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR_EL1, ArmISA::MISCREG_CONTEXTIDR_EL2, ArmISA::MISCREG_CONTEXTIDR_NS, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_MODE, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CPUACTLR_EL1, ArmISA::MISCREG_CPUECTLR_EL1, ArmISA::MISCREG_CPUMERRSR, ArmISA::MISCREG_CPUMERRSR_EL1, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CSSELR_EL1, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_DACR_NS, ArmISA::MISCREG_DBGAUTHSTATUS, ArmISA::MISCREG_DBGAUTHSTATUS_EL1, ArmISA::MISCREG_DBGBCR0, ArmISA::MISCREG_DBGBCR0_EL1, ArmISA::MISCREG_DBGBCR1, ArmISA::MISCREG_DBGBCR1_EL1, ArmISA::MISCREG_DBGBCR2, ArmISA::MISCREG_DBGBCR2_EL1, ArmISA::MISCREG_DBGBCR3, ArmISA::MISCREG_DBGBCR3_EL1, ArmISA::MISCREG_DBGBCR4, ArmISA::MISCREG_DBGBCR4_EL1, ArmISA::MISCREG_DBGBCR5, ArmISA::MISCREG_DBGBCR5_EL1, ArmISA::MISCREG_DBGBVR0, ArmISA::MISCREG_DBGBVR0_EL1, ArmISA::MISCREG_DBGBVR1, ArmISA::MISCREG_DBGBVR1_EL1, ArmISA::MISCREG_DBGBVR2, ArmISA::MISCREG_DBGBVR2_EL1, ArmISA::MISCREG_DBGBVR3, ArmISA::MISCREG_DBGBVR3_EL1, ArmISA::MISCREG_DBGBVR4, ArmISA::MISCREG_DBGBVR4_EL1, ArmISA::MISCREG_DBGBVR5, ArmISA::MISCREG_DBGBVR5_EL1, ArmISA::MISCREG_DBGBXVR4, ArmISA::MISCREG_DBGBXVR5, ArmISA::MISCREG_DBGCLAIMCLR, ArmISA::MISCREG_DBGCLAIMCLR_EL1, ArmISA::MISCREG_DBGCLAIMSET, ArmISA::MISCREG_DBGCLAIMSET_EL1, ArmISA::MISCREG_DBGDTRRXext, ArmISA::MISCREG_DBGDTRTXext, ArmISA::MISCREG_DBGOSLAR, ArmISA::MISCREG_DBGPRCR, ArmISA::MISCREG_DBGPRCR_EL1, ArmISA::MISCREG_DBGWCR0, ArmISA::MISCREG_DBGWCR0_EL1, ArmISA::MISCREG_DBGWCR1, ArmISA::MISCREG_DBGWCR1_EL1, ArmISA::MISCREG_DBGWCR2, ArmISA::MISCREG_DBGWCR2_EL1, ArmISA::MISCREG_DBGWCR3, ArmISA::MISCREG_DBGWCR3_EL1, ArmISA::MISCREG_DBGWFAR, ArmISA::MISCREG_DBGWVR0, ArmISA::MISCREG_DBGWVR0_EL1, ArmISA::MISCREG_DBGWVR1, ArmISA::MISCREG_DBGWVR1_EL1, ArmISA::MISCREG_DBGWVR2, ArmISA::MISCREG_DBGWVR2_EL1, ArmISA::MISCREG_DBGWVR3, ArmISA::MISCREG_DBGWVR3_EL1, ArmISA::MISCREG_DC_CISW_Xt, ArmISA::MISCREG_DC_CIVAC_Xt, ArmISA::MISCREG_DC_CSW_Xt, ArmISA::MISCREG_DC_CVAC_Xt, ArmISA::MISCREG_DC_CVAU_Xt, ArmISA::MISCREG_DC_ISW_Xt, ArmISA::MISCREG_DC_IVAC_Xt, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DCCISW, ArmISA::MISCREG_DCCMVAC, ArmISA::MISCREG_DCCMVAU, ArmISA::MISCREG_DCCSW, ArmISA::MISCREG_DCIMVAC, ArmISA::MISCREG_DCISW, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR_NS, ArmISA::MISCREG_DFSR_NS, ArmISA::MISCREG_DISR_EL1, ArmISA::MISCREG_DLR_EL0, ArmISA::MISCREG_DSPSR_EL0, ArmISA::MISCREG_ELR_EL1, ArmISA::MISCREG_ELR_EL2, ArmISA::MISCREG_ELR_EL3, ArmISA::MISCREG_ERRIDR_EL1, ArmISA::MISCREG_ERRSELR_EL1, ArmISA::MISCREG_ERXADDR_EL1, ArmISA::MISCREG_ERXCTLR_EL1, ArmISA::MISCREG_ERXFR_EL1, ArmISA::MISCREG_ERXMISC0_EL1, ArmISA::MISCREG_ERXMISC1_EL1, ArmISA::MISCREG_ERXSTATUS_EL1, ArmISA::MISCREG_ESR_EL1, ArmISA::MISCREG_ESR_EL2, ArmISA::MISCREG_ESR_EL3, ArmISA::MISCREG_FAR_EL1, ArmISA::MISCREG_FAR_EL2, ArmISA::MISCREG_FAR_EL3, ArmISA::MISCREG_FCSEIDR, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HACR, ArmISA::MISCREG_HACR_EL2, ArmISA::MISCREG_HACTLR, ArmISA::MISCREG_HAMAIR0, ArmISA::MISCREG_HAMAIR1, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDCR, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HMAIR0, ArmISA::MISCREG_HMAIR1, ArmISA::MISCREG_HPFAR, ArmISA::MISCREG_HPFAR_EL2, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_HSTR_EL2, ArmISA::MISCREG_HTPIDR, ArmISA::MISCREG_HTTBR, ArmISA::MISCREG_HVBAR, ArmISA::MISCREG_IC_IALLU, ArmISA::MISCREG_IC_IALLUIS, ArmISA::MISCREG_IC_IVAU_Xt, ArmISA::MISCREG_ICIALLU, ArmISA::MISCREG_ICIALLUIS, ArmISA::MISCREG_ICIMVAU, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_AFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR0_EL1, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR1_EL1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR2_EL1, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR3_EL1, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR4_EL1, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_ISAR5_EL1, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR0_EL1, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR1_EL1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR2_EL1, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_MMFR3_EL1, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR0_EL1, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_ID_PFR1_EL1, ArmISA::MISCREG_IFAR_NS, ArmISA::MISCREG_IFSR_NS, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_L2MERRSR, ArmISA::MISCREG_L2MERRSR_EL1, ArmISA::MISCREG_MAIR_EL1, ArmISA::MISCREG_MAIR_EL2, ArmISA::MISCREG_MAIR_EL3, ArmISA::MISCREG_MDCCINT_EL1, ArmISA::MISCREG_MDCCSR_EL0, ArmISA::MISCREG_MDCR_EL2, ArmISA::MISCREG_MDCR_EL3, ArmISA::MISCREG_MDRAR_EL1, ArmISA::MISCREG_MDSCR_EL1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_MVBAR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR0_EL1, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_MVFR1_EL1, ArmISA::MISCREG_MVFR2_EL1, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_OSDLR_EL1, ArmISA::MISCREG_OSDTRRX_EL1, ArmISA::MISCREG_OSDTRTX_EL1, ArmISA::MISCREG_OSECCR_EL1, ArmISA::MISCREG_OSLAR_EL1, ArmISA::MISCREG_OSLSR_EL1, ArmISA::MISCREG_PAR_EL1, ArmISA::MISCREG_PAR_NS, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMCCFILTR_EL0, ArmISA::MISCREG_PMCCNTR, ArmISA::MISCREG_PMCCNTR_EL0, ArmISA::MISCREG_PMCEID0, ArmISA::MISCREG_PMCEID0_EL0, ArmISA::MISCREG_PMCEID1, ArmISA::MISCREG_PMCEID1_EL0, ArmISA::MISCREG_PMCNTENCLR, ArmISA::MISCREG_PMCNTENCLR_EL0, ArmISA::MISCREG_PMCNTENSET, ArmISA::MISCREG_PMCNTENSET_EL0, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMCR_EL0, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVCNTR1_EL0, ArmISA::MISCREG_PMEVCNTR2_EL0, ArmISA::MISCREG_PMEVCNTR3_EL0, ArmISA::MISCREG_PMEVCNTR4_EL0, ArmISA::MISCREG_PMEVCNTR5_EL0, ArmISA::MISCREG_PMEVTYPER0_EL0, ArmISA::MISCREG_PMEVTYPER1_EL0, ArmISA::MISCREG_PMEVTYPER2_EL0, ArmISA::MISCREG_PMEVTYPER3_EL0, ArmISA::MISCREG_PMEVTYPER4_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENCLR, ArmISA::MISCREG_PMINTENCLR_EL1, ArmISA::MISCREG_PMINTENSET, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSCLR_EL0, ArmISA::MISCREG_PMOVSR, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMSELR_EL0, ArmISA::MISCREG_PMSWINC, ArmISA::MISCREG_PMSWINC_EL0, ArmISA::MISCREG_PMUSERENR, ArmISA::MISCREG_PMUSERENR_EL0, ArmISA::MISCREG_PMXEVCNTR, ArmISA::MISCREG_PMXEVCNTR_EL0, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_EL0, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_RAMINDEX, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_REVIDR_EL1, ArmISA::MISCREG_RMR, ArmISA::MISCREG_RMR_EL3, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SDER, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE2, ArmISA::MISCREG_TLBI_ALLE2IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TPIDR_EL0, ArmISA::MISCREG_TPIDR_EL1, ArmISA::MISCREG_TPIDR_EL2, ArmISA::MISCREG_TPIDR_EL3, ArmISA::MISCREG_TPIDRPRW_NS, ArmISA::MISCREG_TPIDRRO_EL0, ArmISA::MISCREG_TPIDRURO_NS, ArmISA::MISCREG_TPIDRURW_NS, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR0_NS, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_TTBR1_NS, ArmISA::MISCREG_VBAR_EL1, ArmISA::MISCREG_VBAR_EL2, ArmISA::MISCREG_VBAR_EL3, ArmISA::MISCREG_VBAR_NS, ArmISA::MISCREG_VDISR_EL2, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VMPIDR_EL2, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_VPIDR_EL2, ArmISA::MISCREG_VSESR_EL2, ArmISA::MISCREG_VTCR_EL2, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_VTTBR_EL2, miscRegIdxNameMap, panic_if, and vecRegIdxNameMap.

◆ initFromIrisInstance()

void FastModel::CortexA76TC::initFromIrisInstance ( const ResourceMap &  resources)
overridevirtual

Reimplemented from Iris::ThreadContext.

Definition at line 85 of file thread_context.cc.

References Iris::ThreadContext::ccRegIds, ccRegIdxNameMap, Iris::ThreadContext::extractResourceId(), Iris::ThreadContext::extractResourceMap(), Iris::ThreadContext::flattenedIntIds, flattenedIntIdxNameMap, Iris::ThreadContext::intReg32Ids, intReg32IdxNameMap, Iris::ThreadContext::intReg64Ids, intReg64IdxNameMap, Iris::ThreadContext::miscRegIds, miscRegIdxNameMap, Iris::ThreadContext::pcRscId, Iris::ThreadContext::vecRegIds, and vecRegIdxNameMap.

◆ readCCRegFlat()

RegVal FastModel::CortexA76TC::readCCRegFlat ( RegIndex  idx) const
overridevirtual

Implements ThreadContext.

Definition at line 146 of file thread_context.cc.

References bits(), ArmISA::CCREG_FP, ArmISA::CCREG_NZ, and Iris::ThreadContext::readCCRegFlat().

◆ readIntRegFlat()

RegVal FastModel::CortexA76TC::readIntRegFlat ( RegIndex  idx) const
overridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements ThreadContext.

Definition at line 104 of file thread_context.cc.

References ArmISA::INTREG_R13_MON, ArmISA::INTREG_R14_MON, ArmISA::MISCREG_CPSR, ArmISA::MODE_MON, ThreadContext::readIntRegFlat(), Iris::ThreadContext::readMiscRegNoEffect(), and X86ISA::val.

◆ setCCRegFlat()

void FastModel::CortexA76TC::setCCRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

Implements ThreadContext.

Definition at line 163 of file thread_context.cc.

References ArmISA::CCREG_FP, ArmISA::CCREG_NZ, insertBits(), ArmISA::MISCREG_CPSR, ArmISA::MISCREG_FPSCR, Iris::ThreadContext::readMiscRegNoEffect(), Iris::ThreadContext::setCCRegFlat(), and X86ISA::val.

◆ setIntRegFlat()

void FastModel::CortexA76TC::setIntRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

Implements ThreadContext.

Definition at line 127 of file thread_context.cc.

References ArmISA::INTREG_R13_MON, ArmISA::INTREG_R14_MON, ArmISA::MISCREG_CPSR, ArmISA::MODE_MON, Iris::ThreadContext::readMiscRegNoEffect(), ThreadContext::setIntRegFlat(), and Iris::ThreadContext::setMiscReg().

◆ translateAddress()

bool FastModel::CortexA76TC::translateAddress ( Addr &  paddr,
Addr  vaddr 
)
overridevirtual

Implements Iris::ThreadContext.

Definition at line 48 of file thread_context.cc.

References ArmISA::currEL(), ArmISA::EL2, ArmISA::EL3, Iris::GuestMsn, ArmISA::inSecureState(), Iris::ThreadContext::memorySpaces, Iris::NsHypMsn, panic_if, Iris::PhysicalMemoryNonSecureMsn, Iris::PhysicalMemorySecureMsn, and Iris::SecureMonitorMsn.

Member Data Documentation

◆ bpSpaceId

iris::MemorySpaceId FastModel::CortexA76TC::bpSpaceId = iris::IRIS_UINT64_MAX
staticprotected

Definition at line 49 of file thread_context.hh.

Referenced by getBpSpaceId().

◆ ccRegIdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::ccRegIdxNameMap
staticprotected

Definition at line 47 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

◆ flattenedIntIdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::flattenedIntIdxNameMap
staticprotected

Definition at line 46 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

◆ intReg32IdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::intReg32IdxNameMap
staticprotected

Definition at line 44 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

◆ intReg64IdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::intReg64IdxNameMap
staticprotected

Definition at line 45 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

◆ miscRegIdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::miscRegIdxNameMap
staticprotected

Definition at line 43 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

◆ vecRegIdxNameMap

Iris::ThreadContext::IdxNameMap FastModel::CortexA76TC::vecRegIdxNameMap
staticprotected

Definition at line 48 of file thread_context.hh.

Referenced by getBpSpaceId(), and initFromIrisInstance().

The documentation for this class was generated from the following files:
Generated on Fri Feb 28 2020 16:27:21 for gem5 by doxygen 1.8.13