ArmISA::ISA Class Reference

#include <isa.hh>

Inheritance diagram for ArmISA::ISA:

Classes
struct	MiscRegLUTEntry
	MiscReg metadata. More...
class	MiscRegLUTEntryInitializer

Public Types
typedef ArmISAParams	Params
Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
void	clear ()
RegVal	readMiscRegNoEffect (int misc_reg) const
RegVal	readMiscReg (int misc_reg, ThreadContext *tc)
void	setMiscRegNoEffect (int misc_reg, RegVal val)
void	setMiscReg (int misc_reg, RegVal val, ThreadContext *tc)
RegId	flattenRegId (const RegId &regId) const
int	flattenIntIndex (int reg) const
int	flattenFloatIndex (int reg) const
int	flattenVecIndex (int reg) const
int	flattenVecElemIndex (int reg) const
int	flattenVecPredIndex (int reg) const
int	flattenCCIndex (int reg) const
int	flattenMiscIndex (int reg) const
int	snsBankedIndex64 (MiscRegIndex reg, bool ns) const
std::pair< int, int >	getMiscIndices (int misc_reg) const
unsigned	getCurSveVecLenInBits (ThreadContext *tc) const
unsigned	getCurSveVecLenInBitsAtReset () const
void	serialize (CheckpointOut &cp) const
	Serialize an object. More...
void	unserialize (CheckpointIn &cp)
	Unserialize an object. More...
void	startup (ThreadContext *tc)
Enums::DecoderFlavour	decoderFlavour () const
bool	haveGICv3CpuIfc () const
	Getter for haveGICv3CPUInterface. More...
Enums::VecRegRenameMode	vecRegRenameMode () const
const Params *	params () const
	ISA (Params *p)
Public Member Functions inherited from SimObject
const Params *	params () const
	SimObject (const Params *_params)
virtual	~SimObject ()
virtual const std::string	name () const
virtual void	init ()
	init() is called after all C++ SimObjects have been created and all ports are connected. More...
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regProbePoints ()
	Register probe points for this object. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
virtual void	startup ()
	startup() is the final initialization call before simulation. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
Public Member Functions inherited from EventManager
	EventManager (EventManager &em)
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
void	setCurTick (Tick newVal)
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from Stats::Group
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group. More...
virtual	~Group ()
virtual void	regStats ()
	Callback to set stat parameters. More...
virtual void	resetStats ()
	Callback to reset stats. More...
virtual void	preDumpStats ()
	Callback before stats are dumped. More...
void	addStat (Stats::Info *info)
	Register a stat with this group. More...
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block. More...

Static Public Member Functions
static void	zeroSveVecRegUpperPart (VecRegContainer &vc, unsigned eCount)
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
static void	unserializeGlobals (CheckpointIn &cp)

Protected Member Functions
const MiscRegLUTEntryInitializer	InitReg (uint32_t reg)
void	initializeMiscRegMetadata ()
void	updateRegMap (CPSR cpsr)
BaseISADevice &	getGenericTimer (ThreadContext *tc)
BaseISADevice &	getGICv3CPUInterface (ThreadContext *tc)
void	clear32 (const ArmISAParams *p, const SCTLR &sctlr_rst)
void	clear64 (const ArmISAParams *p)
void	initID32 (const ArmISAParams *p)
void	initID64 (const ArmISAParams *p)
Protected Member Functions inherited from Drainable
	Drainable ()
virtual	~Drainable ()
virtual void	drainResume ()
	Resume execution after a successful drain. More...
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
ArmSystem *	system
const Enums::DecoderFlavour	_decoderFlavour
const Enums::VecRegRenameMode	_vecRegRenameMode
DummyISADevice	dummyDevice
	Dummy device for to handle non-existing ISA devices. More...
BaseISADevice *	pmu
std::unique_ptr< BaseISADevice >	timer
std::unique_ptr< BaseISADevice >	gicv3CpuInterface
bool	highestELIs64
bool	haveSecurity
bool	haveLPAE
bool	haveVirtualization
bool	haveCrypto
bool	haveLargeAsid64
bool	haveGICv3CPUInterface
uint8_t	physAddrRange
bool	haveSVE
bool	haveLSE
bool	havePAN
unsigned	sveVL
	SVE vector length in quadwords. More...
bool	impdefAsNop
	If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION. More...
bool	afterStartup
RegVal	miscRegs [NumMiscRegs]
const IntRegIndex *	intRegMap
Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Static Protected Attributes
static std::vector< struct MiscRegLUTEntry >	lookUpMiscReg
	Metadata table accessible via the value of the register. More...

Private Member Functions
void	assert32 (ThreadContext *tc)
void	assert64 (ThreadContext *tc)

Additional Inherited Members
Static Public Attributes inherited from Serializable
static int	ckptCount = 0
static int	ckptMaxCount = 0
static int	ckptPrevCount = -1

Detailed Description

Definition at line 67 of file isa.hh.

Member Typedef Documentation

Params

typedef ArmISAParams ArmISA::ISA::Params

Definition at line 769 of file isa.hh.

Constructor & Destructor Documentation

ISA()

ArmISA::ISA::ISA

(

Params *

p

)

Definition at line 64 of file isa.cc.

References _vecRegRenameMode, clear(), dummyDevice, FullSystem, haveCrypto, ArmSystem::haveCrypto(), haveLargeAsid64, ArmSystem::haveLargeAsid64(), haveLPAE, ArmSystem::haveLPAE(), haveLSE, ArmSystem::haveLSE(), havePAN, ArmSystem::havePAN(), haveSecurity, ArmSystem::haveSecurity(), haveSVE, ArmSystem::haveSVE(), haveVirtualization, ArmSystem::haveVirtualization(), highestELIs64, ArmSystem::highestELIs64(), initializeMiscRegMetadata(), lookUpMiscReg, ArmISA::MISCREG_SCTLR_RST, miscRegs, ArmISA::NUM_MISCREGS, physAddrRange, ArmSystem::physAddrRange(), pmu, ArmISA::preUnflattenMiscReg(), ArmISA::BaseISADevice::setISA(), sveVL, ArmSystem::sveVL(), and system.

Member Function Documentation

assert32()

void ArmISA::ISA::assert32 ( ThreadContext *  tc )

inlineprivate

Definition at line 457 of file isa.hh.

References M5_VAR_USED, ArmISA::MISCREG_CPSR, and readMiscReg().

Referenced by setMiscReg().

assert64()

void ArmISA::ISA::assert64 ( ThreadContext *  tc )

inlineprivate

Definition at line 462 of file isa.hh.

References clear(), clear32(), clear64(), initID32(), initID64(), M5_VAR_USED, ArmISA::MISCREG_CPSR, MipsISA::p, readMiscReg(), readMiscRegNoEffect(), setMiscReg(), setMiscRegNoEffect(), and X86ISA::val.

Referenced by setMiscReg().

clear()

void ArmISA::ISA::clear

(

)

Definition at line 126 of file isa.cc.

References clear32(), clear64(), FullSystem, ArmSystem::highestELIs64(), initID32(), initID64(), ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SEV_MAILBOX, ArmISA::MISCREG_TLBTR, miscRegs, MipsISA::p, params(), and system.

Referenced by assert64(), and ISA().

clear32()

void ArmISA::ISA::clear32 ( const ArmISAParams *  p, const SCTLR &  sctlr_rst  )

protected

Definition at line 213 of file isa.cc.

References FullSystem, haveLPAE, haveSecurity, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_MVBAR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_VBAR_S, miscRegs, ArmISA::MODE_USER, ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by assert64(), and clear().

clear64()

void ArmISA::ISA::clear64 ( const ArmISAParams *  p )

protected

Definition at line 265 of file isa.cc.

References ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, haveSecurity, haveVirtualization, ArmSystem::highestEL(), ArmISA::MISCREG_CPSR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_RVBAR_EL1, ArmISA::MISCREG_RVBAR_EL2, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, miscRegs, ArmISA::MODE_EL1H, ArmISA::MODE_EL2H, ArmISA::MODE_EL3H, panic, ArmSystem::resetAddr(), system, and updateRegMap().

Referenced by assert64(), and clear().

decoderFlavour()

Enums::DecoderFlavour ArmISA::ISA::decoderFlavour ( ) const

inline

Definition at line 748 of file isa.hh.

References _decoderFlavour.

flattenCCIndex()

int ArmISA::ISA::flattenCCIndex ( int  reg ) const

inline

Definition at line 567 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenFloatIndex()

int ArmISA::ISA::flattenFloatIndex ( int  reg ) const

inline

Definition at line 539 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenIntIndex()

int ArmISA::ISA::flattenIntIndex ( int  reg ) const

inline

Definition at line 507 of file isa.hh.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::flattenIntRegModeIndex(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::INTREG_SP3, ArmISA::INTREG_SPX, ArmISA::MISCREG_CPSR, ArmISA::NUM_ARCH_INTREGS, ArmISA::NUM_INTREGS, ArmISA::opModeToEL(), panic, and X86ISA::reg.

Referenced by flattenRegId().

flattenMiscIndex()

int ArmISA::ISA::flattenMiscIndex ( int  reg ) const

inline

Definition at line 574 of file isa.hh.

References ArmISA::inSecureState(), ArmISA::MISCREG_BANKED, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MUTEX, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NMRR_MAIR1, ArmISA::MISCREG_NMRR_MAIR1_NS, ArmISA::MISCREG_NMRR_MAIR1_S, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_PRRR_MAIR0, ArmISA::MISCREG_PRRR_MAIR0_NS, ArmISA::MISCREG_PRRR_MAIR0_S, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_HYP, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_MON, ArmISA::MISCREG_SPSR_SVC, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_TTBCR, ArmISA::miscRegInfo, ArmISA::MODE_ABORT, ArmISA::MODE_EL0T, ArmISA::MODE_EL1H, ArmISA::MODE_EL1T, ArmISA::MODE_EL2H, ArmISA::MODE_EL2T, ArmISA::MODE_EL3H, ArmISA::MODE_EL3T, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, panic, readMiscRegNoEffect(), X86ISA::reg, snsBankedIndex64(), and warn.

Referenced by flattenRegId(), and getMiscIndices().

flattenRegId()

RegId ArmISA::ISA::flattenRegId ( const RegId &  regId ) const

inline

Definition at line 483 of file isa.hh.

References CCRegClass, RegId::classValue(), RegId::elemIndex(), flattenCCIndex(), flattenFloatIndex(), flattenIntIndex(), flattenMiscIndex(), flattenVecElemIndex(), flattenVecIndex(), flattenVecPredIndex(), FloatRegClass, RegId::index(), IntRegClass, MiscRegClass, VecElemClass, VecPredRegClass, and VecRegClass.

flattenVecElemIndex()

int ArmISA::ISA::flattenVecElemIndex ( int  reg ) const

inline

Definition at line 553 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenVecIndex()

int ArmISA::ISA::flattenVecIndex ( int  reg ) const

inline

Definition at line 546 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

flattenVecPredIndex()

int ArmISA::ISA::flattenVecPredIndex ( int  reg ) const

inline

Definition at line 560 of file isa.hh.

References X86ISA::reg.

Referenced by flattenRegId().

getCurSveVecLenInBits()

unsigned ArmISA::ISA::getCurSveVecLenInBits

(

ThreadContext *

tc

)

const

Definition at line 2136 of file isa.cc.

References ArmISA::el, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIsInHost(), FullSystem, haveSecurity, haveVirtualization, ArmISA::inSecureState(), ArmISA::len, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, miscRegs, panic_if, and sveVL.

Referenced by ArmISA::ArmStaticInst::getCurSveVecLenInBits(), getMiscIndices(), and setMiscReg().

getCurSveVecLenInBitsAtReset()

unsigned ArmISA::ISA::getCurSveVecLenInBitsAtReset ( ) const

inline

Definition at line 725 of file isa.hh.

References zeroSveVecRegUpperPart().

Referenced by ArmISA::Decoder::Decoder().

getGenericTimer()

BaseISADevice & ArmISA::ISA::getGenericTimer ( ThreadContext *  tc )

protected

Definition at line 2108 of file isa.cc.

References ThreadContext::contextId(), ArmSystem::getGenericTimer(), panic, system, and timer.

Referenced by readMiscReg(), setMiscReg(), and updateRegMap().

getGICv3CPUInterface()

BaseISADevice & ArmISA::ISA::getGICv3CPUInterface ( ThreadContext *  tc )

protected

Definition at line 2129 of file isa.cc.

References gicv3CpuInterface, and panic_if.

Referenced by readMiscReg(), setMiscReg(), and updateRegMap().

getMiscIndices()

std::pair<int,int> ArmISA::ISA::getMiscIndices ( int  misc_reg ) const

inline

Definition at line 702 of file isa.hh.

References flattenMiscIndex(), getCurSveVecLenInBits(), ArmISA::inSecureState(), ArmISA::ISA::MiscRegLUTEntry::lower, ArmISA::MISCREG_BANKED_CHILD, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_SCR, ArmISA::miscRegInfo, and ArmISA::ISA::MiscRegLUTEntry::upper.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

haveGICv3CpuIfc()

bool ArmISA::ISA::haveGICv3CpuIfc ( ) const

inline

Getter for haveGICv3CPUInterface.

Definition at line 751 of file isa.hh.

References haveGICv3CPUInterface.

initializeMiscRegMetadata()

void ArmISA::ISA::initializeMiscRegMetadata ( )

protected

Some registers alias with others, and therefore need to be translated. When two mapping registers are given, they are the 32b lower and upper halves, respectively, of the 64b register being mapped. aligned with reference documentation ARM DDI 0487A.i pp 1540-1543

NAM = "not architecturally mandated", from ARM DDI 0487A.i, template text "AArch64 System register ___ can be mapped to AArch32 System register ___, but this is not architecturally mandated."

Definition at line 2891 of file miscregs.cc.

References ArmISA::EL1, ArmISA::EL2, FullSystem, ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_ACTLR_EL1, ArmISA::MISCREG_ACTLR_EL2, ArmISA::MISCREG_ACTLR_EL3, ArmISA::MISCREG_ACTLR_NS, ArmISA::MISCREG_ACTLR_S, ArmISA::MISCREG_ADFSR, ArmISA::MISCREG_ADFSR_NS, ArmISA::MISCREG_ADFSR_S, ArmISA::MISCREG_AFSR0_EL1, ArmISA::MISCREG_AFSR0_EL2, ArmISA::MISCREG_AFSR0_EL3, ArmISA::MISCREG_AFSR1_EL1, ArmISA::MISCREG_AFSR1_EL2, ArmISA::MISCREG_AFSR1_EL3, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_AIDR_EL1, ArmISA::MISCREG_AIFSR, ArmISA::MISCREG_AIFSR_NS, ArmISA::MISCREG_AIFSR_S, ArmISA::MISCREG_AMAIR0, ArmISA::MISCREG_AMAIR0_NS, ArmISA::MISCREG_AMAIR0_S, ArmISA::MISCREG_AMAIR1, ArmISA::MISCREG_AMAIR1_NS, ArmISA::MISCREG_AMAIR1_S, ArmISA::MISCREG_AMAIR_EL1, ArmISA::MISCREG_AMAIR_EL2, ArmISA::MISCREG_AMAIR_EL3, ArmISA::MISCREG_APDAKeyHi_EL1, ArmISA::MISCREG_APDAKeyLo_EL1, ArmISA::MISCREG_APDBKeyHi_EL1, ArmISA::MISCREG_APDBKeyLo_EL1, ArmISA::MISCREG_APGAKeyHi_EL1, ArmISA::MISCREG_APGAKeyLo_EL1, ArmISA::MISCREG_APIAKeyHi_EL1, ArmISA::MISCREG_APIAKeyLo_EL1, ArmISA::MISCREG_APIBKeyHi_EL1, ArmISA::MISCREG_APIBKeyLo_EL1, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_BPIALL, ArmISA::MISCREG_BPIALLIS, ArmISA::MISCREG_BPIMVA, ArmISA::MISCREG_CBAR, ArmISA::MISCREG_CBAR_EL1, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CCSIDR_EL1, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CLIDR_EL1, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTFRQ_EL0, ArmISA::MISCREG_CNTHCTL, ArmISA::MISCREG_CNTHCTL_EL2, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CTL_EL2, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTHP_CVAL_EL2, ArmISA::MISCREG_CNTHP_TVAL, ArmISA::MISCREG_CNTHP_TVAL_EL2, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTKCTL, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTP_CTL, ArmISA::MISCREG_CNTP_CTL_EL0, ArmISA::MISCREG_CNTP_CTL_NS, ArmISA::MISCREG_CNTP_CTL_S, ArmISA::MISCREG_CNTP_CVAL, ArmISA::MISCREG_CNTP_CVAL_EL0, ArmISA::MISCREG_CNTP_CVAL_NS, ArmISA::MISCREG_CNTP_CVAL_S, ArmISA::MISCREG_CNTP_TVAL, ArmISA::MISCREG_CNTP_TVAL_EL0, ArmISA::MISCREG_CNTP_TVAL_NS, ArmISA::MISCREG_CNTP_TVAL_S, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPCT_EL0, ArmISA::MISCREG_CNTPS_CTL_EL1, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTPS_TVAL_EL1, ArmISA::MISCREG_CNTV_CTL, ArmISA::MISCREG_CNTV_CTL_EL0, ArmISA::MISCREG_CNTV_CVAL, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTV_TVAL, ArmISA::MISCREG_CNTV_TVAL_EL0, ArmISA::MISCREG_CNTVCT, ArmISA::MISCREG_CNTVCT_EL0, ArmISA::MISCREG_CNTVOFF, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CONTEXTIDR_EL1, ArmISA::MISCREG_CONTEXTIDR_EL2, ArmISA::MISCREG_CONTEXTIDR_NS, ArmISA::MISCREG_CONTEXTIDR_S, ArmISA::MISCREG_CP14_UNIMPL, ArmISA::MISCREG_CP15_UNIMPL, ArmISA::MISCREG_CP15DMB, ArmISA::MISCREG_CP15DSB, ArmISA::MISCREG_CP15ISB, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_MODE, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CPUACTLR_EL1, ArmISA::MISCREG_CPUECTLR_EL1, ArmISA::MISCREG_CPUMERRSR, ArmISA::MISCREG_CPUMERRSR_EL1, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CSSELR_EL1, ArmISA::MISCREG_CSSELR_NS, ArmISA::MISCREG_CSSELR_S, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DACR, ArmISA::MISCREG_DACR32_EL2, ArmISA::MISCREG_DACR_NS, ArmISA::MISCREG_DACR_S, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGAUTHSTATUS, ArmISA::MISCREG_DBGAUTHSTATUS_EL1, ArmISA::MISCREG_DBGBCR0, ArmISA::MISCREG_DBGBCR0_EL1, ArmISA::MISCREG_DBGBCR1, ArmISA::MISCREG_DBGBCR1_EL1, ArmISA::MISCREG_DBGBCR2, ArmISA::MISCREG_DBGBCR2_EL1, ArmISA::MISCREG_DBGBCR3, ArmISA::MISCREG_DBGBCR3_EL1, ArmISA::MISCREG_DBGBCR4, ArmISA::MISCREG_DBGBCR4_EL1, ArmISA::MISCREG_DBGBCR5, ArmISA::MISCREG_DBGBCR5_EL1, ArmISA::MISCREG_DBGBVR0, ArmISA::MISCREG_DBGBVR0_EL1, ArmISA::MISCREG_DBGBVR1, ArmISA::MISCREG_DBGBVR1_EL1, ArmISA::MISCREG_DBGBVR2, ArmISA::MISCREG_DBGBVR2_EL1, ArmISA::MISCREG_DBGBVR3, ArmISA::MISCREG_DBGBVR3_EL1, ArmISA::MISCREG_DBGBVR4, ArmISA::MISCREG_DBGBVR4_EL1, ArmISA::MISCREG_DBGBVR5, ArmISA::MISCREG_DBGBVR5_EL1, ArmISA::MISCREG_DBGBXVR4, ArmISA::MISCREG_DBGBXVR5, ArmISA::MISCREG_DBGCLAIMCLR, ArmISA::MISCREG_DBGCLAIMCLR_EL1, ArmISA::MISCREG_DBGCLAIMSET, ArmISA::MISCREG_DBGCLAIMSET_EL1, ArmISA::MISCREG_DBGDCCINT, ArmISA::MISCREG_DBGDEVID0, ArmISA::MISCREG_DBGDEVID1, ArmISA::MISCREG_DBGDEVID2, ArmISA::MISCREG_DBGDIDR, ArmISA::MISCREG_DBGDRAR, ArmISA::MISCREG_DBGDSAR, ArmISA::MISCREG_DBGDSCRext, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DBGDTRRXext, ArmISA::MISCREG_DBGDTRRXint, ArmISA::MISCREG_DBGDTRTXext, ArmISA::MISCREG_DBGDTRTXint, ArmISA::MISCREG_DBGOSDLR, ArmISA::MISCREG_DBGOSECCR, ArmISA::MISCREG_DBGOSLAR, ArmISA::MISCREG_DBGOSLSR, ArmISA::MISCREG_DBGPRCR, ArmISA::MISCREG_DBGPRCR_EL1, ArmISA::MISCREG_DBGVCR, ArmISA::MISCREG_DBGVCR32_EL2, ArmISA::MISCREG_DBGWCR0, ArmISA::MISCREG_DBGWCR0_EL1, ArmISA::MISCREG_DBGWCR1, ArmISA::MISCREG_DBGWCR1_EL1, ArmISA::MISCREG_DBGWCR2, ArmISA::MISCREG_DBGWCR2_EL1, ArmISA::MISCREG_DBGWCR3, ArmISA::MISCREG_DBGWCR3_EL1, ArmISA::MISCREG_DBGWFAR, ArmISA::MISCREG_DBGWVR0, ArmISA::MISCREG_DBGWVR0_EL1, ArmISA::MISCREG_DBGWVR1, ArmISA::MISCREG_DBGWVR1_EL1, ArmISA::MISCREG_DBGWVR2, ArmISA::MISCREG_DBGWVR2_EL1, ArmISA::MISCREG_DBGWVR3, ArmISA::MISCREG_DBGWVR3_EL1, ArmISA::MISCREG_DC_CISW_Xt, ArmISA::MISCREG_DC_CIVAC_Xt, ArmISA::MISCREG_DC_CSW_Xt, ArmISA::MISCREG_DC_CVAC_Xt, ArmISA::MISCREG_DC_CVAU_Xt, ArmISA::MISCREG_DC_ISW_Xt, ArmISA::MISCREG_DC_IVAC_Xt, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DCCIMVAC, ArmISA::MISCREG_DCCISW, ArmISA::MISCREG_DCCMVAC, ArmISA::MISCREG_DCCMVAU, ArmISA::MISCREG_DCCSW, ArmISA::MISCREG_DCIMVAC, ArmISA::MISCREG_DCISW, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR, ArmISA::MISCREG_DFAR_NS, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_DFSR, ArmISA::MISCREG_DFSR_NS, ArmISA::MISCREG_DFSR_S, ArmISA::MISCREG_DISR_EL1, ArmISA::MISCREG_DL1DATA0, ArmISA::MISCREG_DL1DATA0_EL1, ArmISA::MISCREG_DL1DATA1, ArmISA::MISCREG_DL1DATA1_EL1, ArmISA::MISCREG_DL1DATA2, ArmISA::MISCREG_DL1DATA2_EL1, ArmISA::MISCREG_DL1DATA3, ArmISA::MISCREG_DL1DATA3_EL1, ArmISA::MISCREG_DL1DATA4, ArmISA::MISCREG_DL1DATA4_EL1, ArmISA::MISCREG_DLR_EL0, ArmISA::MISCREG_DSPSR_EL0, ArmISA::MISCREG_DTLBIALL, ArmISA::MISCREG_DTLBIASID, ArmISA::MISCREG_DTLBIMVA, ArmISA::MISCREG_ELR_EL1, ArmISA::MISCREG_ELR_EL2, ArmISA::MISCREG_ELR_EL3, ArmISA::MISCREG_ELR_HYP, ArmISA::MISCREG_ERRIDR_EL1, ArmISA::MISCREG_ERRSELR_EL1, ArmISA::MISCREG_ERXADDR_EL1, ArmISA::MISCREG_ERXCTLR_EL1, ArmISA::MISCREG_ERXFR_EL1, ArmISA::MISCREG_ERXMISC0_EL1, ArmISA::MISCREG_ERXMISC1_EL1, ArmISA::MISCREG_ERXSTATUS_EL1, ArmISA::MISCREG_ESR_EL1, ArmISA::MISCREG_ESR_EL2, ArmISA::MISCREG_ESR_EL3, ArmISA::MISCREG_FAR_EL1, ArmISA::MISCREG_FAR_EL2, ArmISA::MISCREG_FAR_EL3, ArmISA::MISCREG_FCSEIDR, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPEXC, ArmISA::MISCREG_FPEXC32_EL2, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HACR, ArmISA::MISCREG_HACR_EL2, ArmISA::MISCREG_HACTLR, ArmISA::MISCREG_HADFSR, ArmISA::MISCREG_HAIFSR, ArmISA::MISCREG_HAMAIR0, ArmISA::MISCREG_HAMAIR1, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDCR, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HMAIR0, ArmISA::MISCREG_HMAIR1, ArmISA::MISCREG_HPFAR, ArmISA::MISCREG_HPFAR_EL2, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_HSTR_EL2, ArmISA::MISCREG_HTCR, ArmISA::MISCREG_HTPIDR, ArmISA::MISCREG_HTTBR, ArmISA::MISCREG_HVBAR, ArmISA::MISCREG_IC_IALLU, ArmISA::MISCREG_IC_IALLUIS, ArmISA::MISCREG_IC_IVAU_Xt, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_AP0R0_EL1, ArmISA::MISCREG_ICC_AP0R1, ArmISA::MISCREG_ICC_AP0R1_EL1, ArmISA::MISCREG_ICC_AP0R2, ArmISA::MISCREG_ICC_AP0R2_EL1, ArmISA::MISCREG_ICC_AP0R3, ArmISA::MISCREG_ICC_AP0R3_EL1, ArmISA::MISCREG_ICC_AP1R0, ArmISA::MISCREG_ICC_AP1R0_EL1, ArmISA::MISCREG_ICC_AP1R0_EL1_NS, ArmISA::MISCREG_ICC_AP1R0_EL1_S, ArmISA::MISCREG_ICC_AP1R0_NS, ArmISA::MISCREG_ICC_AP1R0_S, ArmISA::MISCREG_ICC_AP1R1, ArmISA::MISCREG_ICC_AP1R1_EL1, ArmISA::MISCREG_ICC_AP1R1_EL1_NS, ArmISA::MISCREG_ICC_AP1R1_EL1_S, ArmISA::MISCREG_ICC_AP1R1_NS, ArmISA::MISCREG_ICC_AP1R1_S, ArmISA::MISCREG_ICC_AP1R2, ArmISA::MISCREG_ICC_AP1R2_EL1, ArmISA::MISCREG_ICC_AP1R2_EL1_NS, ArmISA::MISCREG_ICC_AP1R2_EL1_S, ArmISA::MISCREG_ICC_AP1R2_NS, ArmISA::MISCREG_ICC_AP1R2_S, ArmISA::MISCREG_ICC_AP1R3, ArmISA::MISCREG_ICC_AP1R3_EL1, ArmISA::MISCREG_ICC_AP1R3_EL1_NS, ArmISA::MISCREG_ICC_AP1R3_EL1_S, ArmISA::MISCREG_ICC_AP1R3_NS, ArmISA::MISCREG_ICC_AP1R3_S, ArmISA::MISCREG_ICC_ASGI1R, ArmISA::MISCREG_ICC_ASGI1R_EL1, ArmISA::MISCREG_ICC_BPR0, ArmISA::MISCREG_ICC_BPR0_EL1, ArmISA::MISCREG_ICC_BPR1, ArmISA::MISCREG_ICC_BPR1_EL1, ArmISA::MISCREG_ICC_BPR1_EL1_NS, ArmISA::MISCREG_ICC_BPR1_EL1_S, ArmISA::MISCREG_ICC_BPR1_NS, ArmISA::MISCREG_ICC_BPR1_S, ArmISA::MISCREG_ICC_CTLR, ArmISA::MISCREG_ICC_CTLR_EL1, ArmISA::MISCREG_ICC_CTLR_EL1_NS, ArmISA::MISCREG_ICC_CTLR_EL1_S, ArmISA::MISCREG_ICC_CTLR_EL3, ArmISA::MISCREG_ICC_CTLR_NS, ArmISA::MISCREG_ICC_CTLR_S, ArmISA::MISCREG_ICC_DIR, ArmISA::MISCREG_ICC_DIR_EL1, ArmISA::MISCREG_ICC_EOIR0, ArmISA::MISCREG_ICC_EOIR0_EL1, ArmISA::MISCREG_ICC_EOIR1, ArmISA::MISCREG_ICC_EOIR1_EL1, ArmISA::MISCREG_ICC_HPPIR0, ArmISA::MISCREG_ICC_HPPIR0_EL1, ArmISA::MISCREG_ICC_HPPIR1, ArmISA::MISCREG_ICC_HPPIR1_EL1, ArmISA::MISCREG_ICC_HSRE, ArmISA::MISCREG_ICC_IAR0, ArmISA::MISCREG_ICC_IAR0_EL1, ArmISA::MISCREG_ICC_IAR1, ArmISA::MISCREG_ICC_IAR1_EL1, ArmISA::MISCREG_ICC_IGRPEN0, ArmISA::MISCREG_ICC_IGRPEN0_EL1, ArmISA::MISCREG_ICC_IGRPEN1, ArmISA::MISCREG_ICC_IGRPEN1_EL1, ArmISA::MISCREG_ICC_IGRPEN1_EL1_NS, ArmISA::MISCREG_ICC_IGRPEN1_EL1_S, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_IGRPEN1_NS, ArmISA::MISCREG_ICC_IGRPEN1_S, ArmISA::MISCREG_ICC_MCTLR, ArmISA::MISCREG_ICC_MGRPEN1, ArmISA::MISCREG_ICC_MSRE, ArmISA::MISCREG_ICC_PMR, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICC_RPR, ArmISA::MISCREG_ICC_RPR_EL1, ArmISA::MISCREG_ICC_SGI0R, ArmISA::MISCREG_ICC_SGI0R_EL1, ArmISA::MISCREG_ICC_SGI1R, ArmISA::MISCREG_ICC_SGI1R_EL1, ArmISA::MISCREG_ICC_SRE, ArmISA::MISCREG_ICC_SRE_EL1, ArmISA::MISCREG_ICC_SRE_EL1_NS, ArmISA::MISCREG_ICC_SRE_EL1_S, ArmISA::MISCREG_ICC_SRE_EL2, ArmISA::MISCREG_ICC_SRE_EL3, ArmISA::MISCREG_ICC_SRE_NS, ArmISA::MISCREG_ICC_SRE_S, ArmISA::MISCREG_ICH_AP0R0, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_AP0R1, ArmISA::MISCREG_ICH_AP0R1_EL2, ArmISA::MISCREG_ICH_AP0R2, ArmISA::MISCREG_ICH_AP0R2_EL2, ArmISA::MISCREG_ICH_AP0R3, ArmISA::MISCREG_ICH_AP0R3_EL2, ArmISA::MISCREG_ICH_AP1R0, ArmISA::MISCREG_ICH_AP1R0_EL2, ArmISA::MISCREG_ICH_AP1R1, ArmISA::MISCREG_ICH_AP1R1_EL2, ArmISA::MISCREG_ICH_AP1R2, ArmISA::MISCREG_ICH_AP1R2_EL2, ArmISA::MISCREG_ICH_AP1R3, ArmISA::MISCREG_ICH_AP1R3_EL2, ArmISA::MISCREG_ICH_EISR, ArmISA::MISCREG_ICH_EISR_EL2, ArmISA::MISCREG_ICH_ELRSR, ArmISA::MISCREG_ICH_ELRSR_EL2, ArmISA::MISCREG_ICH_HCR, ArmISA::MISCREG_ICH_HCR_EL2, ArmISA::MISCREG_ICH_LR0, ArmISA::MISCREG_ICH_LR0_EL2, ArmISA::MISCREG_ICH_LR1, ArmISA::MISCREG_ICH_LR10, ArmISA::MISCREG_ICH_LR10_EL2, ArmISA::MISCREG_ICH_LR11, ArmISA::MISCREG_ICH_LR11_EL2, ArmISA::MISCREG_ICH_LR12, ArmISA::MISCREG_ICH_LR12_EL2, ArmISA::MISCREG_ICH_LR13, ArmISA::MISCREG_ICH_LR13_EL2, ArmISA::MISCREG_ICH_LR14, ArmISA::MISCREG_ICH_LR14_EL2, ArmISA::MISCREG_ICH_LR15, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LR1_EL2, ArmISA::MISCREG_ICH_LR2, ArmISA::MISCREG_ICH_LR2_EL2, ArmISA::MISCREG_ICH_LR3, ArmISA::MISCREG_ICH_LR3_EL2, ArmISA::MISCREG_ICH_LR4, ArmISA::MISCREG_ICH_LR4_EL2, ArmISA::MISCREG_ICH_LR5, ArmISA::MISCREG_ICH_LR5_EL2, ArmISA::MISCREG_ICH_LR6, ArmISA::MISCREG_ICH_LR6_EL2, ArmISA::MISCREG_ICH_LR7, ArmISA::MISCREG_ICH_LR7_EL2, ArmISA::MISCREG_ICH_LR8, ArmISA::MISCREG_ICH_LR8_EL2, ArmISA::MISCREG_ICH_LR9, ArmISA::MISCREG_ICH_LR9_EL2, ArmISA::MISCREG_ICH_LRC0, ArmISA::MISCREG_ICH_LRC1, ArmISA::MISCREG_ICH_LRC10, ArmISA::MISCREG_ICH_LRC11, ArmISA::MISCREG_ICH_LRC12, ArmISA::MISCREG_ICH_LRC13, ArmISA::MISCREG_ICH_LRC14, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ICH_LRC2, ArmISA::MISCREG_ICH_LRC3, ArmISA::MISCREG_ICH_LRC4, ArmISA::MISCREG_ICH_LRC5, ArmISA::MISCREG_ICH_LRC6, ArmISA::MISCREG_ICH_LRC7, ArmISA::MISCREG_ICH_LRC8, ArmISA::MISCREG_ICH_LRC9, ArmISA::MISCREG_ICH_MISR, ArmISA::MISCREG_ICH_MISR_EL2, ArmISA::MISCREG_ICH_VMCR, ArmISA::MISCREG_ICH_VMCR_EL2, ArmISA::MISCREG_ICH_VTR, ArmISA::MISCREG_ICH_VTR_EL2, ArmISA::MISCREG_ICIALLU, ArmISA::MISCREG_ICIALLUIS, ArmISA::MISCREG_ICIMVAU, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AA64ZFR0_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_AFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR0_EL1, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR1_EL1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR2_EL1, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR3_EL1, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR4_EL1, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_ISAR5_EL1, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR0_EL1, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR1_EL1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR2_EL1, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_MMFR3_EL1, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR0_EL1, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_ID_PFR1_EL1, ArmISA::MISCREG_IFAR, ArmISA::MISCREG_IFAR_NS, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IFSR, ArmISA::MISCREG_IFSR32_EL2, ArmISA::MISCREG_IFSR_NS, ArmISA::MISCREG_IFSR_S, ArmISA::MISCREG_IL1DATA0, ArmISA::MISCREG_IL1DATA0_EL1, ArmISA::MISCREG_IL1DATA1, ArmISA::MISCREG_IL1DATA1_EL1, ArmISA::MISCREG_IL1DATA2, ArmISA::MISCREG_IL1DATA2_EL1, ArmISA::MISCREG_IL1DATA3, ArmISA::MISCREG_IL1DATA3_EL1, ArmISA::MISCREG_IMPDEF_UNIMPL, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_ITLBIALL, ArmISA::MISCREG_ITLBIASID, ArmISA::MISCREG_ITLBIMVA, ArmISA::MISCREG_JIDR, ArmISA::MISCREG_JMCR, ArmISA::MISCREG_JOSCR, ArmISA::MISCREG_L2ACTLR, ArmISA::MISCREG_L2ACTLR_EL1, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_L2CTLR_EL1, ArmISA::MISCREG_L2ECTLR, ArmISA::MISCREG_L2ECTLR_EL1, ArmISA::MISCREG_L2MERRSR, ArmISA::MISCREG_L2MERRSR_EL1, ArmISA::MISCREG_LOCKADDR, ArmISA::MISCREG_LOCKFLAG, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR0_NS, ArmISA::MISCREG_MAIR0_S, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MAIR1_NS, ArmISA::MISCREG_MAIR1_S, ArmISA::MISCREG_MAIR_EL1, ArmISA::MISCREG_MAIR_EL2, ArmISA::MISCREG_MAIR_EL3, ArmISA::MISCREG_MDCCINT_EL1, ArmISA::MISCREG_MDCCSR_EL0, ArmISA::MISCREG_MDCR_EL2, ArmISA::MISCREG_MDCR_EL3, ArmISA::MISCREG_MDDTR_EL0, ArmISA::MISCREG_MDDTRRX_EL0, ArmISA::MISCREG_MDDTRTX_EL0, ArmISA::MISCREG_MDRAR_EL1, ArmISA::MISCREG_MDSCR_EL1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_MVBAR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR0_EL1, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_MVFR1_EL1, ArmISA::MISCREG_MVFR2_EL1, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NMRR_MAIR1, ArmISA::MISCREG_NMRR_MAIR1_NS, ArmISA::MISCREG_NMRR_MAIR1_S, ArmISA::MISCREG_NMRR_NS, ArmISA::MISCREG_NMRR_S, ArmISA::MISCREG_NOP, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_OSDLR_EL1, ArmISA::MISCREG_OSDTRRX_EL1, ArmISA::MISCREG_OSDTRTX_EL1, ArmISA::MISCREG_OSECCR_EL1, ArmISA::MISCREG_OSLAR_EL1, ArmISA::MISCREG_OSLSR_EL1, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PAR, ArmISA::MISCREG_PAR_EL1, ArmISA::MISCREG_PAR_NS, ArmISA::MISCREG_PAR_S, ArmISA::MISCREG_PMCCFILTR, ArmISA::MISCREG_PMCCFILTR_EL0, ArmISA::MISCREG_PMCCNTR, ArmISA::MISCREG_PMCCNTR_EL0, ArmISA::MISCREG_PMCEID0, ArmISA::MISCREG_PMCEID0_EL0, ArmISA::MISCREG_PMCEID1, ArmISA::MISCREG_PMCEID1_EL0, ArmISA::MISCREG_PMCNTENCLR, ArmISA::MISCREG_PMCNTENCLR_EL0, ArmISA::MISCREG_PMCNTENSET, ArmISA::MISCREG_PMCNTENSET_EL0, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMCR_EL0, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVCNTR1_EL0, ArmISA::MISCREG_PMEVCNTR2_EL0, ArmISA::MISCREG_PMEVCNTR3_EL0, ArmISA::MISCREG_PMEVCNTR4_EL0, ArmISA::MISCREG_PMEVCNTR5_EL0, ArmISA::MISCREG_PMEVTYPER0_EL0, ArmISA::MISCREG_PMEVTYPER1_EL0, ArmISA::MISCREG_PMEVTYPER2_EL0, ArmISA::MISCREG_PMEVTYPER3_EL0, ArmISA::MISCREG_PMEVTYPER4_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENCLR, ArmISA::MISCREG_PMINTENCLR_EL1, ArmISA::MISCREG_PMINTENSET, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSCLR_EL0, ArmISA::MISCREG_PMOVSR, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMSELR, ArmISA::MISCREG_PMSELR_EL0, ArmISA::MISCREG_PMSWINC, ArmISA::MISCREG_PMSWINC_EL0, ArmISA::MISCREG_PMUSERENR, ArmISA::MISCREG_PMUSERENR_EL0, ArmISA::MISCREG_PMXEVCNTR, ArmISA::MISCREG_PMXEVCNTR_EL0, ArmISA::MISCREG_PMXEVTYPER, ArmISA::MISCREG_PMXEVTYPER_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_PRRR_MAIR0, ArmISA::MISCREG_PRRR_MAIR0_NS, ArmISA::MISCREG_PRRR_MAIR0_S, ArmISA::MISCREG_PRRR_NS, ArmISA::MISCREG_PRRR_S, ArmISA::MISCREG_RAMINDEX, ArmISA::MISCREG_RAZ, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_REVIDR_EL1, ArmISA::MISCREG_RMR, ArmISA::MISCREG_RMR_EL3, ArmISA::MISCREG_RVBAR_EL1, ArmISA::MISCREG_RVBAR_EL2, ArmISA::MISCREG_RVBAR_EL3, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_RST, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SDER, ArmISA::MISCREG_SDER32_EL3, ArmISA::MISCREG_SEV_MAILBOX, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_SPSR, ArmISA::MISCREG_SPSR_ABT, ArmISA::MISCREG_SPSR_ABT_AA64, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_SPSR_FIQ, ArmISA::MISCREG_SPSR_FIQ_AA64, ArmISA::MISCREG_SPSR_HYP, ArmISA::MISCREG_SPSR_IRQ, ArmISA::MISCREG_SPSR_IRQ_AA64, ArmISA::MISCREG_SPSR_MON, ArmISA::MISCREG_SPSR_SVC, ArmISA::MISCREG_SPSR_UND, ArmISA::MISCREG_SPSR_UND_AA64, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TEECR, ArmISA::MISCREG_TEECR32_EL1, ArmISA::MISCREG_TEEHBR, ArmISA::MISCREG_TEEHBR32_EL1, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE2, ArmISA::MISCREG_TLBI_ALLE2IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBIALL, ArmISA::MISCREG_TLBIALLH, ArmISA::MISCREG_TLBIALLHIS, ArmISA::MISCREG_TLBIALLIS, ArmISA::MISCREG_TLBIALLNSNH, ArmISA::MISCREG_TLBIALLNSNHIS, ArmISA::MISCREG_TLBIASID, ArmISA::MISCREG_TLBIASIDIS, ArmISA::MISCREG_TLBIIPAS2, ArmISA::MISCREG_TLBIIPAS2IS, ArmISA::MISCREG_TLBIIPAS2L, ArmISA::MISCREG_TLBIIPAS2LIS, ArmISA::MISCREG_TLBIMVA, ArmISA::MISCREG_TLBIMVAA, ArmISA::MISCREG_TLBIMVAAIS, ArmISA::MISCREG_TLBIMVAAL, ArmISA::MISCREG_TLBIMVAALIS, ArmISA::MISCREG_TLBIMVAH, ArmISA::MISCREG_TLBIMVAHIS, ArmISA::MISCREG_TLBIMVAIS, ArmISA::MISCREG_TLBIMVAL, ArmISA::MISCREG_TLBIMVALH, ArmISA::MISCREG_TLBIMVALHIS, ArmISA::MISCREG_TLBIMVALIS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TPIDR_EL0, ArmISA::MISCREG_TPIDR_EL1, ArmISA::MISCREG_TPIDR_EL2, ArmISA::MISCREG_TPIDR_EL3, ArmISA::MISCREG_TPIDRPRW, ArmISA::MISCREG_TPIDRPRW_NS, ArmISA::MISCREG_TPIDRPRW_S, ArmISA::MISCREG_TPIDRRO_EL0, ArmISA::MISCREG_TPIDRURO, ArmISA::MISCREG_TPIDRURO_NS, ArmISA::MISCREG_TPIDRURO_S, ArmISA::MISCREG_TPIDRURW, ArmISA::MISCREG_TPIDRURW_NS, ArmISA::MISCREG_TPIDRURW_S, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBCR_NS, ArmISA::MISCREG_TTBCR_S, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR0_NS, ArmISA::MISCREG_TTBR0_S, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_TTBR1_NS, ArmISA::MISCREG_TTBR1_S, ArmISA::MISCREG_UNKNOWN, ArmISA::MISCREG_VBAR, ArmISA::MISCREG_VBAR_EL1, ArmISA::MISCREG_VBAR_EL2, ArmISA::MISCREG_VBAR_EL3, ArmISA::MISCREG_VBAR_NS, ArmISA::MISCREG_VBAR_S, ArmISA::MISCREG_VDISR_EL2, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VMPIDR_EL2, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_VPIDR_EL2, ArmISA::MISCREG_VSESR_EL2, ArmISA::MISCREG_VTCR, ArmISA::MISCREG_VTCR_EL2, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_VTTBR_EL2, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL12, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, and X86ISA::system.

Referenced by InitReg(), and ISA().

initID32()

void ArmISA::ISA::initID32 ( const ArmISAParams *  p )

protected

Definition at line 314 of file isa.cc.

References haveCrypto, highestELIs64, insertBits(), ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MIDR_EL1, ArmISA::MISCREG_VPIDR, and miscRegs.

Referenced by assert64(), and clear().

initID64()

void ArmISA::ISA::initID64 ( const ArmISAParams *  p )

protected

Definition at line 350 of file isa.cc.

References ArmISA::encodePhysAddrRange64(), haveCrypto, haveLargeAsid64, haveLSE, havePAN, haveSecurity, haveSVE, haveVirtualization, insertBits(), ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64ZFR0_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_DFR0_EL1, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, miscRegs, physAddrRange, sveVL, and ULL.

Referenced by assert64(), and clear().

InitReg()

const MiscRegLUTEntryInitializer ArmISA::ISA::InitReg ( uint32_t  reg )

inlineprotected

Definition at line 404 of file isa.hh.

References initializeMiscRegMetadata(), and ArmISA::miscRegInfo.

params()

const ArmISAParams * ArmISA::ISA::params

(

)

const

Definition at line 120 of file isa.cc.

References SimObject::_params.

Referenced by clear().

readMiscReg()

RegVal ArmISA::ISA::readMiscReg	(	int	misc_reg,
		ThreadContext *	tc
	)

Definition at line 461 of file isa.cc.

References System::cacheLineSize(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ArmISA::daif, DPRINTF, ArmISA::EL3, ArmISA::ELIs32(), ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, ThreadContext::getCpuPtr(), ArmSystem::getGenericTimer(), getGenericTimer(), getGICv3CPUInterface(), BaseCPU::getInterruptController(), ThreadContext::getSystemPtr(), haveGICv3CPUInterface, haveSecurity, haveSVE, haveVirtualization, iGbReg::TxdOp::ic(), ArmISA::inSecureState(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::mask, ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AIDR, ArmISA::MISCREG_CCSIDR, ArmISA::MISCREG_CLIDR, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CTR, ArmISA::MISCREG_CTR_EL0, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DBGDIDR, ArmISA::MISCREG_DBGDSCRint, ArmISA::MISCREG_DCZID_EL0, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_AFR0, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ISR, ArmISA::MISCREG_ISR_EL1, ArmISA::MISCREG_JIDR, ArmISA::MISCREG_JMCR, ArmISA::MISCREG_JOSCR, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MPIDR_EL1, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_REVIDR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_TCMTR, ArmISA::MISCREG_VMPIDR, ArmISA::MISCREG_VMPIDR_EL2, ArmISA::MISCREG_VPIDR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::MODE_HYP, ArmISA::MODE_MON, System::numContexts(), panic, MipsISA::pc, ThreadContext::pcState(), pmu, ThreadContext::readCCReg(), ThreadContext::readIntReg(), ArmISA::BaseISADevice::readMiscReg(), readMiscRegNoEffect(), ArmISA::readMPIDR(), system, ThreadContext::threadId(), ArmISA::unflattenMiscReg(), X86ISA::val, warn, and warn_once.

Referenced by assert32(), assert64(), and setMiscReg().

readMiscRegNoEffect()

RegVal ArmISA::ISA::readMiscRegNoEffect

(

int

misc_reg

)

const

Definition at line 437 of file isa.cc.

References DPRINTF, getMiscIndices(), lookUpMiscReg, ArmISA::mask, ArmISA::miscRegName, miscRegs, ArmISA::NumMiscRegs, X86ISA::reg, and X86ISA::val.

Referenced by assert64(), Gicv3CPUInterface::bpr1(), Gicv3CPUInterface::currEL(), Gicv3CPUInterface::dropPriority(), Gicv3CPUInterface::eoiMaintenanceInterruptStatus(), flattenMiscIndex(), Gicv3CPUInterface::generateSGI(), Gicv3CPUInterface::getHCREL2FMO(), Gicv3CPUInterface::getHCREL2IMO(), Gicv3CPUInterface::getHPPIR1(), Gicv3CPUInterface::getHPPVILR(), Gicv3CPUInterface::groupEnabled(), Gicv3CPUInterface::groupPriorityMask(), Gicv3CPUInterface::highestActiveGroup(), Gicv3CPUInterface::highestActivePriority(), Gicv3CPUInterface::hppiCanPreempt(), Gicv3CPUInterface::hppviCanPreempt(), Gicv3CPUInterface::inSecureState(), Gicv3CPUInterface::isAA64(), Gicv3CPUInterface::isEL3OrMon(), Gicv3CPUInterface::isEOISplitMode(), Gicv3CPUInterface::isSecureBelowEL3(), Gicv3CPUInterface::maintenanceInterruptStatus(), Gicv3CPUInterface::readBankedMiscReg(), Gicv3CPUInterface::readMiscReg(), readMiscReg(), Gicv3CPUInterface::setMiscReg(), setMiscReg(), Gicv3CPUInterface::virtualActivateIRQ(), Gicv3CPUInterface::virtualDeactivateIRQ(), Gicv3CPUInterface::virtualDropPriority(), Gicv3CPUInterface::virtualFindActive(), Gicv3CPUInterface::virtualGroupPriorityMask(), Gicv3CPUInterface::virtualHighestActivePriority(), Gicv3CPUInterface::virtualIncrementEOICount(), Gicv3CPUInterface::virtualIsEOISplitMode(), and Gicv3CPUInterface::virtualUpdate().

serialize()

void ArmISA::ISA::serialize ( CheckpointOut &  cp ) const

inlinevirtual

Serialize an object.

Output an object's state into the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 731 of file isa.hh.

References DPRINTF, ArmISA::NUM_PHYS_MISCREGS, and SERIALIZE_ARRAY.

setMiscReg()

void ArmISA::ISA::setMiscReg	(	int	misc_reg,
		RegVal	val,
		ThreadContext *	tc
	)

Definition at line 790 of file isa.cc.

References ArmISA::asid, assert32(), assert64(), ArmISA::attr, bits(), ArmISA::TLBIOp::broadcast(), ArmISA::CCREG_C, ArmISA::CCREG_NZ, ArmISA::CCREG_V, ThreadContext::contextId(), ArmISA::CpsrMaskQ, ArmISA::daif, DPRINTF, ArmISA::el, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs32(), ArmISA::FpscrExcMask, ArmISA::FpscrQcMask, Request::funcMasterId, ArmISA::TLB::getAttr(), ThreadContext::getCheckerCpuPtr(), getCurSveVecLenInBits(), ThreadContext::getDecoderPtr(), ArmISA::getDTBPtr(), ArmISA::ArmFault::getFsr(), getGenericTimer(), getGICv3CPUInterface(), ArmISA::getITBPtr(), haveLargeAsid64, haveLPAE, havePAN, haveSecurity, haveSVE, haveVirtualization, highestELIs64, ArmISA::TLB::HypMode, ArmISA::inSecureState(), ArmISA::INTREG_SP0, ArmISA::INTREG_SP1, ArmISA::INTREG_SP2, ArmISA::TLB::invalidateMiscReg(), ArmISA::ArmFault::iss(), ArmISA::ArmFault::isStage2(), ArmISA::mask, mbits(), ArmISA::MISCREG_ACTLR, ArmISA::MISCREG_AMAIR0, ArmISA::MISCREG_AMAIR1, ArmISA::MISCREG_AT_S12E0R_Xt, ArmISA::MISCREG_AT_S12E0W_Xt, ArmISA::MISCREG_AT_S12E1R_Xt, ArmISA::MISCREG_AT_S12E1W_Xt, ArmISA::MISCREG_AT_S1E0R_Xt, ArmISA::MISCREG_AT_S1E0W_Xt, ArmISA::MISCREG_AT_S1E1R_Xt, ArmISA::MISCREG_AT_S1E1W_Xt, ArmISA::MISCREG_AT_S1E2R_Xt, ArmISA::MISCREG_AT_S1E2W_Xt, ArmISA::MISCREG_AT_S1E3R_Xt, ArmISA::MISCREG_AT_S1E3W_Xt, ArmISA::MISCREG_ATS12NSOPR, ArmISA::MISCREG_ATS12NSOPW, ArmISA::MISCREG_ATS12NSOUR, ArmISA::MISCREG_ATS12NSOUW, ArmISA::MISCREG_ATS1CPR, ArmISA::MISCREG_ATS1CPW, ArmISA::MISCREG_ATS1CUR, ArmISA::MISCREG_ATS1CUW, ArmISA::MISCREG_ATS1HR, ArmISA::MISCREG_ATS1HW, ArmISA::MISCREG_CNTFRQ, ArmISA::MISCREG_CNTHP_CTL, ArmISA::MISCREG_CNTHP_CVAL, ArmISA::MISCREG_CNTHV_CTL_EL2, ArmISA::MISCREG_CNTHV_CVAL_EL2, ArmISA::MISCREG_CNTHV_TVAL_EL2, ArmISA::MISCREG_CNTKCTL_EL1, ArmISA::MISCREG_CNTPCT, ArmISA::MISCREG_CNTPS_CVAL_EL1, ArmISA::MISCREG_CNTV_CVAL_EL0, ArmISA::MISCREG_CNTVOFF_EL2, ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CPACR, ArmISA::MISCREG_CPACR_EL1, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_CPSR_Q, ArmISA::MISCREG_CPTR_EL2, ArmISA::MISCREG_CPTR_EL3, ArmISA::MISCREG_CSSELR, ArmISA::MISCREG_CURRENTEL, ArmISA::MISCREG_DACR, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_DC_ZVA_Xt, ArmISA::MISCREG_DFAR_S, ArmISA::MISCREG_DFSR, ArmISA::MISCREG_DTLBIALL, ArmISA::MISCREG_DTLBIASID, ArmISA::MISCREG_DTLBIMVA, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPEXC, ArmISA::MISCREG_FPSCR, ArmISA::MISCREG_FPSCR_EXC, ArmISA::MISCREG_FPSCR_QC, ArmISA::MISCREG_FPSID, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_HCPTR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR2, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HDFAR, ArmISA::MISCREG_HIFAR, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_HSTR, ArmISA::MISCREG_ICC_AP0R0, ArmISA::MISCREG_ICC_IGRPEN1_EL3, ArmISA::MISCREG_ICC_PMR_EL1, ArmISA::MISCREG_ICH_AP0R0_EL2, ArmISA::MISCREG_ICH_LR15_EL2, ArmISA::MISCREG_ICH_LRC15, ArmISA::MISCREG_ID_AA64AFR0_EL1, ArmISA::MISCREG_ID_AA64AFR1_EL1, ArmISA::MISCREG_ID_AA64DFR0_EL1, ArmISA::MISCREG_ID_AA64DFR1_EL1, ArmISA::MISCREG_ID_AA64ISAR0_EL1, ArmISA::MISCREG_ID_AA64ISAR1_EL1, ArmISA::MISCREG_ID_AA64MMFR0_EL1, ArmISA::MISCREG_ID_AA64MMFR1_EL1, ArmISA::MISCREG_ID_AA64MMFR2_EL1, ArmISA::MISCREG_ID_AA64PFR0_EL1, ArmISA::MISCREG_ID_AA64PFR1_EL1, ArmISA::MISCREG_ID_DFR0, ArmISA::MISCREG_ID_ISAR0, ArmISA::MISCREG_ID_ISAR1, ArmISA::MISCREG_ID_ISAR2, ArmISA::MISCREG_ID_ISAR3, ArmISA::MISCREG_ID_ISAR4, ArmISA::MISCREG_ID_ISAR5, ArmISA::MISCREG_ID_MMFR0, ArmISA::MISCREG_ID_MMFR1, ArmISA::MISCREG_ID_MMFR2, ArmISA::MISCREG_ID_MMFR3, ArmISA::MISCREG_ID_PFR0, ArmISA::MISCREG_ID_PFR1, ArmISA::MISCREG_IFAR_S, ArmISA::MISCREG_IFSR, ArmISA::MISCREG_IMPLEMENTED, ArmISA::MISCREG_ITLBIALL, ArmISA::MISCREG_ITLBIASID, ArmISA::MISCREG_ITLBIMVA, ArmISA::MISCREG_L2CTLR, ArmISA::MISCREG_MAIR0, ArmISA::MISCREG_MAIR1, ArmISA::MISCREG_MIDR, ArmISA::MISCREG_MPIDR, ArmISA::MISCREG_MVFR0, ArmISA::MISCREG_MVFR1, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_NSACR, ArmISA::MISCREG_NZCV, ArmISA::MISCREG_PAN, ArmISA::MISCREG_PAR, ArmISA::MISCREG_PAR_EL1, ArmISA::MISCREG_PMCR, ArmISA::MISCREG_PMEVCNTR0_EL0, ArmISA::MISCREG_PMEVTYPER5_EL0, ArmISA::MISCREG_PMINTENSET_EL1, ArmISA::MISCREG_PMOVSSET, ArmISA::MISCREG_PMOVSSET_EL0, ArmISA::MISCREG_PMXEVTYPER_PMCCFILTR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_SCTLR_NS, ArmISA::MISCREG_SCTLR_S, ArmISA::MISCREG_SP_EL0, ArmISA::MISCREG_SP_EL1, ArmISA::MISCREG_SP_EL2, ArmISA::MISCREG_SPSEL, ArmISA::MISCREG_SPSR_EL1, ArmISA::MISCREG_SPSR_EL2, ArmISA::MISCREG_SPSR_EL3, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TLBI_ALLE1, ArmISA::MISCREG_TLBI_ALLE1IS, ArmISA::MISCREG_TLBI_ALLE2, ArmISA::MISCREG_TLBI_ALLE2IS, ArmISA::MISCREG_TLBI_ALLE3, ArmISA::MISCREG_TLBI_ALLE3IS, ArmISA::MISCREG_TLBI_ASIDE1_Xt, ArmISA::MISCREG_TLBI_ASIDE1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2E1_Xt, ArmISA::MISCREG_TLBI_IPAS2E1IS_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1_Xt, ArmISA::MISCREG_TLBI_IPAS2LE1IS_Xt, ArmISA::MISCREG_TLBI_VAAE1_Xt, ArmISA::MISCREG_TLBI_VAAE1IS_Xt, ArmISA::MISCREG_TLBI_VAALE1_Xt, ArmISA::MISCREG_TLBI_VAALE1IS_Xt, ArmISA::MISCREG_TLBI_VAE1_Xt, ArmISA::MISCREG_TLBI_VAE1IS_Xt, ArmISA::MISCREG_TLBI_VAE2_Xt, ArmISA::MISCREG_TLBI_VAE2IS_Xt, ArmISA::MISCREG_TLBI_VAE3_Xt, ArmISA::MISCREG_TLBI_VAE3IS_Xt, ArmISA::MISCREG_TLBI_VALE1_Xt, ArmISA::MISCREG_TLBI_VALE1IS_Xt, ArmISA::MISCREG_TLBI_VALE2_Xt, ArmISA::MISCREG_TLBI_VALE2IS_Xt, ArmISA::MISCREG_TLBI_VALE3_Xt, ArmISA::MISCREG_TLBI_VALE3IS_Xt, ArmISA::MISCREG_TLBI_VMALLE1, ArmISA::MISCREG_TLBI_VMALLE1IS, ArmISA::MISCREG_TLBI_VMALLS12E1, ArmISA::MISCREG_TLBI_VMALLS12E1IS, ArmISA::MISCREG_TLBIALL, ArmISA::MISCREG_TLBIALLH, ArmISA::MISCREG_TLBIALLHIS, ArmISA::MISCREG_TLBIALLIS, ArmISA::MISCREG_TLBIALLNSNH, ArmISA::MISCREG_TLBIALLNSNHIS, ArmISA::MISCREG_TLBIASID, ArmISA::MISCREG_TLBIASIDIS, ArmISA::MISCREG_TLBIIPAS2, ArmISA::MISCREG_TLBIIPAS2IS, ArmISA::MISCREG_TLBIIPAS2L, ArmISA::MISCREG_TLBIIPAS2LIS, ArmISA::MISCREG_TLBIMVA, ArmISA::MISCREG_TLBIMVAA, ArmISA::MISCREG_TLBIMVAAIS, ArmISA::MISCREG_TLBIMVAAL, ArmISA::MISCREG_TLBIMVAALIS, ArmISA::MISCREG_TLBIMVAH, ArmISA::MISCREG_TLBIMVAHIS, ArmISA::MISCREG_TLBIMVAIS, ArmISA::MISCREG_TLBIMVAL, ArmISA::MISCREG_TLBIMVALH, ArmISA::MISCREG_TLBIMVALHIS, ArmISA::MISCREG_TLBIMVALIS, ArmISA::MISCREG_TLBTR, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR0_EL2, ArmISA::MISCREG_TTBR0_EL3, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_TTBR1_EL2, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_WARN_NOT_FAIL, ArmISA::MISCREG_ZCR_EL1, ArmISA::MISCREG_ZCR_EL2, ArmISA::MISCREG_ZCR_EL3, ArmISA::miscRegInfo, ArmISA::miscRegName, miscRegs, ArmISA::mode, ArmISA::MODE_MON, ArmISA::TLB::MustBeOne, NoFault, ArmISA::TLB::NormalTran, ArmISA::pan, panic, MipsISA::pc, ThreadContext::pcState(), ThreadContext::pcStateNoRecord(), pmu, BaseTLB::Read, ThreadContext::readMiscReg(), readMiscReg(), readMiscRegNoEffect(), ArmISA::TLB::S12E0Tran, ArmISA::TLB::S12E1Tran, ArmISA::TLB::S1CTran, ArmISA::TLB::S1E0Tran, ArmISA::TLB::S1E1Tran, ArmISA::TLB::S1E2Tran, ArmISA::TLB::S1E3Tran, ArmISA::TLB::S1S2NsTran, ThreadContext::setCCReg(), ThreadContext::setIntReg(), ArmISA::BaseISADevice::setMiscReg(), setMiscRegNoEffect(), ArmISA::sp, ArmISA::TLB::translateFunctional(), ArmISA::unflattenMiscReg(), ArmISA::ArmFault::update(), updateRegMap(), ArmISA::TLB::UserMode, X86ISA::val, warn, warn_once, and BaseTLB::Write.

Referenced by assert64().

setMiscRegNoEffect()

void ArmISA::ISA::setMiscRegNoEffect	(	int	misc_reg,
		RegVal	val
	)

Definition at line 768 of file isa.cc.

References bits(), DPRINTF, getMiscIndices(), lookUpMiscReg, miscRegs, ArmISA::NumMiscRegs, X86ISA::reg, and ArmISA::v.

Referenced by assert64(), Gicv3CPUInterface::dropPriority(), Gicv3CPUInterface::generateSGI(), Gicv3CPUInterface::readMiscReg(), Gicv3CPUInterface::setBankedMiscReg(), Gicv3CPUInterface::setMiscReg(), setMiscReg(), Gicv3CPUInterface::virtualActivateIRQ(), Gicv3CPUInterface::virtualDeactivateIRQ(), Gicv3CPUInterface::virtualDropPriority(), and Gicv3CPUInterface::virtualIncrementEOICount().

snsBankedIndex64()

int ArmISA::ISA::snsBankedIndex64 ( MiscRegIndex  reg, bool  ns  ) const

inline

Definition at line 693 of file isa.hh.

References ArmISA::MISCREG_BANKED64, ArmISA::miscRegInfo, ArmISA::ns, and X86ISA::reg.

Referenced by flattenMiscIndex(), Gicv3CPUInterface::readBankedMiscReg(), and Gicv3CPUInterface::setBankedMiscReg().

startup()

void ArmISA::ISA::startup

(

ThreadContext *

tc

)

Definition at line 418 of file isa.cc.

References afterStartup, ThreadContext::contextId(), Gicv3::getCPUInterface(), ArmSystem::getGIC(), gicv3CpuInterface, haveGICv3CPUInterface, pmu, ArmISA::BaseISADevice::setThreadContext(), and system.

unserialize()

void ArmISA::ISA::unserialize ( CheckpointIn &  cp )

inlinevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters

cp	Checkpoint state

Implements Serializable.

Definition at line 738 of file isa.hh.

References DPRINTF, ArmISA::MISCREG_CPSR, ArmISA::NUM_PHYS_MISCREGS, SimObject::startup(), UNSERIALIZE_ARRAY, and updateRegMap().

updateRegMap()

void ArmISA::ISA::updateRegMap ( CPSR  cpsr )

inlineprotected

Definition at line 415 of file isa.hh.

References getGenericTimer(), getGICv3CPUInterface(), ArmISA::IntReg64Map, ArmISA::IntRegAbtMap, ArmISA::IntRegFiqMap, ArmISA::IntRegHypMap, ArmISA::IntRegIrqMap, ArmISA::IntRegMonMap, ArmISA::IntRegSvcMap, ArmISA::IntRegUndMap, ArmISA::IntRegUsrMap, ArmISA::MODE_ABORT, ArmISA::MODE_FIQ, ArmISA::MODE_HYP, ArmISA::MODE_IRQ, ArmISA::MODE_MON, ArmISA::MODE_SVC, ArmISA::MODE_SYSTEM, ArmISA::MODE_UNDEFINED, ArmISA::MODE_USER, and panic.

Referenced by clear32(), clear64(), setMiscReg(), and unserialize().

vecRegRenameMode()

Enums::VecRegRenameMode ArmISA::ISA::vecRegRenameMode ( ) const

inline

Definition at line 761 of file isa.hh.

References _vecRegRenameMode, and SimObject::startup().

Referenced by RenameMode< ArmISA::ISA >::init().

zeroSveVecRegUpperPart()

void ArmISA::ISA::zeroSveVecRegUpperPart ( VecRegContainer &  vc, unsigned  eCount  )

static

Definition at line 2180 of file isa.cc.

References VecRegContainer< Sz >::as(), and ArmISA::i.

Referenced by getCurSveVecLenInBitsAtReset().

Member Data Documentation

_decoderFlavour

const Enums::DecoderFlavour ArmISA::ISA::_decoderFlavour

protected

Definition at line 74 of file isa.hh.

Referenced by decoderFlavour().

_vecRegRenameMode

const Enums::VecRegRenameMode ArmISA::ISA::_vecRegRenameMode

protected

Definition at line 75 of file isa.hh.

Referenced by ISA(), and vecRegRenameMode().

afterStartup

bool ArmISA::ISA::afterStartup

protected

Definition at line 111 of file isa.hh.

Referenced by startup().

dummyDevice

DummyISADevice ArmISA::ISA::dummyDevice

protected

Dummy device for to handle non-existing ISA devices.

Definition at line 78 of file isa.hh.

Referenced by ISA().

gicv3CpuInterface

std::unique_ptr<BaseISADevice> ArmISA::ISA::gicv3CpuInterface

protected

Definition at line 87 of file isa.hh.

Referenced by getGICv3CPUInterface(), and startup().

haveCrypto

bool ArmISA::ISA::haveCrypto

protected

Definition at line 94 of file isa.hh.

Referenced by initID32(), initID64(), and ISA().

haveGICv3CPUInterface

bool ArmISA::ISA::haveGICv3CPUInterface

protected

Definition at line 96 of file isa.hh.

Referenced by haveGICv3CpuIfc(), readMiscReg(), and startup().

haveLargeAsid64

bool ArmISA::ISA::haveLargeAsid64

protected

Definition at line 95 of file isa.hh.

Referenced by initID64(), ISA(), and setMiscReg().

haveLPAE

bool ArmISA::ISA::haveLPAE

protected

Definition at line 92 of file isa.hh.

Referenced by clear32(), ISA(), and setMiscReg().

haveLSE

bool ArmISA::ISA::haveLSE

protected

Definition at line 99 of file isa.hh.

Referenced by initID64(), and ISA().

havePAN

bool ArmISA::ISA::havePAN

protected

Definition at line 100 of file isa.hh.

Referenced by initID64(), ISA(), and setMiscReg().

haveSecurity

bool ArmISA::ISA::haveSecurity

protected

Definition at line 91 of file isa.hh.

Referenced by clear32(), clear64(), getCurSveVecLenInBits(), initID64(), ISA(), readMiscReg(), and setMiscReg().

haveSVE

bool ArmISA::ISA::haveSVE

protected

Definition at line 98 of file isa.hh.

Referenced by initID64(), ISA(), readMiscReg(), and setMiscReg().

haveVirtualization

bool ArmISA::ISA::haveVirtualization

protected

Definition at line 93 of file isa.hh.

Referenced by clear64(), getCurSveVecLenInBits(), initID64(), ISA(), readMiscReg(), and setMiscReg().

highestELIs64

bool ArmISA::ISA::highestELIs64

protected

Definition at line 90 of file isa.hh.

Referenced by initID32(), ISA(), and setMiscReg().

impdefAsNop

bool ArmISA::ISA::impdefAsNop

protected

If true, accesses to IMPLEMENTATION DEFINED registers are treated as NOP hence not causing UNDEFINED INSTRUCTION.

Definition at line 109 of file isa.hh.

intRegMap

const IntRegIndex* ArmISA::ISA::intRegMap

protected

Definition at line 412 of file isa.hh.

lookUpMiscReg

std::vector< struct ISA::MiscRegLUTEntry > ArmISA::ISA::lookUpMiscReg

staticprotected

Metadata table accessible via the value of the register.

Definition at line 136 of file isa.hh.

Referenced by ISA(), readMiscRegNoEffect(), and setMiscRegNoEffect().

miscRegs

RegVal ArmISA::ISA::miscRegs[NumMiscRegs]

protected

Definition at line 411 of file isa.hh.

Referenced by clear(), clear32(), clear64(), getCurSveVecLenInBits(), initID32(), initID64(), ISA(), readMiscReg(), readMiscRegNoEffect(), setMiscReg(), and setMiscRegNoEffect().

physAddrRange

uint8_t ArmISA::ISA::physAddrRange

protected

Definition at line 97 of file isa.hh.

Referenced by initID64(), and ISA().

pmu

BaseISADevice* ArmISA::ISA::pmu

protected

Definition at line 81 of file isa.hh.

Referenced by ISA(), readMiscReg(), setMiscReg(), and startup().

sveVL

unsigned ArmISA::ISA::sveVL

protected

SVE vector length in quadwords.

Definition at line 103 of file isa.hh.

Referenced by getCurSveVecLenInBits(), initID64(), and ISA().

system

ArmSystem* ArmISA::ISA::system

protected

Definition at line 71 of file isa.hh.

Referenced by clear(), clear32(), clear64(), getGenericTimer(), ISA(), readMiscReg(), and startup().

timer

std::unique_ptr<BaseISADevice> ArmISA::ISA::timer

protected

Definition at line 84 of file isa.hh.

Referenced by getGenericTimer().

---

The documentation for this class was generated from the following files:

• arch/arm/isa.hh
• arch/arm/isa.cc
• arch/arm/miscregs.cc