gem5  v20.0.0.3
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
Gcn3ISA::Inst_SMEM Class Reference

#include <op_encodings.hh>

Inheritance diagram for Gcn3ISA::Inst_SMEM:
Gcn3ISA::GCN3GPUStaticInst GPUStaticInst Gcn3ISA::Inst_SMEM__S_ATC_PROBE Gcn3ISA::Inst_SMEM__S_ATC_PROBE_BUFFER Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORD Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16 Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2 Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4 Gcn3ISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8 Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORD Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2 Gcn3ISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4 Gcn3ISA::Inst_SMEM__S_DCACHE_INV Gcn3ISA::Inst_SMEM__S_DCACHE_INV_VOL Gcn3ISA::Inst_SMEM__S_DCACHE_WB Gcn3ISA::Inst_SMEM__S_DCACHE_WB_VOL Gcn3ISA::Inst_SMEM__S_LOAD_DWORD Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16 Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2 Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4 Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8 Gcn3ISA::Inst_SMEM__S_MEMREALTIME Gcn3ISA::Inst_SMEM__S_MEMTIME Gcn3ISA::Inst_SMEM__S_STORE_DWORD Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2 Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4

Public Member Functions

 Inst_SMEM (InFmt_SMEM *, const std::string &opcode)
 
 ~Inst_SMEM ()
 
int instSize () const override
 
void generateDisassembly () override
 
bool isScalarRegister (int opIdx) override
 
bool isVectorRegister (int opIdx) override
 
int getRegisterIndex (int opIdx, GPUDynInstPtr gpuDynInst) override
 
- Public Member Functions inherited from Gcn3ISA::GCN3GPUStaticInst
 GCN3GPUStaticInst (const std::string &opcode)
 
 ~GCN3GPUStaticInst ()
 
bool isFlatScratchRegister (int opIdx) override
 
bool isExecMaskRegister (int opIdx) override
 
bool isSrcOperand (int opIdx) override
 
bool isDstOperand (int opIdx) override
 
int getOperandSize (int opIdx) override
 
int coalescerTokenCount () const override
 Return the number of tokens needed by the coalescer. More...
 
ScalarRegU32 srcLiteral () const override
 
- Public Member Functions inherited from GPUStaticInst
 GPUStaticInst (const std::string &opcode)
 
void instAddr (int inst_addr)
 
int instAddr () const
 
int nextInstAddr () const
 
void instNum (int num)
 
int instNum ()
 
void ipdInstNum (int num)
 
int ipdInstNum () const
 
virtual void execute (GPUDynInstPtr gpuDynInst)=0
 
const std::string & disassemble ()
 
virtual int getNumOperands ()=0
 
virtual bool isCondRegister (int operandIndex)=0
 
virtual int numDstRegOperands ()=0
 
virtual int numSrcRegOperands ()=0
 
virtual bool isValid () const =0
 
bool isALU () const
 
bool isBranch () const
 
bool isNop () const
 
bool isReturn () const
 
bool isUnconditionalJump () const
 
bool isSpecialOp () const
 
bool isWaitcnt () const
 
bool isBarrier () const
 
bool isMemFence () const
 
bool isMemRef () const
 
bool isFlat () const
 
bool isLoad () const
 
bool isStore () const
 
bool isAtomic () const
 
bool isAtomicNoRet () const
 
bool isAtomicRet () const
 
bool isScalar () const
 
bool readsSCC () const
 
bool writesSCC () const
 
bool readsVCC () const
 
bool writesVCC () const
 
bool isAtomicAnd () const
 
bool isAtomicOr () const
 
bool isAtomicXor () const
 
bool isAtomicCAS () const
 
bool isAtomicExch () const
 
bool isAtomicAdd () const
 
bool isAtomicSub () const
 
bool isAtomicInc () const
 
bool isAtomicDec () const
 
bool isAtomicMax () const
 
bool isAtomicMin () const
 
bool isArgLoad () const
 
bool isGlobalMem () const
 
bool isLocalMem () const
 
bool isArgSeg () const
 
bool isGlobalSeg () const
 
bool isGroupSeg () const
 
bool isKernArgSeg () const
 
bool isPrivateSeg () const
 
bool isReadOnlySeg () const
 
bool isSpillSeg () const
 
bool isWorkitemScope () const
 
bool isWavefrontScope () const
 
bool isWorkgroupScope () const
 
bool isDeviceScope () const
 
bool isSystemScope () const
 
bool isNoScope () const
 
bool isRelaxedOrder () const
 
bool isAcquire () const
 
bool isRelease () const
 
bool isAcquireRelease () const
 
bool isNoOrder () const
 
bool isGloballyCoherent () const
 Coherence domain of a memory instruction. More...
 
bool isSystemCoherent () const
 
virtual void initiateAcc (GPUDynInstPtr gpuDynInst)
 
virtual void completeAcc (GPUDynInstPtr gpuDynInst)
 
virtual uint32_t getTargetPc ()
 
void setFlag (Flags flag)
 
virtual void execLdAcq (GPUDynInstPtr gpuDynInst)
 
virtual void execSt (GPUDynInstPtr gpuDynInst)
 
virtual void execAtomic (GPUDynInstPtr gpuDynInst)
 
virtual void execAtomicAcq (GPUDynInstPtr gpuDynInst)
 

Protected Member Functions

template<int N>
void initMemRead (GPUDynInstPtr gpuDynInst)
 initiate a memory read access for N dwords More...
 
template<int N>
void initMemWrite (GPUDynInstPtr gpuDynInst)
 initiate a memory write access for N dwords More...
 
void calcAddr (GPUDynInstPtr gpuDynInst, ConstScalarOperandU64 &addr, ScalarRegU32 offset)
 
- Protected Member Functions inherited from Gcn3ISA::GCN3GPUStaticInst
void panicUnimplemented () const
 

Protected Attributes

InFmt_SMEM instData
 
InFmt_SMEM_1 extData
 
- Protected Attributes inherited from Gcn3ISA::GCN3GPUStaticInst
ScalarRegU32 _srcLiteral
 if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here More...
 
- Protected Attributes inherited from GPUStaticInst
const std::string opcode
 
std::string disassembly
 
int _instNum
 
int _instAddr
 
int _ipdInstNum
 Identifier of the immediate post-dominator instruction. More...
 
std::bitset< Num_Flags > _flags
 

Additional Inherited Members

- Public Attributes inherited from GPUStaticInst
Enums::StorageClassType executed_as
 
- Static Public Attributes inherited from GPUStaticInst
static uint64_t dynamic_id_count
 

Detailed Description

Definition at line 156 of file op_encodings.hh.

Constructor & Destructor Documentation

◆ Inst_SMEM()

Gcn3ISA::Inst_SMEM::Inst_SMEM ( InFmt_SMEM iFmt,
const std::string &  opcode 
)

◆ ~Inst_SMEM()

Gcn3ISA::Inst_SMEM::~Inst_SMEM ( )

Definition at line 572 of file op_encodings.cc.

Member Function Documentation

◆ calcAddr()

void Gcn3ISA::Inst_SMEM::calcAddr ( GPUDynInstPtr  gpuDynInst,
ConstScalarOperandU64 addr,
ScalarRegU32  offset 
)
inlineprotected

◆ generateDisassembly()

void Gcn3ISA::Inst_SMEM::generateDisassembly ( )
overridevirtual

◆ getRegisterIndex()

int Gcn3ISA::Inst_SMEM::getRegisterIndex ( int  opIdx,
GPUDynInstPtr  gpuDynInst 
)
overridevirtual

◆ initMemRead()

template<int N>
void Gcn3ISA::Inst_SMEM::initMemRead ( GPUDynInstPtr  gpuDynInst)
inlineprotected

initiate a memory read access for N dwords

the base address of the cache line where the the last byte of the request will be stored.

if the base cache line address of the last byte is greater than the address of the first byte then we have a misaligned access.

Definition at line 175 of file op_encodings.hh.

References Packet::dataStatic(), MemCmd::ReadReq, roundDown(), Request::splitOnVaddr(), and MipsISA::vaddr.

◆ initMemWrite()

template<int N>
void Gcn3ISA::Inst_SMEM::initMemWrite ( GPUDynInstPtr  gpuDynInst)
inlineprotected

initiate a memory write access for N dwords

the base address of the cache line where the the last byte of the request will be stored.

if the base cache line address of the last byte is greater than the address of the first byte then we have a misaligned access.

Definition at line 226 of file op_encodings.hh.

References Packet::dataStatic(), MemCmd::ReadReq, roundDown(), Request::splitOnVaddr(), MipsISA::vaddr, and MemCmd::WriteReq.

◆ instSize()

int Gcn3ISA::Inst_SMEM::instSize ( ) const
overridevirtual

Implements GPUStaticInst.

Definition at line 577 of file op_encodings.cc.

◆ isScalarRegister()

bool Gcn3ISA::Inst_SMEM::isScalarRegister ( int  opIdx)
overridevirtual

◆ isVectorRegister()

bool Gcn3ISA::Inst_SMEM::isVectorRegister ( int  opIdx)
overridevirtual

Reimplemented from Gcn3ISA::GCN3GPUStaticInst.

Definition at line 642 of file op_encodings.cc.

References GPUStaticInst::getNumOperands().

Member Data Documentation

◆ extData

InFmt_SMEM_1 Gcn3ISA::Inst_SMEM::extData
protected

◆ instData

InFmt_SMEM Gcn3ISA::Inst_SMEM::instData
protected

The documentation for this class was generated from the following files:

Generated on Fri Jul 3 2020 15:53:34 for gem5 by doxygen 1.8.13