gem5  v20.0.0.3
faults.hh
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37 
38 #ifndef __ARCH_X86_FAULTS_HH__
39 #define __ARCH_X86_FAULTS_HH__
40 
41 #include <string>
42 
43 #include "arch/x86/tlb.hh"
44 #include "base/bitunion.hh"
45 #include "base/logging.hh"
46 #include "sim/faults.hh"
47 
48 namespace X86ISA
49 {
50  // Base class for all x86 "faults" where faults is in the m5 sense
51  class X86FaultBase : public FaultBase
52  {
53  protected:
54  const char * faultName;
55  const char * mnem;
56  uint8_t vector;
57  uint64_t errorCode;
58 
59  X86FaultBase(const char * _faultName, const char * _mnem,
60  const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
61  : faultName(_faultName), mnem(_mnem),
62  vector(_vector), errorCode(_errorCode)
63  {
64  }
65 
66  const char * name() const
67  {
68  return faultName;
69  }
70 
71  virtual bool isBenign()
72  {
73  return true;
74  }
75 
76  virtual const char * mnemonic() const
77  {
78  return mnem;
79  }
80 
81  virtual bool isSoft()
82  {
83  return false;
84  }
85 
86  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
88 
89  virtual std::string describe() const;
90 
91  public:
97  virtual uint8_t getVector() const { return vector; }
98  };
99 
100  // Base class for x86 faults which behave as if the underlying instruction
101  // didn't happen.
102  class X86Fault : public X86FaultBase
103  {
104  protected:
105  X86Fault(const char * name, const char * mnem,
106  const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
107  : X86FaultBase(name, mnem, vector, _errorCode)
108  {}
109  };
110 
111  // Base class for x86 traps which behave as if the underlying instruction
112  // completed.
113  class X86Trap : public X86FaultBase
114  {
115  protected:
116  X86Trap(const char * name, const char * mnem,
117  const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
118  : X86FaultBase(name, mnem, vector, _errorCode)
119  {}
120 
121  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
123  };
124 
125  // Base class for x86 aborts which seem to be catastrophic failures.
126  class X86Abort : public X86FaultBase
127  {
128  protected:
129  X86Abort(const char * name, const char * mnem,
130  const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
131  : X86FaultBase(name, mnem, vector, _errorCode)
132  {}
133 
134  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
136  };
137 
138  // Base class for x86 interrupts.
139  class X86Interrupt : public X86FaultBase
140  {
141  protected:
142  X86Interrupt(const char * name, const char * mnem,
143  const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1)
144  : X86FaultBase(name, mnem, _vector, _errorCode)
145  {}
146  };
147 
148  class UnimpInstFault : public FaultBase
149  {
150  public:
151  const char * name() const
152  {
153  return "unimplemented_micro";
154  }
155 
156  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
158  {
159  panic("Unimplemented instruction!");
160  }
161  };
162 
163  // Below is a summary of the interrupt/exception information in the
164  // architecture manuals.
165 
166  // Class | Type | vector | Cause | mnem
167  //------------------------------------------------------------------------
168  //Contrib Fault 0 Divide Error #DE
169  //Benign Either 1 Debug #DB
170  //Benign Interrupt 2 Non-Maskable-Interrupt #NMI
171  //Benign Trap 3 Breakpoint #BP
172  //Benign Trap 4 Overflow #OF
173  //Benign Fault 5 Bound-Range #BR
174  //Benign Fault 6 Invalid-Opcode #UD
175  //Benign Fault 7 Device-Not-Available #NM
176  //Benign Abort 8 Double-Fault #DF
177  // 9 Coprocessor-Segment-Overrun
178  //Contrib Fault 10 Invalid-TSS #TS
179  //Contrib Fault 11 Segment-Not-Present #NP
180  //Contrib Fault 12 Stack #SS
181  //Contrib Fault 13 General-Protection #GP
182  //Either Fault 14 Page-Fault #PF
183  // 15 Reserved
184  //Benign Fault 16 x87 Floating-Point Exception Pending #MF
185  //Benign Fault 17 Alignment-Check #AC
186  //Benign Abort 18 Machine-Check #MC
187  //Benign Fault 19 SIMD Floating-Point #XF
188  // 20-29 Reserved
189  //Contrib ? 30 Security Exception #SX
190  // 31 Reserved
191  //Benign Interrupt 0-255 External Interrupts #INTR
192  //Benign Interrupt 0-255 Software Interrupts INTn
193 
194  // Note that
195  class DivideError : public X86Fault
196  {
197  public:
199  X86Fault("Divide-Error", "#DE", 0)
200  {}
201  };
202 
204  {
205  public:
207  X86FaultBase("Debug", "#DB", 1)
208  {}
209  };
210 
212  {
213  public:
214  NonMaskableInterrupt(uint8_t _vector) :
215  X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector)
216  {}
217  };
218 
219  class Breakpoint : public X86Trap
220  {
221  public:
223  X86Trap("Breakpoint", "#BP", 3)
224  {}
225  };
226 
227  class OverflowTrap : public X86Trap
228  {
229  public:
231  X86Trap("Overflow", "#OF", 4)
232  {}
233  };
234 
235  class BoundRange : public X86Fault
236  {
237  public:
239  X86Fault("Bound-Range", "#BR", 5)
240  {}
241  };
242 
243  class InvalidOpcode : public X86Fault
244  {
245  public:
247  X86Fault("Invalid-Opcode", "#UD", 6)
248  {}
249 
250  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
252  };
253 
255  {
256  public:
258  X86Fault("Device-Not-Available", "#NM", 7)
259  {}
260  };
261 
262  class DoubleFault : public X86Abort
263  {
264  public:
266  X86Abort("Double-Fault", "#DF", 8, 0)
267  {}
268  };
269 
270  class InvalidTSS : public X86Fault
271  {
272  public:
273  InvalidTSS(uint32_t _errorCode) :
274  X86Fault("Invalid-TSS", "#TS", 10, _errorCode)
275  {}
276  };
277 
279  {
280  public:
281  SegmentNotPresent(uint32_t _errorCode) :
282  X86Fault("Segment-Not-Present", "#NP", 11, _errorCode)
283  {}
284  };
285 
286  class StackFault : public X86Fault
287  {
288  public:
289  StackFault(uint32_t _errorCode) :
290  X86Fault("Stack", "#SS", 12, _errorCode)
291  {}
292  };
293 
295  {
296  public:
297  GeneralProtection(uint32_t _errorCode) :
298  X86Fault("General-Protection", "#GP", 13, _errorCode)
299  {}
300  };
301 
302  class PageFault : public X86Fault
303  {
304  protected:
305  BitUnion32(PageFaultErrorCode)
306  Bitfield<0> present;
307  Bitfield<1> write;
308  Bitfield<2> user;
309  Bitfield<3> reserved;
310  Bitfield<4> fetch;
311  EndBitUnion(PageFaultErrorCode)
312 
313  Addr addr;
314 
315  public:
316  PageFault(Addr _addr, uint32_t _errorCode) :
317  X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr)
318  {}
319 
320  PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
321  bool user, bool reserved) :
322  X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr)
323  {
324  PageFaultErrorCode code = 0;
325  code.present = present;
326  code.write = (mode == BaseTLB::Write);
327  code.user = user;
328  code.reserved = reserved;
329  code.fetch = (mode == BaseTLB::Execute);
330  errorCode = code;
331  }
332 
333  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
335 
336  virtual std::string describe() const;
337  };
338 
340  {
341  public:
343  X86Fault("x87 Floating-Point Exception Pending", "#MF", 16)
344  {}
345  };
346 
347  class AlignmentCheck : public X86Fault
348  {
349  public:
351  X86Fault("Alignment-Check", "#AC", 17, 0)
352  {}
353  };
354 
355  class MachineCheck : public X86Abort
356  {
357  public:
359  X86Abort("Machine-Check", "#MC", 18)
360  {}
361  };
362 
364  {
365  public:
367  X86Fault("SIMD Floating-Point", "#XF", 19)
368  {}
369  };
370 
372  {
373  public:
375  X86FaultBase("Security Exception", "#SX", 30)
376  {}
377  };
378 
380  {
381  public:
382  ExternalInterrupt(uint8_t _vector) :
383  X86Interrupt("External Interrupt", "#INTR", _vector)
384  {}
385  };
386 
388  {
389  public:
391  X86Interrupt("System Management Interrupt", "#SMI", 0)
392  {}
393  };
394 
396  {
397  public:
398  InitInterrupt(uint8_t _vector) :
399  X86Interrupt("INIT Interrupt", "#INIT", _vector)
400  {}
401 
402  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
404  };
405 
407  {
408  public:
409  StartupInterrupt(uint8_t _vector) :
410  X86Interrupt("Startup Interrupt", "#SIPI", _vector)
411  {}
412 
413  void invoke(ThreadContext * tc, const StaticInstPtr &inst =
415  };
416 
418  {
419  public:
420  SoftwareInterrupt(uint8_t _vector) :
421  X86Interrupt("Software Interrupt", "#INTR", _vector)
422  {}
423 
424  bool isSoft()
425  {
426  return true;
427  }
428  };
429 }
430 
431 #endif // __ARCH_X86_FAULTS_HH__
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:163
PageFault(Addr _addr, bool present, BaseTLB::Mode mode, bool user, bool reserved)
Definition: faults.hh:320
GeneralProtection(uint32_t _errorCode)
Definition: faults.hh:297
virtual uint8_t getVector() const
Get the vector of an interrupt.
Definition: faults.hh:97
X86Interrupt(const char *name, const char *mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:142
Bitfield< 1 > write
Definition: faults.hh:307
Bitfield< 3 > reserved
Definition: faults.hh:309
X86Fault(const char *name, const char *mnem, const uint8_t vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:105
EndBitUnion(TriggerIntMessage) namespace DeliveryMode
Definition: intmessage.hh:49
InitInterrupt(uint8_t _vector)
Definition: faults.hh:398
Bitfield< 2 > user
Definition: faults.hh:308
X86Abort(const char *name, const char *mnem, const uint8_t vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:129
Bitfield< 7 > present
Definition: misc.hh:992
PageFault(Addr _addr, uint32_t _errorCode)
Definition: faults.hh:316
Bitfield< 4, 0 > mode
uint64_t errorCode
Definition: faults.hh:57
Bitfield< 4 > fetch
Definition: faults.hh:310
ThreadContext is the external interface to all thread state for anything outside of the CPU...
const char * faultName
Definition: faults.hh:54
virtual bool isSoft()
Definition: faults.hh:81
BitUnion32(TriggerIntMessage) Bitfield< 7
NonMaskableInterrupt(uint8_t _vector)
Definition: faults.hh:214
X86FaultBase(const char *_faultName, const char *_mnem, const uint8_t _vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:59
InvalidTSS(uint32_t _errorCode)
Definition: faults.hh:273
const char * name() const
Definition: faults.hh:66
virtual bool isBenign()
Definition: faults.hh:71
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
Mode
Definition: tlb.hh:57
const char * mnem
Definition: faults.hh:55
virtual std::string describe() const
Definition: faults.cc:97
virtual const char * mnemonic() const
Definition: faults.hh:76
This is exposed globally, independent of the ISA.
Definition: acpi.hh:55
X86Trap(const char *name, const char *mnem, const uint8_t vector, uint64_t _errorCode=(uint64_t) -1)
Definition: faults.hh:116
SegmentNotPresent(uint32_t _errorCode)
Definition: faults.hh:281
ExternalInterrupt(uint8_t _vector)
Definition: faults.hh:382
SoftwareInterrupt(uint8_t _vector)
Definition: faults.hh:420
StackFault(uint32_t _errorCode)
Definition: faults.hh:289
void invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr)
Definition: faults.hh:156
static StaticInstPtr nullStaticInstPtr
Pointer to a statically allocated "null" instruction object.
Definition: static_inst.hh:225
void invoke(ThreadContext *tc, const StaticInstPtr &inst=StaticInst::nullStaticInstPtr)
Definition: faults.cc:54
Bitfield< 3 > addr
Definition: types.hh:79
const char * name() const
Definition: faults.hh:151
StartupInterrupt(uint8_t _vector)
Definition: faults.hh:409

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