free_list.hh

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#ifndef __CPU_O3_FREE_LIST_HH__
#define __CPU_O3_FREE_LIST_HH__

#include <iostream>
#include <queue>
#include <vector>

#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/regfile.hh"
#include "debug/FreeList.hh"

class SimpleFreeList
{
  private:

    std::queue<PhysRegIdPtr> freeRegs;

  public:

    SimpleFreeList() {};

    void addReg(PhysRegIdPtr reg) { freeRegs.push(reg); }

    template<class InputIt>
    void
    addRegs(InputIt first, InputIt last) {
        std::for_each(first, last, [this](typename InputIt::value_type& reg) {
            this->freeRegs.push(&reg);
        });
    }

    PhysRegIdPtr getReg()
    {
        assert(!freeRegs.empty());
        PhysRegIdPtr free_reg = freeRegs.front();
        freeRegs.pop();
        return free_reg;
    }

    unsigned numFreeRegs() const { return freeRegs.size(); }

    bool hasFreeRegs() const { return !freeRegs.empty(); }
};


class UnifiedFreeList
{
  private:

    const std::string _name;

    SimpleFreeList intList;

    SimpleFreeList floatList;

    SimpleFreeList vecList;

    SimpleFreeList vecElemList;
    SimpleFreeList predList;

    SimpleFreeList ccList;

    PhysRegFile *regFile;

    /*
     * We give UnifiedRenameMap internal access so it can get at the
     * internal per-class free lists and associate those with its
     * per-class rename maps. See UnifiedRenameMap::init().
     */
    friend class UnifiedRenameMap;

  public:
    UnifiedFreeList(const std::string &_my_name, PhysRegFile *_regFile);

    std::string name() const { return _name; };

    SimpleFreeList *getCCList() { return &ccList; }

    PhysRegIdPtr getIntReg() { return intList.getReg(); }

    PhysRegIdPtr getFloatReg() { return floatList.getReg(); }

    PhysRegIdPtr getVecReg() { return vecList.getReg(); }

    PhysRegIdPtr getVecElem() { return vecElemList.getReg(); }

    PhysRegIdPtr getVecPredReg() { return predList.getReg(); }

    PhysRegIdPtr getCCReg() { return ccList.getReg(); }

    void addReg(PhysRegIdPtr freed_reg);

    template<class InputIt>
    void addRegs(InputIt first, InputIt last);

    void addIntReg(PhysRegIdPtr freed_reg) { intList.addReg(freed_reg); }

    void addFloatReg(PhysRegIdPtr freed_reg) { floatList.addReg(freed_reg); }

    void addVecReg(PhysRegIdPtr freed_reg) { vecList.addReg(freed_reg); }

    void addVecElem(PhysRegIdPtr freed_reg) {
        vecElemList.addReg(freed_reg);
    }

    void addVecPredReg(PhysRegIdPtr freed_reg) { predList.addReg(freed_reg); }

    void addCCReg(PhysRegIdPtr freed_reg) { ccList.addReg(freed_reg); }

    bool hasFreeIntRegs() const { return intList.hasFreeRegs(); }

    bool hasFreeFloatRegs() const { return floatList.hasFreeRegs(); }

    bool hasFreeVecRegs() const { return vecList.hasFreeRegs(); }

    bool hasFreeVecElems() const { return vecElemList.hasFreeRegs(); }

    bool hasFreeVecPredRegs() const { return predList.hasFreeRegs(); }

    bool hasFreeCCRegs() const { return ccList.hasFreeRegs(); }

    unsigned numFreeIntRegs() const { return intList.numFreeRegs(); }

    unsigned numFreeFloatRegs() const { return floatList.numFreeRegs(); }

    unsigned numFreeVecRegs() const { return vecList.numFreeRegs(); }

    unsigned numFreeVecElems() const { return vecElemList.numFreeRegs(); }

    unsigned numFreeVecPredRegs() const { return predList.numFreeRegs(); }

    unsigned numFreeCCRegs() const { return ccList.numFreeRegs(); }
};

template<class InputIt>
inline void
UnifiedFreeList::addRegs(InputIt first, InputIt last)
{
    // Are there any registers to add?
    if (first == last)
        return;

    panic_if((first != last) &&
            first->classValue() != (last-1)->classValue(),
            "Attempt to add mixed type regs: %s and %s",
            first->className(),
            (last-1)->className());
    switch (first->classValue()) {
        case IntRegClass:
            intList.addRegs(first, last);
            break;
        case FloatRegClass:
            floatList.addRegs(first, last);
            break;
        case VecRegClass:
            vecList.addRegs(first, last);
            break;
        case VecElemClass:
            vecElemList.addRegs(first, last);
            break;
        case VecPredRegClass:
            predList.addRegs(first, last);
            break;
        case CCRegClass:
            ccList.addRegs(first, last);
            break;
        default:
            panic("Unexpected RegClass (%s)",
                                   first->className());
    }

}

inline void
UnifiedFreeList::addReg(PhysRegIdPtr freed_reg)
{
    DPRINTF(FreeList,"Freeing register %i (%s).\n", freed_reg->index(),
            freed_reg->className());
    //Might want to add in a check for whether or not this register is
    //already in there.  A bit vector or something similar would be useful.
    switch (freed_reg->classValue()) {
        case IntRegClass:
            intList.addReg(freed_reg);
            break;
        case FloatRegClass:
            floatList.addReg(freed_reg);
            break;
        case VecRegClass:
            vecList.addReg(freed_reg);
            break;
        case VecElemClass:
            vecElemList.addReg(freed_reg);
            break;
        case VecPredRegClass:
            predList.addReg(freed_reg);
            break;
        case CCRegClass:
            ccList.addReg(freed_reg);
            break;
        default:
            panic("Unexpected RegClass (%s)",
                                   freed_reg->className());
    }

    // These assert conditions ensure that the number of free
    // registers are not more than the # of total Physical  Registers.
    // If this were false, it would mean that registers
    // have been freed twice, overflowing the free register
    // pool and potentially crashing SMT workloads.
    // ----
    // Comment out for now so as to not potentially break
    // CMP and single-threaded workloads
    // ----
    // assert(freeIntRegs.size() <= numPhysicalIntRegs);
    // assert(freeFloatRegs.size() <= numPhysicalFloatRegs);
}


#endif // __CPU_O3_FREE_LIST_HH__