gem5  v20.1.0.0
htm.hh
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37 
38 #ifndef __ARCH_ARM_HTM_HH__
39 #define __ARCH_ARM_HTM_HH__
40 
47 #include "arch/arm/registers.hh"
48 #include "arch/generic/htm.hh"
49 #include "base/types.hh"
50 
51 namespace ArmISA
52 {
53 
55 {
56  public:
59  {}
60 
61  const static int MAX_HTM_DEPTH = 255;
62 
63  void reset() override;
64  void save(ThreadContext *tc) override;
65  void restore(ThreadContext *tc, HtmFailureFaultCause cause) override;
66 
67  void destinationRegister(RegIndex dest) { rt = dest; }
68  void cancelReason(uint16_t reason) { tcreason = reason; }
69 
70  private:
71  uint8_t rt; // TSTART destination register
72  Addr nPc; // Fallback instruction address
73  std::array<RegVal, NumIntArchRegs> x; // General purpose registers
74  std::array<VecRegContainer, NumVecRegs> z; // Vector registers
75  std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
76  Addr sp; // Stack Pointer at current EL
77  uint16_t tcreason; // TCANCEL reason
78  uint32_t fpcr; // Floating-point Control Register
79  uint32_t fpsr; // Floating-point Status Register
80  uint32_t iccPmrEl1; // Interrupt Controller Interrupt Priority Mask
81  uint8_t nzcv; // Condition flags
82  uint8_t daif;
84 };
85 
86 } // namespace ArmISA
87 
88 #endif
htm.hh
ArmISA::HTMCheckpoint::daif
uint8_t daif
Definition: htm.hh:82
ArmISA::HTMCheckpoint::fpsr
uint32_t fpsr
Definition: htm.hh:79
ArmISA::HTMCheckpoint::MAX_HTM_DEPTH
const static int MAX_HTM_DEPTH
Definition: htm.hh:61
ArmISA::HTMCheckpoint::save
void save(ThreadContext *tc) override
Every ISA implementing HTM support should override the save method.
Definition: htm.cc:66
ArmISA::HTMCheckpoint::HTMCheckpoint
HTMCheckpoint()
Definition: htm.hh:57
ArmISA::HTMCheckpoint::nzcv
uint8_t nzcv
Definition: htm.hh:81
ArmISA::HTMCheckpoint
Definition: htm.hh:54
ArmISA::HTMCheckpoint::pcstateckpt
PCState pcstateckpt
Definition: htm.hh:83
HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:44
ArmISA::HTMCheckpoint::fpcr
uint32_t fpcr
Definition: htm.hh:78
ArmISA
Definition: ccregs.hh:41
ArmISA::HTMCheckpoint::sp
Addr sp
Definition: htm.hh:76
ArmISA::HTMCheckpoint::cancelReason
void cancelReason(uint16_t reason)
Definition: htm.hh:68
ArmISA::HTMCheckpoint::rt
uint8_t rt
Definition: htm.hh:71
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
BaseHTMCheckpoint
Transactional Memory checkpoint.
Definition: htm.hh:129
ArmISA::HTMCheckpoint::x
std::array< RegVal, NumIntArchRegs > x
Definition: htm.hh:73
ArmISA::HTMCheckpoint::destinationRegister
void destinationRegister(RegIndex dest)
Definition: htm.hh:67
ArmISA::HTMCheckpoint::tcreason
uint16_t tcreason
Definition: htm.hh:77
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
ArmISA::HTMCheckpoint::reset
void reset() override
Resets the checkpoint once a transaction has completed.
Definition: htm.cc:42
ArmISA::HTMCheckpoint::p
std::array< VecPredRegContainer, NumVecRegs > p
Definition: htm.hh:75
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
types.hh
RegIndex
uint16_t RegIndex
Definition: types.hh:52
registers.hh
ArmISA::HTMCheckpoint::iccPmrEl1
uint32_t iccPmrEl1
Definition: htm.hh:80
ArmISA::HTMCheckpoint::nPc
Addr nPc
Definition: htm.hh:72
ArmISA::HTMCheckpoint::z
std::array< VecRegContainer, NumVecRegs > z
Definition: htm.hh:74
ArmISA::HTMCheckpoint::restore
void restore(ThreadContext *tc, HtmFailureFaultCause cause) override
Every ISA implementing HTM support should override the restore method.
Definition: htm.cc:93

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