htm.hh

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/*
 * Copyright (c) 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 */
 
#ifndef __ARCH_ARM_HTM_HH__
#define __ARCH_ARM_HTM_HH__
 
#include "arch/arm/registers.hh"
#include "arch/generic/htm.hh"
#include "base/types.hh"
 
namespace ArmISA
{
 
class HTMCheckpoint : public BaseHTMCheckpoint
{
  public:
    HTMCheckpoint()
      : BaseHTMCheckpoint()
    {}
 
    const static int MAX_HTM_DEPTH = 255;
 
    void reset() override;
    void save(ThreadContext *tc) override;
    void restore(ThreadContext *tc, HtmFailureFaultCause cause) override;
 
    void destinationRegister(RegIndex dest) { rt = dest; }
    void cancelReason(uint16_t reason) { tcreason = reason; }
 
  private:
    uint8_t rt; // TSTART destination register
    Addr nPc; // Fallback instruction address
    std::array<RegVal, NumIntArchRegs> x; // General purpose registers
    std::array<VecRegContainer, NumVecRegs> z; // Vector registers
    std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
    Addr sp; // Stack Pointer at current EL
    uint16_t tcreason; // TCANCEL reason
    uint32_t fpcr; // Floating-point Control Register
    uint32_t fpsr; // Floating-point Status Register
    uint32_t iccPmrEl1; // Interrupt Controller Interrupt Priority Mask
    uint8_t nzcv; // Condition flags
    uint8_t daif;
    PCState pcstateckpt;
};
 
} // namespace ArmISA
 
#endif