Definition at line 54 of file htm.hh.
void ArmISA::HTMCheckpoint::reset |
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Resets the checkpoint once a transaction has completed.
The method is bringing up the checkpoint to a known reset state so that it can be reused. ISA specific checkpoints inheriting from this class should override this method so that they can reset their own ISA specific state.
Reimplemented from BaseHTMCheckpoint.
Definition at line 42 of file htm.cc.
References daif, fpcr, fpsr, ArmISA::i, iccPmrEl1, nPc, ArmISA::NumVecPredRegs, ArmISA::NumVecRegs, nzcv, p, pcstateckpt, BaseHTMCheckpoint::reset(), rt, sp, tcreason, x, and z.
Every ISA implementing HTM support should override the restore method.
This is called once a transaction gets aborted and the architectural state needs to be reverted. This will restore the checkpointed arch state.
- Parameters
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tc | thread context to be restored |
cause | the reason why the transaction has been aborted |
Reimplemented from BaseHTMCheckpoint.
Definition at line 93 of file htm.cc.
References bits(), ArmISA::daif, EXCEPTION, EXPLICIT, ArmISA::INTREG_SPX, MEMORY, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_NZCV, ArmISA::n, NEST, ArmISA::NumIntArchRegs, ArmISA::NumVecPredRegs, ArmISA::NumVecRegs, OTHER, MipsISA::p, panic, ThreadContext::pcState(), replaceBits(), BaseHTMCheckpoint::restore(), ArmISA::rt, ThreadContext::setIntReg(), ThreadContext::setMiscReg(), ThreadContext::setVecPredReg(), ThreadContext::setVecReg(), SIZE, ArmISA::sp, VecPredRegClass, VecRegClass, RiscvISA::x, and ArmISA::z.
Every ISA implementing HTM support should override the save method.
This is called once a transaction starts and the architectural state needs to be saved. This will checkpoint the arch state.
- Parameters
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tc | thread context state to be saved |
Reimplemented from BaseHTMCheckpoint.
Definition at line 66 of file htm.cc.
References ArmISA::daif, ArmISA::INTREG_SPX, ArmISA::MISCREG_DAIF, ArmISA::MISCREG_FPCR, ArmISA::MISCREG_FPSR, ArmISA::MISCREG_NZCV, ArmISA::n, ArmISA::NumIntArchRegs, ArmISA::NumVecPredRegs, ArmISA::NumVecRegs, MipsISA::p, ThreadContext::pcState(), ThreadContext::readIntReg(), ThreadContext::readMiscReg(), ThreadContext::readVecPredReg(), ThreadContext::readVecReg(), BaseHTMCheckpoint::save(), ArmISA::sp, VecPredRegClass, VecRegClass, RiscvISA::x, and ArmISA::z.